[mirror_edk2.git] / ArmPlatformPkg / ArmPlatformPkg.dec

#/** @file\r
#\r
#  Copyright (c) 2011-2018, ARM Limited. All rights reserved.\r
#  Copyright (c) 2015, Intel Corporation. All rights reserved.\r
#\r
#  This program and the accompanying materials\r
#  are licensed and made available under the terms and conditions of the BSD License\r
#  which accompanies this distribution.  The full text of the license may be found at\r
#  http://opensource.org/licenses/bsd-license.php\r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#**/\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = ArmPlatformPkg\r
  PACKAGE_GUID                   = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r
  PACKAGE_VERSION                = 0.1\r
\r
################################################################################\r
#\r
# Include Section - list of Include Paths that are provided by this package.\r
#                   Comments are used for Keywords and Module Types.\r
#\r
# Supported Module Types:\r
#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
#\r
################################################################################\r
[Includes.common]\r
  Include                        # Root include for the package\r
\r
[LibraryClasses]\r
  ArmPlatformLib|Include/Library/ArmPlatformLib.h\r
  LcdHwLib|Include/Library/LcdHwLib.h\r
  LcdPlatformLib|Include/Library/LcdPlatformLib.h\r
  NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h\r
  PL011UartLib|Include/Library/PL011UartLib.h\r
\r
[Guids.common]\r
  gArmPlatformTokenSpaceGuid   = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
\r
[PcdsFeatureFlag.common]\r
  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r
\r
  gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r
\r
  # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r
  # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
  gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r
\r
[PcdsFixedAtBuild.common]\r
  gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r
  gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
\r
  # Stack for CPU Cores in Non Secure Mode\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r
  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r
\r
  # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r
\r
  #\r
  # ARM Primecells\r
  #\r
\r
  ## SP805 Watchdog\r
  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r
  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r
\r
  ## PL011 UART\r
  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r
  gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r
  gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r
  gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F\r
  gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E\r
\r
  ## PL011 Serial Debug UART\r
  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030\r
  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031\r
  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032\r
\r
  ## PL061 GPIO\r
  gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r
\r
  ## PL111 Lcd & HdLcd\r
  gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r
  gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r
\r
  ## Default size for display modes upto 1920x1080 (1920 * 1080 * 4 Bytes Per Pixel)\r
  gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x7E9000|UINT32|0x00000043\r
  ## If set, framebuffer memory will be reserved and mapped in the system RAM\r
  gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x00000044\r
\r
  ## PL180 MCI\r
  gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r
  gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r
\r
  # Graphics Output Pixel format\r
  # 0 : PixelRedGreenBlueReserved8BitPerColor\r
  # 1 : PixelBlueGreenRedReserved8BitPerColor\r
  # 2 : PixelBitMask\r
  # Default is set to UEFI console font format PixelBlueGreenRedReserved8BitPerColor\r
  gArmPlatformTokenSpaceGuid.PcdGopPixelFormat|0x00000001|UINT32|0x00000040\r
\r
  ## If set, this will swap settings for HDLCD RED_SELECT and BLUE_SELECT registers\r
  gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect|FALSE|BOOLEAN|0x00000045\r
\r
[PcdsFixedAtBuild.common,PcdsDynamic.common]\r
  ## PL031 RealTimeClock\r
  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
  gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r
\r
  gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033\r
Commit	Line	Data
	1	#/** @file\r
	2	#\r
	3	# Copyright (c) 2011-2018, ARM Limited. All rights reserved.\r
	4	# Copyright (c) 2015, Intel Corporation. All rights reserved.\r
	5	#\r
	6	# This program and the accompanying materials\r
	7	# are licensed and made available under the terms and conditions of the BSD License\r
	8	# which accompanies this distribution. The full text of the license may be found at\r
	9	# http://opensource.org/licenses/bsd-license.php\r
	10	#\r
	11	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	#\r
	14	#**/\r
	15	\r
	16	[Defines]\r
	17	DEC_SPECIFICATION = 0x00010005\r
	18	PACKAGE_NAME = ArmPlatformPkg\r
	19	PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r
	20	PACKAGE_VERSION = 0.1\r
	21	\r
	22	################################################################################\r
	23	#\r
	24	# Include Section - list of Include Paths that are provided by this package.\r
	25	# Comments are used for Keywords and Module Types.\r
	26	#\r
	27	# Supported Module Types:\r
	28	# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
	29	#\r
	30	################################################################################\r
	31	[Includes.common]\r
	32	Include # Root include for the package\r
	33	\r
	34	[LibraryClasses]\r
	35	ArmPlatformLib\|Include/Library/ArmPlatformLib.h\r
	36	LcdHwLib\|Include/Library/LcdHwLib.h\r
	37	LcdPlatformLib\|Include/Library/LcdPlatformLib.h\r
	38	NorFlashPlatformLib\|Include/Library/NorFlashPlatformLib.h\r
	39	PL011UartLib\|Include/Library/PL011UartLib.h\r
	40	\r
	41	[Guids.common]\r
	42	gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
	43	\r
	44	[PcdsFeatureFlag.common]\r
	45	gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores\|FALSE\|BOOLEAN\|0x00000004\r
	46	\r
	47	gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked\|FALSE\|BOOLEAN\|0x0000003C\r
	48	\r
	49	# Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r
	50	# we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
	51	gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices\|FALSE\|BOOLEAN\|0x0000003D\r
	52	\r
	53	[PcdsFixedAtBuild.common]\r
	54	gArmPlatformTokenSpaceGuid.PcdCoreCount\|1\|UINT32\|0x00000039\r
	55	gArmPlatformTokenSpaceGuid.PcdClusterCount\|1\|UINT32\|0x00000038\r
	56	\r
	57	# Stack for CPU Cores in Non Secure Mode\r
	58	gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase\|0\|UINT64\|0x00000009\r
	59	gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize\|0x10000\|UINT32\|0x00000037\r
	60	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize\|0x1000\|UINT32\|0x0000000A\r
	61	\r
	62	# Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
	63	gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize\|0x08000000\|UINT32\|0x00000015\r
	64	\r
	65	#\r
	66	# ARM Primecells\r
	67	#\r
	68	\r
	69	## SP805 Watchdog\r
	70	gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase\|0x0\|UINT32\|0x00000023\r
	71	gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz\|32000\|UINT32\|0x00000021\r
	72	\r
	73	## PL011 UART\r
	74	gArmPlatformTokenSpaceGuid.PL011UartClkInHz\|24000000\|UINT32\|0x0000001F\r
	75	gArmPlatformTokenSpaceGuid.PL011UartInteger\|0\|UINT32\|0x00000020\r
	76	gArmPlatformTokenSpaceGuid.PL011UartFractional\|0\|UINT32\|0x0000002D\r
	77	gArmPlatformTokenSpaceGuid.PL011UartInterrupt\|0x00000000\|UINT32\|0x0000002F\r
	78	gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant\|0\|UINT8\|0x0000003E\r
	79	\r
	80	## PL011 Serial Debug UART\r
	81	gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase\|0x00000000\|UINT64\|0x00000030\r
	82	gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate\|0x00000000\|UINT64\|0x00000031\r
	83	gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz\|0x00000000\|UINT32\|0x00000032\r
	84	\r
	85	## PL061 GPIO\r
	86	gArmPlatformTokenSpaceGuid.PcdPL061GpioBase\|0x0\|UINT32\|0x00000025\r
	87	\r
	88	## PL111 Lcd & HdLcd\r
	89	gArmPlatformTokenSpaceGuid.PcdPL111LcdBase\|0x0\|UINT32\|0x00000026\r
	90	gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase\|0x0\|UINT32\|0x00000027\r
	91	\r
	92	## Default size for display modes upto 1920x1080 (1920 * 1080 * 4 Bytes Per Pixel)\r
	93	gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize\|0x7E9000\|UINT32\|0x00000043\r
	94	## If set, framebuffer memory will be reserved and mapped in the system RAM\r
	95	gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase\|0x0\|UINT64\|0x00000044\r
	96	\r
	97	## PL180 MCI\r
	98	gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress\|0x00000000\|UINT32\|0x00000028\r
	99	gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress\|0x00000000\|UINT32\|0x00000029\r
	100	\r
	101	# Graphics Output Pixel format\r
	102	# 0 : PixelRedGreenBlueReserved8BitPerColor\r
	103	# 1 : PixelBlueGreenRedReserved8BitPerColor\r
	104	# 2 : PixelBitMask\r
	105	# Default is set to UEFI console font format PixelBlueGreenRedReserved8BitPerColor\r
	106	gArmPlatformTokenSpaceGuid.PcdGopPixelFormat\|0x00000001\|UINT32\|0x00000040\r
	107	\r
	108	## If set, this will swap settings for HDLCD RED_SELECT and BLUE_SELECT registers\r
	109	gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect\|FALSE\|BOOLEAN\|0x00000045\r
	110	\r
	111	[PcdsFixedAtBuild.common,PcdsDynamic.common]\r
	112	## PL031 RealTimeClock\r
	113	gArmPlatformTokenSpaceGuid.PcdPL031RtcBase\|0x0\|UINT32\|0x00000024\r
	114	gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy\|300000000\|UINT32\|0x00000022\r
	115	\r
	116	gArmPlatformTokenSpaceGuid.PcdWatchdogCount\|0x0\|UINT32\|0x00000033\r