]>
Commit | Line | Data |
---|---|---|
1 | #\r | |
2 | # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r | |
3 | # \r | |
4 | # This program and the accompanying materials \r | |
5 | # are licensed and made available under the terms and conditions of the BSD License \r | |
6 | # which accompanies this distribution. The full text of the license may be found at \r | |
7 | # http://opensource.org/licenses/bsd-license.php\r | |
8 | #\r | |
9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | #\r | |
12 | #\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
15 | #include <Base.h>\r | |
16 | #include <Library/PcdLib.h>\r | |
17 | #include <AutoGen.h>\r | |
18 | \r | |
19 | #include <Chipset/ArmCortexA9.h>\r | |
20 | \r | |
21 | .text\r | |
22 | .align 2\r | |
23 | \r | |
24 | GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r | |
25 | GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r | |
26 | GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r | |
27 | \r | |
28 | GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r | |
29 | GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r | |
30 | \r | |
31 | # IN None\r | |
32 | # OUT r0 = SCU Base Address\r | |
33 | ASM_PFX(ArmGetScuBaseAddress):\r | |
34 | # Read Configuration Base Address Register. ArmCBar cannot be called to get\r | |
35 | # the Configuration BAR as a stack is not necessary setup. The SCU is at the\r | |
36 | # offset 0x0000 from the Private Memory Region.\r | |
37 | mrc p15, 4, r0, c15, c0, 0\r | |
38 | bx lr\r | |
39 | \r | |
40 | //UINTN\r | |
41 | //ArmPlatformGetPrimaryCoreMpId (\r | |
42 | // VOID\r | |
43 | // );\r | |
44 | ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r | |
45 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)\r | |
46 | ldr r0, [r0]\r | |
47 | bx lr\r | |
48 | \r | |
49 | # IN None\r | |
50 | # OUT r0 = number of cores present in the system\r | |
51 | ASM_PFX(ArmGetCpuCountPerCluster):\r | |
52 | stmfd SP!, {r1-r2}\r | |
53 | \r | |
54 | # Read CP15 MIDR\r | |
55 | mrc p15, 0, r1, c0, c0, 0\r | |
56 | \r | |
57 | # Check if the CPU is A15\r | |
58 | mov r1, r1, LSR #4\r | |
59 | LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)\r | |
60 | and r1, r1, r0\r | |
61 | \r | |
62 | LoadConstantToReg (ARM_CPU_TYPE_A15, r0)\r | |
63 | cmp r1, r0\r | |
64 | beq _Read_cp15_reg\r | |
65 | \r | |
66 | _CPU_is_not_A15:\r | |
67 | mov r2, lr @ Save link register\r | |
68 | bl ArmGetScuBaseAddress @ Read SCU Base Address\r | |
69 | mov lr, r2 @ Restore link register val\r | |
70 | ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count\r | |
71 | b _Return\r | |
72 | \r | |
73 | _Read_cp15_reg:\r | |
74 | mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count\r | |
75 | lsr r0, #24\r | |
76 | \r | |
77 | _Return:\r | |
78 | and r0, r0, #3\r | |
79 | # Add '1' to the number of CPU on the Cluster\r | |
80 | add r0, r0, #1\r | |
81 | ldmfd SP!, {r1-r2}\r | |
82 | bx lr\r | |
83 | \r | |
84 | //UINTN\r | |
85 | //ArmPlatformIsPrimaryCore (\r | |
86 | // IN UINTN MpId\r | |
87 | // );\r | |
88 | ASM_PFX(ArmPlatformIsPrimaryCore):\r | |
89 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r | |
90 | ldr r1, [r1]\r | |
91 | and r0, r0, r1\r | |
92 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r | |
93 | ldr r1, [r1]\r | |
94 | cmp r0, r1\r | |
95 | moveq r0, #1\r | |
96 | movne r0, #0\r | |
97 | bx lr\r | |
98 | \r | |
99 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r |