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1 | /** @file\r | |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | *\r | |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include <Library/ArmGicLib.h>\r | |
16 | #include <Library/ArmMPCoreMailBoxLib.h>\r | |
17 | #include <Chipset/ArmV7.h>\r | |
18 | \r | |
19 | #include "PrePeiCore.h"\r | |
20 | \r | |
21 | /*\r | |
22 | * This is the main function for secondary cores. They loop around until a non Null value is written to\r | |
23 | * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r | |
24 | * Note:The secondary cores, while executing secondary_main, assumes that:\r | |
25 | * : SGI 0 is configured as Non-secure interrupt\r | |
26 | * : Priority Mask is configured to allow SGI 0\r | |
27 | * : Interrupt Distributor and CPU interfaces are enabled\r | |
28 | *\r | |
29 | */\r | |
30 | VOID\r | |
31 | EFIAPI\r | |
32 | SecondaryMain (\r | |
33 | IN UINTN MpId\r | |
34 | )\r | |
35 | {\r | |
36 | // Function pointer to Secondary Core entry point\r | |
37 | VOID (*secondary_start)(VOID);\r | |
38 | UINTN secondary_entry_addr=0;\r | |
39 | \r | |
40 | // Clear Secondary cores MailBox\r | |
41 | ArmClearMPCoreMailbox();\r | |
42 | \r | |
43 | while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r | |
44 | ArmCallWFI();\r | |
45 | // Acknowledge the interrupt and send End of Interrupt signal.\r | |
46 | ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r | |
47 | }\r | |
48 | \r | |
49 | secondary_start = (VOID (*)())secondary_entry_addr;\r | |
50 | \r | |
51 | // Jump to secondary core entry point.\r | |
52 | secondary_start();\r | |
53 | \r | |
54 | // The secondaries shouldn't reach here\r | |
55 | ASSERT(FALSE);\r | |
56 | }\r | |
57 | \r | |
58 | VOID\r | |
59 | EFIAPI\r | |
60 | PrimaryMain (\r | |
61 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r | |
62 | )\r | |
63 | {\r | |
64 | EFI_SEC_PEI_HAND_OFF SecCoreData;\r | |
65 | UINTN PpiListSize;\r | |
66 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
67 | UINTN TemporaryRamBase;\r | |
68 | UINTN TemporaryRamSize;\r | |
69 | \r | |
70 | CreatePpiList (&PpiListSize, &PpiList);\r | |
71 | \r | |
72 | // Enable the GIC Distributor\r | |
73 | ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r | |
74 | \r | |
75 | // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r | |
76 | if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r | |
77 | // Sending SGI to all the Secondary CPU interfaces\r | |
78 | ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r | |
79 | }\r | |
80 | \r | |
81 | // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r | |
82 | // the base of the primary core stack\r | |
83 | PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r | |
84 | TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;\r | |
85 | TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r | |
86 | \r | |
87 | //\r | |
88 | // Bind this information into the SEC hand-off state\r | |
89 | // Note: this must be in sync with the stuff in the asm file\r | |
90 | // Note also: HOBs (pei temp ram) MUST be above stack\r | |
91 | //\r | |
92 | SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r | |
93 | SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);\r | |
94 | SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r | |
95 | SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r | |
96 | SecCoreData.TemporaryRamSize = TemporaryRamSize;\r | |
97 | SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r | |
98 | SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r | |
99 | SecCoreData.StackBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize/2));\r | |
100 | SecCoreData.StackSize = SecCoreData.TemporaryRamSize / 2;\r | |
101 | \r | |
102 | // Jump to PEI core entry point\r | |
103 | (PeiCoreEntryPoint)(&SecCoreData, PpiList);\r | |
104 | }\r |