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1 | /** @file\r | |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | *\r | |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include <Library/ArmMPCoreMailBoxLib.h>\r | |
16 | #include <Chipset/ArmV7.h>\r | |
17 | #include <Drivers/PL390Gic.h>\r | |
18 | \r | |
19 | #include "PrePeiCore.h"\r | |
20 | \r | |
21 | extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;\r | |
22 | \r | |
23 | /*\r | |
24 | * This is the main function for secondary cores. They loop around until a non Null value is written to\r | |
25 | * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r | |
26 | * Note:The secondary cores, while executing secondary_main, assumes that:\r | |
27 | * : SGI 0 is configured as Non-secure interrupt\r | |
28 | * : Priority Mask is configured to allow SGI 0\r | |
29 | * : Interrupt Distributor and CPU interfaces are enabled\r | |
30 | *\r | |
31 | */\r | |
32 | VOID\r | |
33 | EFIAPI\r | |
34 | SecondaryMain (\r | |
35 | IN UINTN CoreId\r | |
36 | )\r | |
37 | {\r | |
38 | // Function pointer to Secondary Core entry point\r | |
39 | VOID (*secondary_start)(VOID);\r | |
40 | UINTN secondary_entry_addr=0;\r | |
41 | \r | |
42 | // Clear Secondary cores MailBox\r | |
43 | ArmClearMPCoreMailbox();\r | |
44 | \r | |
45 | while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r | |
46 | ArmCallWFI();\r | |
47 | // Acknowledge the interrupt and send End of Interrupt signal.\r | |
48 | PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r | |
49 | }\r | |
50 | \r | |
51 | secondary_start = (VOID (*)())secondary_entry_addr;\r | |
52 | \r | |
53 | // Jump to secondary core entry point.\r | |
54 | secondary_start();\r | |
55 | \r | |
56 | // The secondaries shouldn't reach here\r | |
57 | ASSERT(FALSE);\r | |
58 | }\r | |
59 | \r | |
60 | VOID\r | |
61 | EFIAPI\r | |
62 | PrimaryMain (\r | |
63 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r | |
64 | )\r | |
65 | {\r | |
66 | EFI_SEC_PEI_HAND_OFF SecCoreData;\r | |
67 | \r | |
68 | //Enable the GIC Distributor\r | |
69 | PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r | |
70 | \r | |
71 | // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r | |
72 | if (FeaturePcdGet(PcdSendSgiToBringUpSecondaryCores)) {\r | |
73 | // Sending SGI to all the Secondary CPU interfaces\r | |
74 | PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r | |
75 | }\r | |
76 | \r | |
77 | //\r | |
78 | // Bind this information into the SEC hand-off state\r | |
79 | // Note: this must be in sync with the stuff in the asm file\r | |
80 | // Note also: HOBs (pei temp ram) MUST be above stack\r | |
81 | //\r | |
82 | SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r | |
83 | SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r | |
84 | SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r | |
85 | SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r | |
86 | SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r | |
87 | SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r | |
88 | SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r | |
89 | SecCoreData.StackBase = SecCoreData.TemporaryRamBase;\r | |
90 | SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r | |
91 | \r | |
92 | // Jump to PEI core entry point\r | |
93 | (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r | |
94 | }\r |