ArmPlatformPkg: Increase more ARM address Pcd entries to 64-bit.

[mirror_edk2.git] / ArmPlatformPkg / Sec / Sec.c

/** @file\r
*  Main file supporting the SEC Phase on ARM Platforms\r
*\r
*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Library/ArmTrustedMonitorLib.h>\r
#include <Library/DebugAgentLib.h>\r
#include <Library/PrintLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/SerialPortLib.h>\r
#include <Library/ArmGicLib.h>\r
#include <Library/ArmPlatformLib.h>\r
\r
#include "SecInternal.h"\r
\r
#define SerialPrint(txt)  SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);\r
\r
VOID\r
CEntryPoint (\r
  IN  UINTN                     MpId,\r
  IN  UINTN                     SecBootMode\r
  )\r
{\r
  CHAR8           Buffer[100];\r
  UINTN           CharCount;\r
  UINTN           JumpAddress;\r
\r
  // Invalidate the data cache. Doesn't have to do the Data cache clean.\r
  ArmInvalidateDataCache ();\r
\r
  // Invalidate Instruction Cache\r
  ArmInvalidateInstructionCache ();\r
\r
  // Invalidate I & D TLBs\r
  ArmInvalidateTlb ();\r
\r
  // CPU specific settings\r
  ArmCpuSetup (MpId);\r
\r
  // Enable Floating Point Coprocessor if supported by the platform\r
  if (FixedPcdGet32 (PcdVFPEnabled)) {\r
    ArmEnableVFP ();\r
  }\r
\r
  // Initialize peripherals that must be done at the early stage\r
  // Example: Some L2 controller, interconnect, clock, DMC, etc\r
  ArmPlatformSecInitialize (MpId);\r
\r
  // Primary CPU clears out the SCU tag RAMs, secondaries wait\r
  if (ArmPlatformIsPrimaryCore (MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {\r
    if (ArmIsMpCore()) {\r
      // Signal for the initial memory is configured (event: BOOT_MEM_INIT)\r
      ArmCallSEV ();\r
    }\r
\r
    // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib\r
    // In non SEC modules the init call is in autogenerated code.\r
    SerialPortInitialize ();\r
\r
    // Start talking\r
    if (FixedPcdGetBool (PcdTrustzoneSupport)) {\r
      CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure firmware (version %s built at %a on %a)\n\r",\r
          (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
    } else {\r
      CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware (version %s built at %a on %a)\n\r",\r
          (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
    }\r
    SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
\r
    // Initialize the Debug Agent for Source Level Debugging\r
    InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);\r
    SaveAndSetDebugTimerInterrupt (TRUE);\r
\r
    // Enable the GIC distributor and CPU Interface\r
    // - no other Interrupts are enabled,  doesn't have to worry about the priority.\r
    // - all the cores are in secure state, use secure SGI's\r
    ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));\r
    ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));\r
  } else {\r
    // Enable the GIC CPU Interface\r
    ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));\r
  }\r
\r
  // Enable Full Access to CoProcessors\r
  ArmWriteCpacr (CPACR_CP_FULL_ACCESS);\r
\r
  // Test if Trustzone is supported on this platform\r
  if (FixedPcdGetBool (PcdTrustzoneSupport)) {\r
    if (ArmIsMpCore ()) {\r
      // Setup SMP in Non Secure world\r
      ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));\r
    }\r
\r
    // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))\r
    // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))\r
    ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||\r
            ((PcdGet32(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));\r
\r
    // Enter Monitor Mode\r
    enter_monitor_mode (\r
      (UINTN)TrustedWorldInitialization, MpId, SecBootMode,\r
      (VOID*) (PcdGet32 (PcdCPUCoresSecMonStackBase) +\r
          (PcdGet32 (PcdCPUCoreSecMonStackSize) * (ArmPlatformGetCorePosition (MpId) + 1)))\r
      );\r
  } else {\r
    if (ArmPlatformIsPrimaryCore (MpId)) {\r
      SerialPrint ("Trust Zone Configuration is disabled\n\r");\r
    }\r
\r
    // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().\r
    // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program\r
    // Status Register as the the current one (CPSR).\r
    copy_cpsr_into_spsr ();\r
\r
    // Call the Platform specific function to execute additional actions if required\r
    JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
    ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
\r
    NonTrustedWorldTransition (MpId, JumpAddress);\r
  }\r
  ASSERT (0); // We must never return from the above function\r
}\r
\r
VOID\r
TrustedWorldInitialization (\r
  IN  UINTN                     MpId,\r
  IN  UINTN                     SecBootMode\r
  )\r
{\r
  UINTN   JumpAddress;\r
\r
  //-------------------- Monitor Mode ---------------------\r
\r
  // Set up Monitor World (Vector Table, etc)\r
  ArmSecureMonitorWorldInitialize ();\r
\r
  // Transfer the interrupt to Non-secure World\r
  ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));\r
\r
  // Initialize platform specific security policy\r
  ArmPlatformSecTrustzoneInit (MpId);\r
\r
  // Setup the Trustzone Chipsets\r
  if (SecBootMode == ARM_SEC_COLD_BOOT) {\r
    if (ArmPlatformIsPrimaryCore (MpId)) {\r
      if (ArmIsMpCore()) {\r
        // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)\r
        ArmCallSEV ();\r
      }\r
    } else {\r
      // The secondary cores need to wait until the Trustzone chipsets configuration is done\r
      // before switching to Non Secure World\r
\r
      // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)\r
      ArmCallWFE ();\r
    }\r
  }\r
\r
  // Call the Platform specific function to execute additional actions if required\r
  JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
  ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
\r
  // Initialize architecture specific security policy\r
  ArmSecArchTrustzoneInit ();\r
\r
  // CP15 Secure Configuration Register\r
  ArmWriteScr (PcdGet32 (PcdArmScr));\r
\r
  NonTrustedWorldTransition (MpId, JumpAddress);\r
}\r
\r
VOID\r
NonTrustedWorldTransition (\r
  IN  UINTN                     MpId,\r
  IN  UINTN                     JumpAddress\r
  )\r
{\r
  // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition\r
  // By not set, the mode for Non Secure World is SVC\r
  if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {\r
    set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));\r
  }\r
\r
  return_from_exception (JumpAddress);\r
  //-------------------- Non Secure Mode ---------------------\r
\r
  // PEI Core should always load and never return\r
  ASSERT (FALSE);\r
}\r
\r