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1 | //\r | |
2 | // Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r | |
3 | // \r | |
4 | // This program and the accompanying materials \r | |
5 | // are licensed and made available under the terms and conditions of the BSD License \r | |
6 | // which accompanies this distribution. The full text of the license may be found at \r | |
7 | // http://opensource.org/licenses/bsd-license.php \r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AutoGen.h>\r | |
15 | #include <AsmMacroIoLib.h>\r | |
16 | #include "SecInternal.h"\r | |
17 | \r | |
18 | .text\r | |
19 | .align 3\r | |
20 | \r | |
21 | GCC_ASM_IMPORT(CEntryPoint)\r | |
22 | GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r | |
23 | GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r | |
24 | GCC_ASM_IMPORT(ArmDisableInterrupts)\r | |
25 | GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r | |
26 | GCC_ASM_IMPORT(ArmWriteVBar)\r | |
27 | GCC_ASM_IMPORT(ArmReadMpidr)\r | |
28 | GCC_ASM_IMPORT(SecVectorTable)\r | |
29 | GCC_ASM_IMPORT(ArmCallWFE)\r | |
30 | GCC_ASM_EXPORT(_ModuleEntryPoint)\r | |
31 | \r | |
32 | StartupAddr: .word ASM_PFX(CEntryPoint)\r | |
33 | \r | |
34 | ASM_PFX(_ModuleEntryPoint):\r | |
35 | // First ensure all interrupts are disabled\r | |
36 | bl ASM_PFX(ArmDisableInterrupts)\r | |
37 | \r | |
38 | // Ensure that the MMU and caches are off\r | |
39 | bl ASM_PFX(ArmDisableCachesAndMmu)\r | |
40 | \r | |
41 | // Jump to Platform Specific Boot Action function\r | |
42 | blx ASM_PFX(ArmPlatformSecBootAction)\r | |
43 | \r | |
44 | // Set VBAR to the start of the exception vectors in Secure Mode\r | |
45 | LoadConstantToReg (ASM_PFX(SecVectorTable), r0)\r | |
46 | bl ASM_PFX(ArmWriteVBar)\r | |
47 | \r | |
48 | _IdentifyCpu:\r | |
49 | // Identify CPU ID\r | |
50 | bl ASM_PFX(ArmReadMpidr)\r | |
51 | // Get ID of this CPU in Multicore system\r | |
52 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r | |
53 | and r5, r0, r1\r | |
54 | \r | |
55 | // Is it the Primary Core ?\r | |
56 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r | |
57 | cmp r5, r3\r | |
58 | // Only the primary core initialize the memory (SMC)\r | |
59 | beq _InitMem\r | |
60 | \r | |
61 | _WaitInitMem:\r | |
62 | // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r | |
63 | bl ASM_PFX(ArmCallWFE)\r | |
64 | // Now the Init Mem is initialized, we setup the secondary core stacks\r | |
65 | b _SetupSecondaryCoreStack\r | |
66 | \r | |
67 | _InitMem:\r | |
68 | // Initialize Init Boot Memory\r | |
69 | bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r | |
70 | \r | |
71 | // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r | |
72 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r | |
73 | \r | |
74 | _SetupPrimaryCoreStack:\r | |
75 | // Get the top of the primary stacks (and the base of the secondary stacks)\r | |
76 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
77 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r | |
78 | add r1, r1, r2\r | |
79 | \r | |
80 | LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r | |
81 | \r | |
82 | // The reserved space for global variable must be 8-bytes aligned for pushing\r | |
83 | // 64-bit variable on the stack\r | |
84 | SetPrimaryStack (r1, r2, r3)\r | |
85 | b _PrepareArguments\r | |
86 | \r | |
87 | _SetupSecondaryCoreStack:\r | |
88 | // Get the top of the primary stacks (and the base of the secondary stacks)\r | |
89 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
90 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r | |
91 | add r1, r1, r2\r | |
92 | \r | |
93 | // Get the Core Position (ClusterId * 4) + CoreId\r | |
94 | GetCorePositionInStack(r0, r5, r2)\r | |
95 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r | |
96 | add r0, r0, #1\r | |
97 | \r | |
98 | // StackOffset = CorePos * StackSize\r | |
99 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r | |
100 | mul r0, r0, r2\r | |
101 | // SP = StackBase + StackOffset\r | |
102 | add sp, r1, r0\r | |
103 | \r | |
104 | _PrepareArguments:\r | |
105 | // Move sec startup address into a data register\r | |
106 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
107 | ldr r3, StartupAddr\r | |
108 | \r | |
109 | // Jump to SEC C code\r | |
110 | // r0 = mp_id\r | |
111 | mov r0, r5\r | |
112 | blx r3\r | |
113 | \r | |
114 | _NeverReturn:\r | |
115 | b _NeverReturn\r |