| | 1 | /** @file\r |
| | 2 | \r |
| | 3 | Copyright (c) 2006, Intel Corporation\r |
| | 4 | All rights reserved. This program and the accompanying materials\r |
| | 5 | are licensed and made available under the terms and conditions of the BSD License\r |
| | 6 | which accompanies this distribution. The full text of the license may be found at\r |
| | 7 | http://opensource.org/licenses/bsd-license.php\r |
| | 8 | \r |
| | 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| | 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| | 11 | \r |
| | 12 | **/\r |
| | 13 | \r |
| | 14 | \r |
| | 15 | #ifndef _EFI_PCI_BUS_H_\r |
| | 16 | #define _EFI_PCI_BUS_H_\r |
| | 17 | \r |
| | 18 | \r |
| | 19 | #include <FrameworkDxe.h>\r |
| | 20 | \r |
| | 21 | \r |
| | 22 | #include <Protocol/LoadedImage.h>\r |
| | 23 | #include <Protocol/PciHostBridgeResourceAllocation.h>\r |
| | 24 | #include <Protocol/PciIo.h>\r |
| | 25 | #include <Protocol/LoadFile2.h>\r |
| | 26 | #include <Protocol/PciRootBridgeIo.h>\r |
| | 27 | #include <Protocol/PciHotPlugRequest.h>\r |
| | 28 | #include <Protocol/DevicePath.h>\r |
| | 29 | #include <Protocol/PciPlatform.h>\r |
| | 30 | #include <Protocol/PciHotPlugInit.h>\r |
| | 31 | #include <Protocol/Decompress.h>\r |
| | 32 | #include <Guid/PciOptionRomTable.h>\r |
| | 33 | #include <Protocol/BusSpecificDriverOverride.h>\r |
| | 34 | #include <Protocol/UgaIo.h>\r |
| | 35 | #include <Protocol/IncompatiblePciDeviceSupport.h>\r |
| | 36 | \r |
| | 37 | #include <Library/DebugLib.h>\r |
| | 38 | #include <Library/UefiDriverEntryPoint.h>\r |
| | 39 | #include <Library/BaseLib.h>\r |
| | 40 | #include <Library/UefiLib.h>\r |
| | 41 | #include <Library/BaseMemoryLib.h>\r |
| | 42 | #include <Library/ReportStatusCodeLib.h>\r |
| | 43 | #include <Library/MemoryAllocationLib.h>\r |
| | 44 | #include <Library/UefiBootServicesTableLib.h>\r |
| | 45 | #include <Library/DevicePathLib.h>\r |
| | 46 | #include <Library/PcdLib.h>\r |
| | 47 | #include <Library/PciIncompatibleDeviceSupportLib.h>\r |
| | 48 | #include <Library/PeCoffLib.h>\r |
| | 49 | \r |
| | 50 | #include <IndustryStandard/Pci.h>\r |
| | 51 | #include <IndustryStandard/PeImage.h>\r |
| | 52 | #include <IndustryStandard/Acpi.h>\r |
| | 53 | #include "ComponentName.h"\r |
| | 54 | \r |
| | 55 | \r |
| | 56 | //\r |
| | 57 | // Global Variables\r |
| | 58 | //\r |
| | 59 | extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r |
| | 60 | extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r |
| | 61 | extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r |
| | 62 | extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r |
| | 63 | \r |
| | 64 | //\r |
| | 65 | // Driver Produced Protocol Prototypes\r |
| | 66 | //\r |
| | 67 | \r |
| | 68 | #define VGABASE1 0x3B0\r |
| | 69 | #define VGALIMIT1 0x3BB\r |
| | 70 | \r |
| | 71 | #define VGABASE2 0x3C0\r |
| | 72 | #define VGALIMIT2 0x3DF\r |
| | 73 | \r |
| | 74 | #define ISABASE 0x100\r |
| | 75 | #define ISALIMIT 0x3FF\r |
| | 76 | \r |
| | 77 | typedef enum {\r |
| | 78 | PciBarTypeUnknown = 0,\r |
| | 79 | PciBarTypeIo16,\r |
| | 80 | PciBarTypeIo32,\r |
| | 81 | PciBarTypeMem32,\r |
| | 82 | PciBarTypePMem32,\r |
| | 83 | PciBarTypeMem64,\r |
| | 84 | PciBarTypePMem64,\r |
| | 85 | PciBarTypeIo,\r |
| | 86 | PciBarTypeMem,\r |
| | 87 | PciBarTypeMaxType\r |
| | 88 | } PCI_BAR_TYPE;\r |
| | 89 | \r |
| | 90 | typedef struct {\r |
| | 91 | UINT64 BaseAddress;\r |
| | 92 | UINT64 Length;\r |
| | 93 | UINT64 Alignment;\r |
| | 94 | PCI_BAR_TYPE BarType;\r |
| | 95 | BOOLEAN Prefetchable;\r |
| | 96 | UINT8 MemType;\r |
| | 97 | UINT8 Offset;\r |
| | 98 | } PCI_BAR;\r |
| | 99 | \r |
| | 100 | #define PPB_BAR_0 0\r |
| | 101 | #define PPB_BAR_1 1\r |
| | 102 | #define PPB_IO_RANGE 2\r |
| | 103 | #define PPB_MEM32_RANGE 3\r |
| | 104 | #define PPB_PMEM32_RANGE 4\r |
| | 105 | #define PPB_PMEM64_RANGE 5\r |
| | 106 | #define PPB_MEM64_RANGE 0xFF\r |
| | 107 | \r |
| | 108 | #define P2C_BAR_0 0\r |
| | 109 | #define P2C_MEM_1 1\r |
| | 110 | #define P2C_MEM_2 2\r |
| | 111 | #define P2C_IO_1 3\r |
| | 112 | #define P2C_IO_2 4\r |
| | 113 | \r |
| | 114 | #define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')\r |
| | 115 | \r |
| | 116 | #define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r |
| | 117 | #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r |
| | 118 | #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r |
| | 119 | #define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r |
| | 120 | #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r |
| | 121 | #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r |
| | 122 | #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r |
| | 123 | \r |
| | 124 | #define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r |
| | 125 | \r |
| | 126 | //\r |
| | 127 | // Define option for attribute\r |
| | 128 | //\r |
| | 129 | #define EFI_SET_SUPPORTS 0\r |
| | 130 | #define EFI_SET_ATTRIBUTES 1\r |
| | 131 | \r |
| | 132 | typedef struct _PCI_IO_DEVICE {\r |
| | 133 | UINT32 Signature;\r |
| | 134 | EFI_HANDLE Handle;\r |
| | 135 | EFI_PCI_IO_PROTOCOL PciIo;\r |
| | 136 | LIST_ENTRY Link;\r |
| | 137 | \r |
| | 138 | EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r |
| | 139 | EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r |
| | 140 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r |
| | 141 | EFI_LOAD_FILE2_PROTOCOL LoadFile2;\r |
| | 142 | \r |
| | 143 | //\r |
| | 144 | // PCI configuration space header type\r |
| | 145 | //\r |
| | 146 | PCI_TYPE00 Pci;\r |
| | 147 | \r |
| | 148 | //\r |
| | 149 | // Bus number, Device number, Function number\r |
| | 150 | //\r |
| | 151 | UINT8 BusNumber;\r |
| | 152 | UINT8 DeviceNumber;\r |
| | 153 | UINT8 FunctionNumber;\r |
| | 154 | \r |
| | 155 | //\r |
| | 156 | // BAR for this PCI Device\r |
| | 157 | //\r |
| | 158 | PCI_BAR PciBar[PCI_MAX_BAR];\r |
| | 159 | \r |
| | 160 | //\r |
| | 161 | // The bridge device this pci device is subject to\r |
| | 162 | //\r |
| | 163 | struct _PCI_IO_DEVICE *Parent;\r |
| | 164 | \r |
| | 165 | //\r |
| | 166 | // A linked list for children Pci Device if it is bridge device\r |
| | 167 | //\r |
| | 168 | LIST_ENTRY ChildList;\r |
| | 169 | \r |
| | 170 | //\r |
| | 171 | // TURE if the PCI bus driver creates the handle for this PCI device\r |
| | 172 | //\r |
| | 173 | BOOLEAN Registered;\r |
| | 174 | \r |
| | 175 | //\r |
| | 176 | // TRUE if the PCI bus driver successfully allocates the resource required by\r |
| | 177 | // this PCI device\r |
| | 178 | //\r |
| | 179 | BOOLEAN Allocated;\r |
| | 180 | \r |
| | 181 | //\r |
| | 182 | // The attribute this PCI device currently set\r |
| | 183 | //\r |
| | 184 | UINT64 Attributes;\r |
| | 185 | \r |
| | 186 | //\r |
| | 187 | // The attributes this PCI device actually supports\r |
| | 188 | //\r |
| | 189 | UINT64 Supports;\r |
| | 190 | \r |
| | 191 | //\r |
| | 192 | // The resource decode the bridge supports\r |
| | 193 | //\r |
| | 194 | UINT32 Decodes;\r |
| | 195 | \r |
| | 196 | //\r |
| | 197 | // The OptionRom Size\r |
| | 198 | //\r |
| | 199 | UINT64 RomSize;\r |
| | 200 | \r |
| | 201 | //\r |
| | 202 | // The OptionRom Size\r |
| | 203 | //\r |
| | 204 | UINT64 RomBase;\r |
| | 205 | \r |
| | 206 | //\r |
| | 207 | // TRUE if all OpROM (in device or in platform specific position) have been processed\r |
| | 208 | //\r |
| | 209 | BOOLEAN AllOpRomProcessed;\r |
| | 210 | \r |
| | 211 | //\r |
| | 212 | // TRUE if there is any EFI driver in the OptionRom\r |
| | 213 | //\r |
| | 214 | BOOLEAN BusOverride;\r |
| | 215 | \r |
| | 216 | //\r |
| | 217 | // A list tracking reserved resource on a bridge device\r |
| | 218 | //\r |
| | 219 | LIST_ENTRY ReservedResourceList;\r |
| | 220 | \r |
| | 221 | //\r |
| | 222 | // A list tracking image handle of platform specific overriding driver\r |
| | 223 | //\r |
| | 224 | LIST_ENTRY OptionRomDriverList;\r |
| | 225 | \r |
| | 226 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r |
| | 227 | EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r |
| | 228 | \r |
| | 229 | BOOLEAN IsPciExp;\r |
| | 230 | \r |
| | 231 | } PCI_IO_DEVICE;\r |
| | 232 | \r |
| | 233 | \r |
| | 234 | #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r |
| | 235 | CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r |
| | 236 | \r |
| | 237 | #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r |
| | 238 | CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r |
| | 239 | \r |
| | 240 | #define PCI_IO_DEVICE_FROM_LINK(a) \\r |
| | 241 | CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r |
| | 242 | \r |
| | 243 | #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r |
| | 244 | CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r |
| | 245 | \r |
| | 246 | //\r |
| | 247 | // Global Variables\r |
| | 248 | //\r |
| | 249 | extern LIST_ENTRY gPciDevicePool;\r |
| | 250 | extern BOOLEAN gFullEnumeration;\r |
| | 251 | extern UINTN gPciHostBridgeNumber;\r |
| | 252 | extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r |
| | 253 | extern UINT64 gAllOne;\r |
| | 254 | extern UINT64 gAllZero;\r |
| | 255 | \r |
| | 256 | extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r |
| | 257 | \r |
| | 258 | #include "PciIo.h"\r |
| | 259 | #include "PciCommand.h"\r |
| | 260 | #include "PciDeviceSupport.h"\r |
| | 261 | #include "PciEnumerator.h"\r |
| | 262 | #include "PciEnumeratorSupport.h"\r |
| | 263 | #include "PciDriverOverride.h"\r |
| | 264 | #include "PciRomTable.h"\r |
| | 265 | #include "PciOptionRomSupport.h"\r |
| | 266 | #include "PciPowerManagement.h"\r |
| | 267 | #include "PciHotPlugSupport.h"\r |
| | 268 | #include "PciLib.h"\r |
| | 269 | \r |
| | 270 | //\r |
| | 271 | // PCI Bus Support Function Prototypes\r |
| | 272 | //\r |
| | 273 | /**\r |
| | 274 | Test to see if this driver supports ControllerHandle. Any ControllerHandle\r |
| | 275 | than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r |
| | 276 | \r |
| | 277 | @param This Protocol instance pointer.\r |
| | 278 | @param ControllerHandle Handle of device to test.\r |
| | 279 | @param RemainingDevicePath Optional parameter use to pick a specific child.\r |
| | 280 | device to start.\r |
| | 281 | \r |
| | 282 | @retval EFI_SUCCESS This driver supports this device.\r |
| | 283 | @retval EFI_ALREADY_STARTED This driver is already running on this device.\r |
| | 284 | @retval other This driver does not support this device.\r |
| | 285 | \r |
| | 286 | **/\r |
| | 287 | EFI_STATUS\r |
| | 288 | EFIAPI\r |
| | 289 | PciBusDriverBindingSupported (\r |
| | 290 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r |
| | 291 | IN EFI_HANDLE Controller,\r |
| | 292 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r |
| | 293 | );\r |
| | 294 | \r |
| | 295 | /**\r |
| | 296 | Start this driver on ControllerHandle and enumerate Pci bus and start\r |
| | 297 | all device under PCI bus.\r |
| | 298 | \r |
| | 299 | @param This Protocol instance pointer.\r |
| | 300 | @param ControllerHandle Handle of device to bind driver to.\r |
| | 301 | @param RemainingDevicePath Optional parameter use to pick a specific child.\r |
| | 302 | device to start.\r |
| | 303 | \r |
| | 304 | @retval EFI_SUCCESS This driver is added to ControllerHandle.\r |
| | 305 | @retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.\r |
| | 306 | @retval other This driver does not support this device.\r |
| | 307 | \r |
| | 308 | **/\r |
| | 309 | EFI_STATUS\r |
| | 310 | EFIAPI\r |
| | 311 | PciBusDriverBindingStart (\r |
| | 312 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r |
| | 313 | IN EFI_HANDLE Controller,\r |
| | 314 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r |
| | 315 | );\r |
| | 316 | \r |
| | 317 | /**\r |
| | 318 | Stop this driver on ControllerHandle. Support stoping any child handles\r |
| | 319 | created by this driver.\r |
| | 320 | \r |
| | 321 | @param This Protocol instance pointer.\r |
| | 322 | @param ControllerHandle Handle of device to stop driver on.\r |
| | 323 | @param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of\r |
| | 324 | children is zero stop the entire bus driver.\r |
| | 325 | @param ChildHandleBuffer List of Child Handles to Stop.\r |
| | 326 | \r |
| | 327 | @retval EFI_SUCCESS This driver is removed ControllerHandle.\r |
| | 328 | @retval other This driver was not removed from this device.\r |
| | 329 | \r |
| | 330 | **/\r |
| | 331 | EFI_STATUS\r |
| | 332 | EFIAPI\r |
| | 333 | PciBusDriverBindingStop (\r |
| | 334 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r |
| | 335 | IN EFI_HANDLE Controller,\r |
| | 336 | IN UINTN NumberOfChildren,\r |
| | 337 | IN EFI_HANDLE *ChildHandleBuffer\r |
| | 338 | );\r |
| | 339 | \r |
| | 340 | #define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r |
| | 341 | \r |
| | 342 | #endif\r |
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