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1 | /** @file\r | |
2 | Private Header file for Usb Host Controller PEIM\r | |
3 | \r | |
4 | Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r | |
5 | \r | |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions\r | |
8 | of the BSD License which accompanies this distribution. The\r | |
9 | full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #ifndef _RECOVERY_EHC_H_\r | |
18 | #define _RECOVERY_EHC_H_\r | |
19 | \r | |
20 | #include <PiPei.h>\r | |
21 | \r | |
22 | #include <Ppi/UsbController.h>\r | |
23 | #include <Ppi/Usb2HostController.h>\r | |
24 | \r | |
25 | #include <Library/DebugLib.h>\r | |
26 | #include <Library/PeimEntryPoint.h>\r | |
27 | #include <Library/PeiServicesLib.h>\r | |
28 | #include <Library/BaseMemoryLib.h>\r | |
29 | #include <Library/TimerLib.h>\r | |
30 | #include <Library/IoLib.h>\r | |
31 | \r | |
32 | typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;\r | |
33 | \r | |
34 | #define EFI_LIST_ENTRY LIST_ENTRY\r | |
35 | \r | |
36 | #include "UsbHcMem.h"\r | |
37 | #include "EhciReg.h"\r | |
38 | #include "EhciUrb.h"\r | |
39 | #include "EhciSched.h"\r | |
40 | \r | |
41 | #define EFI_USB_SPEED_FULL 0x0000\r | |
42 | #define EFI_USB_SPEED_LOW 0x0001\r | |
43 | #define EFI_USB_SPEED_HIGH 0x0002\r | |
44 | \r | |
45 | #define PAGESIZE 4096\r | |
46 | \r | |
47 | #define EHC_1_MICROSECOND 1\r | |
48 | #define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)\r | |
49 | #define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)\r | |
50 | \r | |
51 | //\r | |
52 | // EHCI register operation timeout, set by experience\r | |
53 | //\r | |
54 | #define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)\r | |
55 | #define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)\r | |
56 | \r | |
57 | \r | |
58 | //\r | |
59 | // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r | |
60 | //\r | |
61 | #define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)\r | |
62 | \r | |
63 | //\r | |
64 | // Sync transfer polling interval, set by experience.\r | |
65 | //\r | |
66 | #define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)\r | |
67 | \r | |
68 | //\r | |
69 | //Iterate through the doule linked list. NOT delete safe\r | |
70 | //\r | |
71 | #define EFI_LIST_FOR_EACH(Entry, ListHead) \\r | |
72 | for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)\r | |
73 | \r | |
74 | //\r | |
75 | //Iterate through the doule linked list. This is delete-safe.\r | |
76 | //Don't touch NextEntry\r | |
77 | //\r | |
78 | #define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \\r | |
79 | for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\\r | |
80 | Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)\r | |
81 | \r | |
82 | #define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)\r | |
83 | \r | |
84 | \r | |
85 | #define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r | |
86 | #define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r | |
87 | #define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r | |
88 | \r | |
89 | #define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \\r | |
90 | (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))\r | |
91 | \r | |
92 | #define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')\r | |
93 | \r | |
94 | struct _PEI_USB2_HC_DEV {\r | |
95 | UINTN Signature;\r | |
96 | PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;\r | |
97 | EFI_PEI_PPI_DESCRIPTOR PpiDescriptor; \r | |
98 | UINT32 UsbHostControllerBaseAddress;\r | |
99 | PEI_URB *Urb;\r | |
100 | USBHC_MEM_POOL *MemPool;\r | |
101 | \r | |
102 | //\r | |
103 | // Schedule data shared between asynchronous and periodic\r | |
104 | // transfers:\r | |
105 | // ShortReadStop, as its name indicates, is used to terminate\r | |
106 | // the short read except the control transfer. EHCI follows\r | |
107 | // the alternative next QTD point when a short read happens.\r | |
108 | // For control transfer, even the short read happens, try the\r | |
109 | // status stage.\r | |
110 | //\r | |
111 | PEI_EHC_QTD *ShortReadStop;\r | |
112 | EFI_EVENT PollTimer;\r | |
113 | \r | |
114 | //\r | |
115 | // Asynchronous(bulk and control) transfer schedule data: \r | |
116 | // ReclaimHead is used as the head of the asynchronous transfer\r | |
117 | // list. It acts as the reclamation header. \r | |
118 | //\r | |
119 | PEI_EHC_QH *ReclaimHead;\r | |
120 | \r | |
121 | //\r | |
122 | // Peroidic (interrupt) transfer schedule data:\r | |
123 | //\r | |
124 | VOID *PeriodFrame; // Mapped as common buffer \r | |
125 | VOID *PeriodFrameHost;\r | |
126 | VOID *PeriodFrameMap;\r | |
127 | \r | |
128 | PEI_EHC_QH *PeriodOne;\r | |
129 | EFI_LIST_ENTRY AsyncIntTransfers;\r | |
130 | \r | |
131 | //\r | |
132 | // EHCI configuration data\r | |
133 | //\r | |
134 | UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET\r | |
135 | UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS\r | |
136 | UINT32 CapLen; // Capability length\r | |
137 | UINT32 High32bitAddr;\r | |
138 | };\r | |
139 | \r | |
140 | #define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)\r | |
141 | \r | |
142 | /**\r | |
143 | @param EhcDev EHCI Device.\r | |
144 | \r | |
145 | @retval EFI_SUCCESS EHCI successfully initialized.\r | |
146 | @retval EFI_ABORTED EHCI was failed to be initialized.\r | |
147 | \r | |
148 | **/\r | |
149 | EFI_STATUS\r | |
150 | InitializeUsbHC (\r | |
151 | IN PEI_USB2_HC_DEV *EhcDev \r | |
152 | );\r | |
153 | \r | |
154 | /**\r | |
155 | Initialize the memory management pool for the host controller.\r | |
156 | \r | |
157 | @param Ehc The EHCI device.\r | |
158 | @param Check4G Whether the host controller requires allocated memory \r | |
159 | from one 4G address space.\r | |
160 | @param Which4G The 4G memory area each memory allocated should be from.\r | |
161 | \r | |
162 | @retval EFI_SUCCESS The memory pool is initialized.\r | |
163 | @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool.\r | |
164 | \r | |
165 | **/\r | |
166 | USBHC_MEM_POOL *\r | |
167 | UsbHcInitMemPool (\r | |
168 | IN PEI_USB2_HC_DEV *Ehc,\r | |
169 | IN BOOLEAN Check4G,\r | |
170 | IN UINT32 Which4G\r | |
171 | )\r | |
172 | ;\r | |
173 | \r | |
174 | /**\r | |
175 | Release the memory management pool.\r | |
176 | \r | |
177 | @param Pool The USB memory pool to free.\r | |
178 | \r | |
179 | @retval EFI_DEVICE_ERROR Fail to free the memory pool.\r | |
180 | @retval EFI_SUCCESS The memory pool is freed.\r | |
181 | \r | |
182 | **/\r | |
183 | EFI_STATUS\r | |
184 | UsbHcFreeMemPool (\r | |
185 | IN USBHC_MEM_POOL *Pool\r | |
186 | )\r | |
187 | ;\r | |
188 | \r | |
189 | /**\r | |
190 | Allocate some memory from the host controller's memory pool\r | |
191 | which can be used to communicate with host controller.\r | |
192 | \r | |
193 | @param Ehc The EHCI device.\r | |
194 | @param Pool The host controller's memory pool.\r | |
195 | @param Size Size of the memory to allocate.\r | |
196 | \r | |
197 | @return The allocated memory or NULL.\r | |
198 | \r | |
199 | **/\r | |
200 | VOID *\r | |
201 | UsbHcAllocateMem (\r | |
202 | IN PEI_USB2_HC_DEV *Ehc,\r | |
203 | IN USBHC_MEM_POOL *Pool,\r | |
204 | IN UINTN Size\r | |
205 | )\r | |
206 | ;\r | |
207 | \r | |
208 | /**\r | |
209 | Free the allocated memory back to the memory pool.\r | |
210 | \r | |
211 | @param Pool The memory pool of the host controller.\r | |
212 | @param Mem The memory to free.\r | |
213 | @param Size The size of the memory to free.\r | |
214 | \r | |
215 | **/\r | |
216 | VOID\r | |
217 | UsbHcFreeMem (\r | |
218 | IN USBHC_MEM_POOL *Pool,\r | |
219 | IN VOID *Mem,\r | |
220 | IN UINTN Size\r | |
221 | )\r | |
222 | ;\r | |
223 | \r | |
224 | #endif\r |