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1/** @file\r
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
3 NVM Express specification.\r
4\r
5 (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>\r
6 Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php.\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#include "NvmExpress.h"\r
18\r
19/**\r
20 Dump the execution status from a given completion queue entry.\r
21\r
22 @param[in] Cq A pointer to the NVME_CQ item.\r
23\r
24**/\r
25VOID\r
26NvmeDumpStatus (\r
27 IN NVME_CQ *Cq\r
28 )\r
29{\r
30 DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));\r
31\r
32 DEBUG ((EFI_D_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));\r
33\r
34 DEBUG ((EFI_D_VERBOSE, " NVMe Cmd Execution Result - "));\r
35\r
36 switch (Cq->Sct) {\r
37 case 0x0:\r
38 switch (Cq->Sc) {\r
39 case 0x0:\r
40 DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));\r
41 break;\r
42 case 0x1:\r
43 DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));\r
44 break;\r
45 case 0x2:\r
46 DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));\r
47 break;\r
48 case 0x3:\r
49 DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));\r
50 break;\r
51 case 0x4:\r
52 DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));\r
53 break;\r
54 case 0x5:\r
55 DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));\r
56 break;\r
57 case 0x6:\r
58 DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));\r
59 break;\r
60 case 0x7:\r
61 DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));\r
62 break;\r
63 case 0x8:\r
64 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));\r
65 break;\r
66 case 0x9:\r
67 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));\r
68 break;\r
69 case 0xA:\r
70 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));\r
71 break;\r
72 case 0xB:\r
73 DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));\r
74 break;\r
75 case 0xC:\r
76 DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));\r
77 break;\r
78 case 0xD:\r
79 DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));\r
80 break;\r
81 case 0xE:\r
82 DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));\r
83 break;\r
84 case 0xF:\r
85 DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));\r
86 break;\r
87 case 0x10:\r
88 DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));\r
89 break;\r
90 case 0x11:\r
91 DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));\r
92 break;\r
93 case 0x80:\r
94 DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));\r
95 break;\r
96 case 0x81:\r
97 DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));\r
98 break;\r
99 case 0x82:\r
100 DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));\r
101 break;\r
102 case 0x83:\r
103 DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));\r
104 break;\r
105 }\r
106 break;\r
107\r
108 case 0x1:\r
109 switch (Cq->Sc) {\r
110 case 0x0:\r
111 DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));\r
112 break;\r
113 case 0x1:\r
114 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));\r
115 break;\r
116 case 0x2:\r
117 DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));\r
118 break;\r
119 case 0x3:\r
120 DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));\r
121 break;\r
122 case 0x5:\r
123 DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));\r
124 break;\r
125 case 0x6:\r
126 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));\r
127 break;\r
128 case 0x7:\r
129 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));\r
130 break;\r
131 case 0x8:\r
132 DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));\r
133 break;\r
134 case 0x9:\r
135 DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));\r
136 break;\r
137 case 0xA:\r
138 DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));\r
139 break;\r
140 case 0xB:\r
141 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));\r
142 break;\r
143 case 0xC:\r
144 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));\r
145 break;\r
146 case 0xD:\r
147 DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));\r
148 break;\r
149 case 0xE:\r
150 DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));\r
151 break;\r
152 case 0xF:\r
153 DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));\r
154 break;\r
155 case 0x10:\r
156 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));\r
157 break;\r
158 case 0x80:\r
159 DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));\r
160 break;\r
161 case 0x81:\r
162 DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));\r
163 break;\r
164 case 0x82:\r
165 DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));\r
166 break;\r
167 }\r
168 break;\r
169\r
170 case 0x2:\r
171 switch (Cq->Sc) {\r
172 case 0x80:\r
173 DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));\r
174 break;\r
175 case 0x81:\r
176 DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));\r
177 break;\r
178 case 0x82:\r
179 DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));\r
180 break;\r
181 case 0x83:\r
182 DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));\r
183 break;\r
184 case 0x84:\r
185 DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));\r
186 break;\r
187 case 0x85:\r
188 DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));\r
189 break;\r
190 case 0x86:\r
191 DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));\r
192 break;\r
193 }\r
194 break;\r
195\r
196 default:\r
197 break;\r
198 }\r
199}\r
200\r
201/**\r
202 Create PRP lists for data transfer which is larger than 2 memory pages.\r
203 Note here we calcuate the number of required PRP lists and allocate them at one time.\r
204\r
205 @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
206 @param[in] PhysicalAddr The physical base address of data buffer.\r
207 @param[in] Pages The number of pages to be transfered.\r
208 @param[out] PrpListHost The host base address of PRP lists.\r
209 @param[in,out] PrpListNo The number of PRP List.\r
210 @param[out] Mapping The mapping value returned from PciIo.Map().\r
211\r
212 @retval The pointer to the first PRP List of the PRP lists.\r
213\r
214**/\r
215VOID*\r
216NvmeCreatePrpList (\r
217 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
218 IN EFI_PHYSICAL_ADDRESS PhysicalAddr,\r
219 IN UINTN Pages,\r
220 OUT VOID **PrpListHost,\r
221 IN OUT UINTN *PrpListNo,\r
222 OUT VOID **Mapping\r
223 )\r
224{\r
225 UINTN PrpEntryNo;\r
226 UINT64 PrpListBase;\r
227 UINTN PrpListIndex;\r
228 UINTN PrpEntryIndex;\r
229 UINT64 Remainder;\r
230 EFI_PHYSICAL_ADDRESS PrpListPhyAddr;\r
231 UINTN Bytes;\r
232 EFI_STATUS Status;\r
233\r
234 //\r
235 // The number of Prp Entry in a memory page.\r
236 //\r
237 PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);\r
238\r
239 //\r
240 // Calculate total PrpList number.\r
241 //\r
242 *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo - 1, &Remainder);\r
243 if (*PrpListNo == 0) {\r
244 *PrpListNo = 1;\r
245 } else if ((Remainder != 0) && (Remainder != 1)) {\r
246 *PrpListNo += 1;\r
247 } else if (Remainder == 1) {\r
248 Remainder = PrpEntryNo;\r
249 } else if (Remainder == 0) {\r
250 Remainder = PrpEntryNo - 1;\r
251 }\r
252\r
253 Status = PciIo->AllocateBuffer (\r
254 PciIo,\r
255 AllocateAnyPages,\r
256 EfiBootServicesData,\r
257 *PrpListNo,\r
258 PrpListHost,\r
259 0\r
260 );\r
261\r
262 if (EFI_ERROR (Status)) {\r
263 return NULL;\r
264 }\r
265\r
266 Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);\r
267 Status = PciIo->Map (\r
268 PciIo,\r
269 EfiPciIoOperationBusMasterCommonBuffer,\r
270 *PrpListHost,\r
271 &Bytes,\r
272 &PrpListPhyAddr,\r
273 Mapping\r
274 );\r
275\r
276 if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {\r
277 DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));\r
278 goto EXIT;\r
279 }\r
280 //\r
281 // Fill all PRP lists except of last one.\r
282 //\r
283 ZeroMem (*PrpListHost, Bytes);\r
284 for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {\r
285 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
286\r
287 for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {\r
288 if (PrpEntryIndex != PrpEntryNo - 1) {\r
289 //\r
290 // Fill all PRP entries except of last one.\r
291 //\r
292 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r
293 PhysicalAddr += EFI_PAGE_SIZE;\r
294 } else {\r
295 //\r
296 // Fill last PRP entries with next PRP List pointer.\r
297 //\r
298 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;\r
299 }\r
300 }\r
301 }\r
302 //\r
303 // Fill last PRP list.\r
304 //\r
305 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
306 for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {\r
307 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r
308 PhysicalAddr += EFI_PAGE_SIZE;\r
309 }\r
310\r
311 return (VOID*)(UINTN)PrpListPhyAddr;\r
312\r
313EXIT:\r
314 PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);\r
315 return NULL;\r
316}\r
317\r
318\r
319/**\r
320 Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r
321 both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking\r
322 I/O functionality is optional.\r
323\r
324\r
325 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
326 @param[in] NamespaceId A 32 bit namespace ID as defined in the NVMe specification to which the NVM Express Command\r
327 Packet will be sent. A value of 0 denotes the NVM Express controller, a value of all 0xFF's\r
328 (all bytes are 0xFF) in the namespace ID specifies that the command packet should be sent to\r
329 all valid namespaces.\r
330 @param[in,out] Packet A pointer to the NVM Express Command Packet.\r
331 @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed.\r
332 If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O\r
333 is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM\r
334 Express Command Packet completes.\r
335\r
336 @retval EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r
337 to, or from DataBuffer.\r
338 @retval EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of bytes that could be transferred\r
339 is returned in TransferLength.\r
340 @retval EFI_NOT_READY The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r
341 may retry again later.\r
342 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Command Packet.\r
343 @retval EFI_INVALID_PARAMETER NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r
344 Express Command Packet was not sent, so no additional status information is available.\r
345 @retval EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not supported by the NVM Express\r
346 controller. The NVM Express Command Packet was not sent so no additional status information\r
347 is available.\r
348 @retval EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet to execute.\r
349\r
350**/\r
351EFI_STATUS\r
352EFIAPI\r
353NvmExpressPassThru (\r
354 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
355 IN UINT32 NamespaceId,\r
356 IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,\r
357 IN EFI_EVENT Event OPTIONAL\r
358 )\r
359{\r
360 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
361 EFI_STATUS Status;\r
362 EFI_PCI_IO_PROTOCOL *PciIo;\r
363 NVME_SQ *Sq;\r
364 NVME_CQ *Cq;\r
365 UINT8 QueueType;\r
366 UINT32 Bytes;\r
367 UINT16 Offset;\r
368 EFI_EVENT TimerEvent;\r
369 EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
370 EFI_PHYSICAL_ADDRESS PhyAddr;\r
371 VOID *MapData;\r
372 VOID *MapMeta;\r
373 VOID *MapPrpList;\r
374 UINTN MapLength;\r
375 UINT64 *Prp;\r
376 VOID *PrpListHost;\r
377 UINTN PrpListNo;\r
378 UINT32 Data;\r
379\r
380 //\r
381 // check the data fields in Packet parameter.\r
382 //\r
383 if ((This == NULL) || (Packet == NULL)) {\r
384 return EFI_INVALID_PARAMETER;\r
385 }\r
386\r
387 if ((Packet->NvmeCmd == NULL) || (Packet->NvmeCompletion == NULL)) {\r
388 return EFI_INVALID_PARAMETER;\r
389 }\r
390\r
391 if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {\r
392 return EFI_INVALID_PARAMETER;\r
393 }\r
394\r
395 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
396 PciIo = Private->PciIo;\r
397 MapData = NULL;\r
398 MapMeta = NULL;\r
399 MapPrpList = NULL;\r
400 PrpListHost = NULL;\r
401 PrpListNo = 0;\r
402 Prp = NULL;\r
403 TimerEvent = NULL;\r
404 Status = EFI_SUCCESS;\r
405\r
406 QueueType = Packet->QueueType;\r
407 Sq = Private->SqBuffer[QueueType] + Private->SqTdbl[QueueType].Sqt;\r
408 Cq = Private->CqBuffer[QueueType] + Private->CqHdbl[QueueType].Cqh;\r
409\r
410 if (Packet->NvmeCmd->Nsid != NamespaceId) {\r
411 return EFI_INVALID_PARAMETER;\r
412 }\r
413\r
414 ZeroMem (Sq, sizeof (NVME_SQ));\r
415 Sq->Opc = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;\r
416 Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;\r
417 Sq->Cid = Private->Cid[QueueType]++;\r
418 Sq->Nsid = Packet->NvmeCmd->Nsid;\r
419\r
420 //\r
421 // Currently we only support PRP for data transfer, SGL is NOT supported.\r
422 //\r
423 ASSERT (Sq->Psdt == 0);\r
424 if (Sq->Psdt != 0) {\r
425 DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));\r
426 return EFI_UNSUPPORTED;\r
427 }\r
428\r
429 Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;\r
430 //\r
431 // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.\r
432 // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because\r
433 // these two cmds are special which requires their data buffer must support simultaneous access by both the\r
434 // processor and a PCI Bus Master. It's caller's responsbility to ensure this.\r
435 //\r
436 if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_OPC) && (Sq->Opc != NVME_ADMIN_CRIOSQ_OPC)) {\r
437 if ((Sq->Opc & BIT0) != 0) {\r
438 Flag = EfiPciIoOperationBusMasterRead;\r
439 } else {\r
440 Flag = EfiPciIoOperationBusMasterWrite;\r
441 }\r
442\r
443 MapLength = Packet->TransferLength;\r
444 Status = PciIo->Map (\r
445 PciIo,\r
446 Flag,\r
447 Packet->TransferBuffer,\r
448 &MapLength,\r
449 &PhyAddr,\r
450 &MapData\r
451 );\r
452 if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {\r
453 return EFI_OUT_OF_RESOURCES;\r
454 }\r
455\r
456 Sq->Prp[0] = PhyAddr;\r
457 Sq->Prp[1] = 0;\r
458\r
459 MapLength = Packet->MetadataLength;\r
460 if(Packet->MetadataBuffer != NULL) {\r
461 MapLength = Packet->MetadataLength;\r
462 Status = PciIo->Map (\r
463 PciIo,\r
464 Flag,\r
465 Packet->MetadataBuffer,\r
466 &MapLength,\r
467 &PhyAddr,\r
468 &MapMeta\r
469 );\r
470 if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {\r
471 PciIo->Unmap (\r
472 PciIo,\r
473 MapData\r
474 );\r
475\r
476 return EFI_OUT_OF_RESOURCES;\r
477 }\r
478 Sq->Mptr = PhyAddr;\r
479 }\r
480 }\r
481 //\r
482 // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),\r
483 // then build a PRP list in the second PRP submission queue entry.\r
484 //\r
485 Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);\r
486 Bytes = Packet->TransferLength;\r
487\r
488 if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {\r
489 //\r
490 // Create PrpList for remaining data buffer.\r
491 //\r
492 PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
493 Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);\r
494 if (Prp == NULL) {\r
495 goto EXIT;\r
496 }\r
497\r
498 Sq->Prp[1] = (UINT64)(UINTN)Prp;\r
499 } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {\r
500 Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
501 }\r
502\r
503 if(Packet->NvmeCmd->Flags & CDW2_VALID) {\r
504 Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;\r
505 }\r
506 if(Packet->NvmeCmd->Flags & CDW3_VALID) {\r
507 Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);\r
508 }\r
509 if(Packet->NvmeCmd->Flags & CDW10_VALID) {\r
510 Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;\r
511 }\r
512 if(Packet->NvmeCmd->Flags & CDW11_VALID) {\r
513 Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;\r
514 }\r
515 if(Packet->NvmeCmd->Flags & CDW12_VALID) {\r
516 Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;\r
517 }\r
518 if(Packet->NvmeCmd->Flags & CDW13_VALID) {\r
519 Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;\r
520 }\r
521 if(Packet->NvmeCmd->Flags & CDW14_VALID) {\r
522 Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;\r
523 }\r
524 if(Packet->NvmeCmd->Flags & CDW15_VALID) {\r
525 Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;\r
526 }\r
527\r
528 //\r
529 // Ring the submission queue doorbell.\r
530 //\r
531 Private->SqTdbl[QueueType].Sqt ^= 1;\r
532 Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueType]);\r
533 PciIo->Mem.Write (\r
534 PciIo,\r
535 EfiPciIoWidthUint32,\r
536 NVME_BAR,\r
537 NVME_SQTDBL_OFFSET(QueueType, Private->Cap.Dstrd),\r
538 1,\r
539 &Data\r
540 );\r
541\r
542 Status = gBS->CreateEvent (\r
543 EVT_TIMER,\r
544 TPL_CALLBACK,\r
545 NULL,\r
546 NULL,\r
547 &TimerEvent\r
548 );\r
549 if (EFI_ERROR (Status)) {\r
550 goto EXIT;\r
551 }\r
552\r
553 Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);\r
554\r
555 if (EFI_ERROR(Status)) {\r
556 goto EXIT;\r
557 }\r
558\r
559 //\r
560 // Wait for completion queue to get filled in.\r
561 //\r
562 Status = EFI_TIMEOUT;\r
563 while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {\r
564 if (Cq->Pt != Private->Pt[QueueType]) {\r
565 Status = EFI_SUCCESS;\r
566 break;\r
567 }\r
568 }\r
569\r
570 if ((Private->CqHdbl[QueueType].Cqh ^= 1) == 0) {\r
571 Private->Pt[QueueType] ^= 1;\r
572 }\r
573\r
574 //\r
575 // Copy the Respose Queue entry for this command to the callers response buffer\r
576 //\r
577 CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));\r
578\r
579 //\r
580 // Dump every completion entry status for debugging.\r
581 //\r
582 DEBUG_CODE_BEGIN();\r
583 NvmeDumpStatus(Cq);\r
584 DEBUG_CODE_END();\r
585\r
586 Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueType]);\r
587 PciIo->Mem.Write (\r
588 PciIo,\r
589 EfiPciIoWidthUint32,\r
590 NVME_BAR,\r
591 NVME_CQHDBL_OFFSET(QueueType, Private->Cap.Dstrd),\r
592 1,\r
593 &Data\r
594 );\r
595\r
596EXIT:\r
597 if (MapData != NULL) {\r
598 PciIo->Unmap (\r
599 PciIo,\r
600 MapData\r
601 );\r
602 }\r
603\r
604 if (MapMeta != NULL) {\r
605 PciIo->Unmap (\r
606 PciIo,\r
607 MapMeta\r
608 );\r
609 }\r
610\r
611 if (MapPrpList != NULL) {\r
612 PciIo->Unmap (\r
613 PciIo,\r
614 MapPrpList\r
615 );\r
616 }\r
617\r
618 if (Prp != NULL) {\r
619 PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);\r
620 }\r
621\r
622 if (TimerEvent != NULL) {\r
623 gBS->CloseEvent (TimerEvent);\r
624 }\r
625 return Status;\r
626}\r
627\r
628/**\r
629 Used to retrieve the next namespace ID for this NVM Express controller.\r
630\r
631 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid\r
632 namespace ID on this NVM Express controller.\r
633\r
634 If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace\r
635 ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId\r
636 and a status of EFI_SUCCESS is returned.\r
637\r
638 If on input the value pointed to by NamespaceId is an invalid namespace ID other than 0xFFFFFFFF,\r
639 then EFI_INVALID_PARAMETER is returned.\r
640\r
641 If on input the value pointed to by NamespaceId is a valid namespace ID, then the next valid\r
642 namespace ID on the NVM Express controller is returned in the location pointed to by NamespaceId,\r
643 and EFI_SUCCESS is returned.\r
644\r
645 If the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM\r
646 Express controller, then EFI_NOT_FOUND is returned.\r
647\r
648 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
649 @param[in,out] NamespaceId On input, a pointer to a legal NamespaceId for an NVM Express\r
650 namespace present on the NVM Express controller. On output, a\r
651 pointer to the next NamespaceId of an NVM Express namespace on\r
652 an NVM Express controller. An input value of 0xFFFFFFFF retrieves\r
653 the first NamespaceId for an NVM Express namespace present on an\r
654 NVM Express controller.\r
655\r
656 @retval EFI_SUCCESS The Namespace ID of the next Namespace was returned.\r
657 @retval EFI_NOT_FOUND There are no more namespaces defined on this controller.\r
658 @retval EFI_INVALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF.\r
659\r
660**/\r
661EFI_STATUS\r
662EFIAPI\r
663NvmExpressGetNextNamespace (\r
664 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
665 IN OUT UINT32 *NamespaceId\r
666 )\r
667{\r
668 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
669 NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r
670 UINT32 NextNamespaceId;\r
671 EFI_STATUS Status;\r
672\r
673 if ((This == NULL) || (NamespaceId == NULL)) {\r
674 return EFI_INVALID_PARAMETER;\r
675 }\r
676\r
677 NamespaceData = NULL;\r
678 Status = EFI_NOT_FOUND;\r
679\r
680 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
681 //\r
682 // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID\r
683 //\r
684 if (*NamespaceId == 0xFFFFFFFF) {\r
685 //\r
686 // Start with the first namespace ID\r
687 //\r
688 NextNamespaceId = 1;\r
689 //\r
690 // Allocate buffer for Identify Namespace data.\r
691 //\r
692 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
693\r
694 if (NamespaceData == NULL) {\r
695 return EFI_NOT_FOUND;\r
696 }\r
697\r
698 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r
699 if (EFI_ERROR(Status)) {\r
700 goto Done;\r
701 }\r
702\r
703 *NamespaceId = NextNamespaceId;\r
704 } else {\r
705 if (*NamespaceId >= Private->ControllerData->Nn) {\r
706 return EFI_INVALID_PARAMETER;\r
707 }\r
708\r
709 NextNamespaceId = *NamespaceId + 1;\r
710 //\r
711 // Allocate buffer for Identify Namespace data.\r
712 //\r
713 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
714 if (NamespaceData == NULL) {\r
715 return EFI_NOT_FOUND;\r
716 }\r
717\r
718 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r
719 if (EFI_ERROR(Status)) {\r
720 goto Done;\r
721 }\r
722\r
723 *NamespaceId = NextNamespaceId;\r
724 }\r
725\r
726Done:\r
727 if (NamespaceData != NULL) {\r
728 FreePool(NamespaceData);\r
729 }\r
730\r
731 return Status;\r
732}\r
733\r
734/**\r
735 Used to translate a device path node to a namespace ID.\r
736\r
737 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID associated with the\r
738 namespace described by DevicePath.\r
739\r
740 If DevicePath is a device path node type that the NVM Express Pass Thru driver supports, then the NVM Express\r
741 Pass Thru driver will attempt to translate the contents DevicePath into a namespace ID.\r
742\r
743 If this translation is successful, then that namespace ID is returned in NamespaceId, and EFI_SUCCESS is returned\r
744\r
745 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
746 @param[in] DevicePath A pointer to the device path node that describes an NVM Express namespace on\r
747 the NVM Express controller.\r
748 @param[out] NamespaceId The NVM Express namespace ID contained in the device path node.\r
749\r
750 @retval EFI_SUCCESS DevicePath was successfully translated to NamespaceId.\r
751 @retval EFI_INVALID_PARAMETER If DevicePath or NamespaceId are NULL, then EFI_INVALID_PARAMETER is returned.\r
752 @retval EFI_UNSUPPORTED If DevicePath is not a device path node type that the NVM Express Pass Thru driver\r
753 supports, then EFI_UNSUPPORTED is returned.\r
754 @retval EFI_NOT_FOUND If DevicePath is a device path node type that the NVM Express Pass Thru driver\r
755 supports, but there is not a valid translation from DevicePath to a namespace ID,\r
756 then EFI_NOT_FOUND is returned.\r
757**/\r
758EFI_STATUS\r
759EFIAPI\r
760NvmExpressGetNamespace (\r
761 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
762 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
763 OUT UINT32 *NamespaceId\r
764 )\r
765{\r
766 NVME_NAMESPACE_DEVICE_PATH *Node;\r
767\r
768 if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {\r
769 return EFI_INVALID_PARAMETER;\r
770 }\r
771\r
772 if (DevicePath->Type != MESSAGING_DEVICE_PATH) {\r
773 return EFI_UNSUPPORTED;\r
774 }\r
775\r
776 Node = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;\r
777\r
778 if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {\r
779 if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {\r
780 return EFI_NOT_FOUND;\r
781 }\r
782\r
783 *NamespaceId = Node->NamespaceId;\r
784\r
785 return EFI_SUCCESS;\r
786 } else {\r
787 return EFI_UNSUPPORTED;\r
788 }\r
789}\r
790\r
791/**\r
792 Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.\r
793\r
794 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device\r
795 path node for the NVM Express namespace specified by NamespaceId.\r
796\r
797 If the NamespaceId is not valid, then EFI_NOT_FOUND is returned.\r
798\r
799 If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.\r
800\r
801 If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.\r
802\r
803 Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are\r
804 initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.\r
805\r
806 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
807 @param[in] NamespaceId The NVM Express namespace ID for which a device path node is to be\r
808 allocated and built. Caller must set the NamespaceId to zero if the\r
809 device path node will contain a valid UUID.\r
810 @param[in,out] DevicePath A pointer to a single device path node that describes the NVM Express\r
811 namespace specified by NamespaceId. This function is responsible for\r
812 allocating the buffer DevicePath with the boot service AllocatePool().\r
813 It is the caller's responsibility to free DevicePath when the caller\r
814 is finished with DevicePath.\r
815 @retval EFI_SUCCESS The device path node that describes the NVM Express namespace specified\r
816 by NamespaceId was allocated and returned in DevicePath.\r
817 @retval EFI_NOT_FOUND The NamespaceId is not valid.\r
818 @retval EFI_INVALID_PARAMETER DevicePath is NULL.\r
819 @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node.\r
820\r
821**/\r
822EFI_STATUS\r
823EFIAPI\r
824NvmExpressBuildDevicePath (\r
825 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
826 IN UINT32 NamespaceId,\r
827 IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
828 )\r
829{\r
830 NVME_NAMESPACE_DEVICE_PATH *Node;\r
831 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
832 EFI_STATUS Status;\r
833 NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r
834\r
835 //\r
836 // Validate parameters\r
837 //\r
838 if ((This == NULL) || (DevicePath == NULL)) {\r
839 return EFI_INVALID_PARAMETER;\r
840 }\r
841\r
842 if (NamespaceId == 0) {\r
843 return EFI_NOT_FOUND;\r
844 }\r
845\r
846 Status = EFI_SUCCESS;\r
847 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
848\r
849 Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));\r
850 if (Node == NULL) {\r
851 return EFI_OUT_OF_RESOURCES;\r
852 }\r
853\r
854 Node->Header.Type = MESSAGING_DEVICE_PATH;\r
855 Node->Header.SubType = MSG_NVME_NAMESPACE_DP;\r
856 SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));\r
857 Node->NamespaceId = NamespaceId;\r
858\r
859 //\r
860 // Allocate a buffer for Identify Namespace data.\r
861 //\r
862 NamespaceData = NULL;\r
863 NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
864 if(NamespaceData == NULL) {\r
865 Status = EFI_OUT_OF_RESOURCES;\r
866 goto Exit;\r
867 }\r
868\r
869 //\r
870 // Get UUID from specified Identify Namespace data.\r
871 //\r
872 Status = NvmeIdentifyNamespace (\r
873 Private,\r
874 NamespaceId,\r
875 (VOID *)NamespaceData\r
876 );\r
877\r
878 if (EFI_ERROR(Status)) {\r
879 goto Exit;\r
880 }\r
881\r
882 Node->NamespaceUuid = NamespaceData->Eui64;\r
883\r
884 *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;\r
885\r
886Exit:\r
887 if(NamespaceData != NULL) {\r
888 FreePool (NamespaceData);\r
889 }\r
890\r
891 if (EFI_ERROR (Status)) {\r
892 FreePool (Node);\r
893 }\r
894\r
895 return Status;\r
896}\r
897\r
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