]>
Commit | Line | Data |
---|---|---|
1 | /** @file\r | |
2 | The NvmExpressPei driver is used to manage non-volatile memory subsystem\r | |
3 | which follows NVM Express specification at PEI phase.\r | |
4 | \r | |
5 | Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>\r | |
6 | \r | |
7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
8 | \r | |
9 | **/\r | |
10 | \r | |
11 | #ifndef _NVM_EXPRESS_PEI_HCI_H_\r | |
12 | #define _NVM_EXPRESS_PEI_HCI_H_\r | |
13 | \r | |
14 | //\r | |
15 | // NVME host controller registers operation definitions\r | |
16 | //\r | |
17 | #define NVME_GET_CAP(Private, Cap) NvmeMmioRead (Cap, Private->MmioBase + NVME_CAP_OFFSET, sizeof (NVME_CAP))\r | |
18 | #define NVME_GET_CC(Private, Cc) NvmeMmioRead (Cc, Private->MmioBase + NVME_CC_OFFSET, sizeof (NVME_CC))\r | |
19 | #define NVME_SET_CC(Private, Cc) NvmeMmioWrite (Private->MmioBase + NVME_CC_OFFSET, Cc, sizeof (NVME_CC))\r | |
20 | #define NVME_GET_CSTS(Private, Csts) NvmeMmioRead (Csts, Private->MmioBase + NVME_CSTS_OFFSET, sizeof (NVME_CSTS))\r | |
21 | #define NVME_GET_AQA(Private, Aqa) NvmeMmioRead (Aqa, Private->MmioBase + NVME_AQA_OFFSET, sizeof (NVME_AQA))\r | |
22 | #define NVME_SET_AQA(Private, Aqa) NvmeMmioWrite (Private->MmioBase + NVME_AQA_OFFSET, Aqa, sizeof (NVME_AQA))\r | |
23 | #define NVME_GET_ASQ(Private, Asq) NvmeMmioRead (Asq, Private->MmioBase + NVME_ASQ_OFFSET, sizeof (NVME_ASQ))\r | |
24 | #define NVME_SET_ASQ(Private, Asq) NvmeMmioWrite (Private->MmioBase + NVME_ASQ_OFFSET, Asq, sizeof (NVME_ASQ))\r | |
25 | #define NVME_GET_ACQ(Private, Acq) NvmeMmioRead (Acq, Private->MmioBase + NVME_ACQ_OFFSET, sizeof (NVME_ACQ))\r | |
26 | #define NVME_SET_ACQ(Private, Acq) NvmeMmioWrite (Private->MmioBase + NVME_ACQ_OFFSET, Acq, sizeof (NVME_ACQ))\r | |
27 | #define NVME_GET_VER(Private, Ver) NvmeMmioRead (Ver, Private->MmioBase + NVME_VER_OFFSET, sizeof (NVME_VER))\r | |
28 | #define NVME_SET_SQTDBL(Private, Qid, Sqtdbl) NvmeMmioWrite (Private->MmioBase + NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd), Sqtdbl, sizeof (NVME_SQTDBL))\r | |
29 | #define NVME_SET_CQHDBL(Private, Qid, Cqhdbl) NvmeMmioWrite (Private->MmioBase + NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd), Cqhdbl, sizeof (NVME_CQHDBL))\r | |
30 | \r | |
31 | //\r | |
32 | // Base memory address enum types\r | |
33 | //\r | |
34 | enum {\r | |
35 | BASEMEM_ASQ,\r | |
36 | BASEMEM_ACQ,\r | |
37 | BASEMEM_SQ,\r | |
38 | BASEMEM_CQ,\r | |
39 | BASEMEM_PRP,\r | |
40 | MAX_BASEMEM_COUNT\r | |
41 | };\r | |
42 | \r | |
43 | //\r | |
44 | // All of base memories are 4K(0x1000) alignment\r | |
45 | //\r | |
46 | #define ALIGN(v, a) (UINTN)((((v) - 1) | ((a) - 1)) + 1)\r | |
47 | #define NVME_MEM_BASE(Private) ((UINTN)(Private->Buffer))\r | |
48 | #define NVME_ASQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r | |
49 | #define NVME_ACQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r | |
50 | #define NVME_SQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r | |
51 | #define NVME_CQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r | |
52 | #define NVME_PRP_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r | |
53 | \r | |
54 | \r | |
55 | /**\r | |
56 | Transfer MMIO Data to memory.\r | |
57 | \r | |
58 | @param[in,out] MemBuffer Destination: Memory address.\r | |
59 | @param[in] MmioAddr Source: MMIO address.\r | |
60 | @param[in] Size Size for read.\r | |
61 | \r | |
62 | @retval EFI_SUCCESS MMIO read sucessfully.\r | |
63 | \r | |
64 | **/\r | |
65 | EFI_STATUS\r | |
66 | NvmeMmioRead (\r | |
67 | IN OUT VOID *MemBuffer,\r | |
68 | IN UINTN MmioAddr,\r | |
69 | IN UINTN Size\r | |
70 | );\r | |
71 | \r | |
72 | /**\r | |
73 | Transfer memory data to MMIO.\r | |
74 | \r | |
75 | @param[in,out] MmioAddr Destination: MMIO address.\r | |
76 | @param[in] MemBuffer Source: Memory address.\r | |
77 | @param[in] Size Size for write.\r | |
78 | \r | |
79 | @retval EFI_SUCCESS MMIO write sucessfully.\r | |
80 | \r | |
81 | **/\r | |
82 | EFI_STATUS\r | |
83 | NvmeMmioWrite (\r | |
84 | IN OUT UINTN MmioAddr,\r | |
85 | IN VOID *MemBuffer,\r | |
86 | IN UINTN Size\r | |
87 | );\r | |
88 | \r | |
89 | /**\r | |
90 | Get the page offset for specific NVME based memory.\r | |
91 | \r | |
92 | @param[in] BaseMemIndex The Index of BaseMem (0-based).\r | |
93 | \r | |
94 | @retval - The page count for specific BaseMem Index\r | |
95 | \r | |
96 | **/\r | |
97 | UINT32\r | |
98 | NvmeBaseMemPageOffset (\r | |
99 | IN UINTN BaseMemIndex\r | |
100 | );\r | |
101 | \r | |
102 | /**\r | |
103 | Initialize the Nvm Express controller.\r | |
104 | \r | |
105 | @param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r | |
106 | \r | |
107 | @retval EFI_SUCCESS The NVM Express Controller is initialized successfully.\r | |
108 | @retval Others A device error occurred while initializing the controller.\r | |
109 | \r | |
110 | **/\r | |
111 | EFI_STATUS\r | |
112 | NvmeControllerInit (\r | |
113 | IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r | |
114 | );\r | |
115 | \r | |
116 | /**\r | |
117 | Get specified identify namespace data.\r | |
118 | \r | |
119 | @param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r | |
120 | @param[in] NamespaceId The specified namespace identifier.\r | |
121 | @param[in] Buffer The buffer used to store the identify namespace data.\r | |
122 | \r | |
123 | @return EFI_SUCCESS Successfully get the identify namespace data.\r | |
124 | @return EFI_DEVICE_ERROR Fail to get the identify namespace data.\r | |
125 | \r | |
126 | **/\r | |
127 | EFI_STATUS\r | |
128 | NvmeIdentifyNamespace (\r | |
129 | IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,\r | |
130 | IN UINT32 NamespaceId,\r | |
131 | IN VOID *Buffer\r | |
132 | );\r | |
133 | \r | |
134 | /**\r | |
135 | Free the DMA resources allocated by an NVME controller.\r | |
136 | \r | |
137 | @param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r | |
138 | \r | |
139 | **/\r | |
140 | VOID\r | |
141 | NvmeFreeDmaResource (\r | |
142 | IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r | |
143 | );\r | |
144 | \r | |
145 | #endif\r |