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MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
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1/** @file\r
2 This driver is used to manage SD/MMC PCI host controllers which are compliance\r
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit\r
4 System Addressing support in SD Host Controller Simplified Specification version\r
5 4.20.\r
6\r
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.\r
8\r
9 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r
10 Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>\r
11 SPDX-License-Identifier: BSD-2-Clause-Patent\r
12\r
13**/\r
14\r
15#include "SdMmcPciHcDxe.h"\r
16\r
17/**\r
18 Dump the content of SD/MMC host controller's Capability Register.\r
19\r
20 @param[in] Slot The slot number of the SD card to send the command to.\r
21 @param[in] Capability The buffer to store the capability data.\r
22\r
23**/\r
24VOID\r
25DumpCapabilityReg (\r
26 IN UINT8 Slot,\r
27 IN SD_MMC_HC_SLOT_CAP *Capability\r
28 )\r
29{\r
30 //\r
31 // Dump Capability Data\r
32 //\r
33 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));\r
34 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));\r
35 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));\r
36 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));\r
37 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));\r
38 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));\r
39 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));\r
40 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));\r
41 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));\r
42 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));\r
43 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));\r
44 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));\r
45 DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));\r
46 DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));\r
47 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));\r
48 DEBUG ((DEBUG_INFO, " SlotType "));\r
49 if (Capability->SlotType == 0x00) {\r
50 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));\r
51 } else if (Capability->SlotType == 0x01) {\r
52 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));\r
53 } else if (Capability->SlotType == 0x02) {\r
54 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));\r
55 } else {\r
56 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));\r
57 }\r
58 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));\r
59 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));\r
60 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));\r
61 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));\r
62 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));\r
63 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));\r
64 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));\r
65 if (Capability->TimerCount == 0) {\r
66 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));\r
67 } else {\r
68 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));\r
69 }\r
70 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));\r
71 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));\r
72 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));\r
73 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));\r
74 return;\r
75}\r
76\r
77/**\r
78 Read SlotInfo register from SD/MMC host controller pci config space.\r
79\r
80 @param[in] PciIo The PCI IO protocol instance.\r
81 @param[out] FirstBar The buffer to store the first BAR value.\r
82 @param[out] SlotNum The buffer to store the supported slot number.\r
83\r
84 @retval EFI_SUCCESS The operation succeeds.\r
85 @retval Others The operation fails.\r
86\r
87**/\r
88EFI_STATUS\r
89EFIAPI\r
90SdMmcHcGetSlotInfo (\r
91 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
92 OUT UINT8 *FirstBar,\r
93 OUT UINT8 *SlotNum\r
94 )\r
95{\r
96 EFI_STATUS Status;\r
97 SD_MMC_HC_SLOT_INFO SlotInfo;\r
98\r
99 Status = PciIo->Pci.Read (\r
100 PciIo,\r
101 EfiPciIoWidthUint8,\r
102 SD_MMC_HC_SLOT_OFFSET,\r
103 sizeof (SlotInfo),\r
104 &SlotInfo\r
105 );\r
106 if (EFI_ERROR (Status)) {\r
107 return Status;\r
108 }\r
109\r
110 *FirstBar = SlotInfo.FirstBar;\r
111 *SlotNum = SlotInfo.SlotNum + 1;\r
112 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);\r
113 return EFI_SUCCESS;\r
114}\r
115\r
116/**\r
117 Read/Write specified SD/MMC host controller mmio register.\r
118\r
119 @param[in] PciIo The PCI IO protocol instance.\r
120 @param[in] BarIndex The BAR index of the standard PCI Configuration\r
121 header to use as the base address for the memory\r
122 operation to perform.\r
123 @param[in] Offset The offset within the selected BAR to start the\r
124 memory operation.\r
125 @param[in] Read A boolean to indicate it's read or write operation.\r
126 @param[in] Count The width of the mmio register in bytes.\r
127 Must be 1, 2 , 4 or 8 bytes.\r
128 @param[in, out] Data For read operations, the destination buffer to store\r
129 the results. For write operations, the source buffer\r
130 to write data from. The caller is responsible for\r
131 having ownership of the data buffer and ensuring its\r
132 size not less than Count bytes.\r
133\r
134 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r
135 @retval EFI_SUCCESS The read/write operation succeeds.\r
136 @retval Others The read/write operation fails.\r
137\r
138**/\r
139EFI_STATUS\r
140EFIAPI\r
141SdMmcHcRwMmio (\r
142 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
143 IN UINT8 BarIndex,\r
144 IN UINT32 Offset,\r
145 IN BOOLEAN Read,\r
146 IN UINT8 Count,\r
147 IN OUT VOID *Data\r
148 )\r
149{\r
150 EFI_STATUS Status;\r
151 EFI_PCI_IO_PROTOCOL_WIDTH Width;\r
152\r
153 if ((PciIo == NULL) || (Data == NULL)) {\r
154 return EFI_INVALID_PARAMETER;\r
155 }\r
156\r
157 switch (Count) {\r
158 case 1:\r
159 Width = EfiPciIoWidthUint8;\r
160 break;\r
161 case 2:\r
162 Width = EfiPciIoWidthUint16;\r
163 Count = 1;\r
164 break;\r
165 case 4:\r
166 Width = EfiPciIoWidthUint32;\r
167 Count = 1;\r
168 break;\r
169 case 8:\r
170 Width = EfiPciIoWidthUint32;\r
171 Count = 2;\r
172 break;\r
173 default:\r
174 return EFI_INVALID_PARAMETER;\r
175 }\r
176\r
177 if (Read) {\r
178 Status = PciIo->Mem.Read (\r
179 PciIo,\r
180 Width,\r
181 BarIndex,\r
182 (UINT64) Offset,\r
183 Count,\r
184 Data\r
185 );\r
186 } else {\r
187 Status = PciIo->Mem.Write (\r
188 PciIo,\r
189 Width,\r
190 BarIndex,\r
191 (UINT64) Offset,\r
192 Count,\r
193 Data\r
194 );\r
195 }\r
196\r
197 return Status;\r
198}\r
199\r
200/**\r
201 Do OR operation with the value of the specified SD/MMC host controller mmio register.\r
202\r
203 @param[in] PciIo The PCI IO protocol instance.\r
204 @param[in] BarIndex The BAR index of the standard PCI Configuration\r
205 header to use as the base address for the memory\r
206 operation to perform.\r
207 @param[in] Offset The offset within the selected BAR to start the\r
208 memory operation.\r
209 @param[in] Count The width of the mmio register in bytes.\r
210 Must be 1, 2 , 4 or 8 bytes.\r
211 @param[in] OrData The pointer to the data used to do OR operation.\r
212 The caller is responsible for having ownership of\r
213 the data buffer and ensuring its size not less than\r
214 Count bytes.\r
215\r
216 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r
217 @retval EFI_SUCCESS The OR operation succeeds.\r
218 @retval Others The OR operation fails.\r
219\r
220**/\r
221EFI_STATUS\r
222EFIAPI\r
223SdMmcHcOrMmio (\r
224 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
225 IN UINT8 BarIndex,\r
226 IN UINT32 Offset,\r
227 IN UINT8 Count,\r
228 IN VOID *OrData\r
229 )\r
230{\r
231 EFI_STATUS Status;\r
232 UINT64 Data;\r
233 UINT64 Or;\r
234\r
235 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r
236 if (EFI_ERROR (Status)) {\r
237 return Status;\r
238 }\r
239\r
240 if (Count == 1) {\r
241 Or = *(UINT8*) OrData;\r
242 } else if (Count == 2) {\r
243 Or = *(UINT16*) OrData;\r
244 } else if (Count == 4) {\r
245 Or = *(UINT32*) OrData;\r
246 } else if (Count == 8) {\r
247 Or = *(UINT64*) OrData;\r
248 } else {\r
249 return EFI_INVALID_PARAMETER;\r
250 }\r
251\r
252 Data |= Or;\r
253 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r
254\r
255 return Status;\r
256}\r
257\r
258/**\r
259 Do AND operation with the value of the specified SD/MMC host controller mmio register.\r
260\r
261 @param[in] PciIo The PCI IO protocol instance.\r
262 @param[in] BarIndex The BAR index of the standard PCI Configuration\r
263 header to use as the base address for the memory\r
264 operation to perform.\r
265 @param[in] Offset The offset within the selected BAR to start the\r
266 memory operation.\r
267 @param[in] Count The width of the mmio register in bytes.\r
268 Must be 1, 2 , 4 or 8 bytes.\r
269 @param[in] AndData The pointer to the data used to do AND operation.\r
270 The caller is responsible for having ownership of\r
271 the data buffer and ensuring its size not less than\r
272 Count bytes.\r
273\r
274 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r
275 @retval EFI_SUCCESS The AND operation succeeds.\r
276 @retval Others The AND operation fails.\r
277\r
278**/\r
279EFI_STATUS\r
280EFIAPI\r
281SdMmcHcAndMmio (\r
282 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
283 IN UINT8 BarIndex,\r
284 IN UINT32 Offset,\r
285 IN UINT8 Count,\r
286 IN VOID *AndData\r
287 )\r
288{\r
289 EFI_STATUS Status;\r
290 UINT64 Data;\r
291 UINT64 And;\r
292\r
293 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r
294 if (EFI_ERROR (Status)) {\r
295 return Status;\r
296 }\r
297\r
298 if (Count == 1) {\r
299 And = *(UINT8*) AndData;\r
300 } else if (Count == 2) {\r
301 And = *(UINT16*) AndData;\r
302 } else if (Count == 4) {\r
303 And = *(UINT32*) AndData;\r
304 } else if (Count == 8) {\r
305 And = *(UINT64*) AndData;\r
306 } else {\r
307 return EFI_INVALID_PARAMETER;\r
308 }\r
309\r
310 Data &= And;\r
311 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r
312\r
313 return Status;\r
314}\r
315\r
316/**\r
317 Wait for the value of the specified MMIO register set to the test value.\r
318\r
319 @param[in] PciIo The PCI IO protocol instance.\r
320 @param[in] BarIndex The BAR index of the standard PCI Configuration\r
321 header to use as the base address for the memory\r
322 operation to perform.\r
323 @param[in] Offset The offset within the selected BAR to start the\r
324 memory operation.\r
325 @param[in] Count The width of the mmio register in bytes.\r
326 Must be 1, 2, 4 or 8 bytes.\r
327 @param[in] MaskValue The mask value of memory.\r
328 @param[in] TestValue The test value of memory.\r
329\r
330 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.\r
331 @retval EFI_SUCCESS The MMIO register has expected value.\r
332 @retval Others The MMIO operation fails.\r
333\r
334**/\r
335EFI_STATUS\r
336EFIAPI\r
337SdMmcHcCheckMmioSet (\r
338 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
339 IN UINT8 BarIndex,\r
340 IN UINT32 Offset,\r
341 IN UINT8 Count,\r
342 IN UINT64 MaskValue,\r
343 IN UINT64 TestValue\r
344 )\r
345{\r
346 EFI_STATUS Status;\r
347 UINT64 Value;\r
348\r
349 //\r
350 // Access PCI MMIO space to see if the value is the tested one.\r
351 //\r
352 Value = 0;\r
353 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);\r
354 if (EFI_ERROR (Status)) {\r
355 return Status;\r
356 }\r
357\r
358 Value &= MaskValue;\r
359\r
360 if (Value == TestValue) {\r
361 return EFI_SUCCESS;\r
362 }\r
363\r
364 return EFI_NOT_READY;\r
365}\r
366\r
367/**\r
368 Wait for the value of the specified MMIO register set to the test value.\r
369\r
370 @param[in] PciIo The PCI IO protocol instance.\r
371 @param[in] BarIndex The BAR index of the standard PCI Configuration\r
372 header to use as the base address for the memory\r
373 operation to perform.\r
374 @param[in] Offset The offset within the selected BAR to start the\r
375 memory operation.\r
376 @param[in] Count The width of the mmio register in bytes.\r
377 Must be 1, 2, 4 or 8 bytes.\r
378 @param[in] MaskValue The mask value of memory.\r
379 @param[in] TestValue The test value of memory.\r
380 @param[in] Timeout The time out value for wait memory set, uses 1\r
381 microsecond as a unit.\r
382\r
383 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r
384 range.\r
385 @retval EFI_SUCCESS The MMIO register has expected value.\r
386 @retval Others The MMIO operation fails.\r
387\r
388**/\r
389EFI_STATUS\r
390EFIAPI\r
391SdMmcHcWaitMmioSet (\r
392 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
393 IN UINT8 BarIndex,\r
394 IN UINT32 Offset,\r
395 IN UINT8 Count,\r
396 IN UINT64 MaskValue,\r
397 IN UINT64 TestValue,\r
398 IN UINT64 Timeout\r
399 )\r
400{\r
401 EFI_STATUS Status;\r
402 BOOLEAN InfiniteWait;\r
403\r
404 if (Timeout == 0) {\r
405 InfiniteWait = TRUE;\r
406 } else {\r
407 InfiniteWait = FALSE;\r
408 }\r
409\r
410 while (InfiniteWait || (Timeout > 0)) {\r
411 Status = SdMmcHcCheckMmioSet (\r
412 PciIo,\r
413 BarIndex,\r
414 Offset,\r
415 Count,\r
416 MaskValue,\r
417 TestValue\r
418 );\r
419 if (Status != EFI_NOT_READY) {\r
420 return Status;\r
421 }\r
422\r
423 //\r
424 // Stall for 1 microsecond.\r
425 //\r
426 gBS->Stall (1);\r
427\r
428 Timeout--;\r
429 }\r
430\r
431 return EFI_TIMEOUT;\r
432}\r
433\r
434/**\r
435 Get the controller version information from the specified slot.\r
436\r
437 @param[in] PciIo The PCI IO protocol instance.\r
438 @param[in] Slot The slot number of the SD card to send the command to.\r
439 @param[out] Version The buffer to store the version information.\r
440\r
441 @retval EFI_SUCCESS The operation executes successfully.\r
442 @retval Others The operation fails.\r
443\r
444**/\r
445EFI_STATUS\r
446SdMmcHcGetControllerVersion (\r
447 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
448 IN UINT8 Slot,\r
449 OUT UINT16 *Version\r
450 )\r
451{\r
452 EFI_STATUS Status;\r
453\r
454 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);\r
455 if (EFI_ERROR (Status)) {\r
456 return Status;\r
457 }\r
458\r
459 *Version &= 0xFF;\r
460\r
461 return EFI_SUCCESS;\r
462}\r
463\r
464/**\r
465 Software reset the specified SD/MMC host controller and enable all interrupts.\r
466\r
467 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
468 @param[in] Slot The slot number of the SD card to send the command to.\r
469\r
470 @retval EFI_SUCCESS The software reset executes successfully.\r
471 @retval Others The software reset fails.\r
472\r
473**/\r
474EFI_STATUS\r
475SdMmcHcReset (\r
476 IN SD_MMC_HC_PRIVATE_DATA *Private,\r
477 IN UINT8 Slot\r
478 )\r
479{\r
480 EFI_STATUS Status;\r
481 UINT8 SwReset;\r
482 EFI_PCI_IO_PROTOCOL *PciIo;\r
483\r
484 //\r
485 // Notify the SD/MMC override protocol that we are about to reset\r
486 // the SD/MMC host controller.\r
487 //\r
488 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
489 Status = mOverride->NotifyPhase (\r
490 Private->ControllerHandle,\r
491 Slot,\r
492 EdkiiSdMmcResetPre,\r
493 NULL);\r
494 if (EFI_ERROR (Status)) {\r
495 DEBUG ((DEBUG_WARN,\r
496 "%a: SD/MMC pre reset notifier callback failed - %r\n",\r
497 __FUNCTION__, Status));\r
498 return Status;\r
499 }\r
500 }\r
501\r
502 PciIo = Private->PciIo;\r
503 SwReset = BIT0;\r
504 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);\r
505\r
506 if (EFI_ERROR (Status)) {\r
507 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));\r
508 return Status;\r
509 }\r
510\r
511 Status = SdMmcHcWaitMmioSet (\r
512 PciIo,\r
513 Slot,\r
514 SD_MMC_HC_SW_RST,\r
515 sizeof (SwReset),\r
516 BIT0,\r
517 0x00,\r
518 SD_MMC_HC_GENERIC_TIMEOUT\r
519 );\r
520 if (EFI_ERROR (Status)) {\r
521 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));\r
522 return Status;\r
523 }\r
524\r
525 //\r
526 // Enable all interrupt after reset all.\r
527 //\r
528 Status = SdMmcHcEnableInterrupt (PciIo, Slot);\r
529 if (EFI_ERROR (Status)) {\r
530 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",\r
531 Status));\r
532 return Status;\r
533 }\r
534\r
535 //\r
536 // Notify the SD/MMC override protocol that we have just reset\r
537 // the SD/MMC host controller.\r
538 //\r
539 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
540 Status = mOverride->NotifyPhase (\r
541 Private->ControllerHandle,\r
542 Slot,\r
543 EdkiiSdMmcResetPost,\r
544 NULL);\r
545 if (EFI_ERROR (Status)) {\r
546 DEBUG ((DEBUG_WARN,\r
547 "%a: SD/MMC post reset notifier callback failed - %r\n",\r
548 __FUNCTION__, Status));\r
549 }\r
550 }\r
551\r
552 return Status;\r
553}\r
554\r
555/**\r
556 Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
557 register.\r
558\r
559 @param[in] PciIo The PCI IO protocol instance.\r
560 @param[in] Slot The slot number of the SD card to send the command to.\r
561\r
562 @retval EFI_SUCCESS The operation executes successfully.\r
563 @retval Others The operation fails.\r
564\r
565**/\r
566EFI_STATUS\r
567SdMmcHcEnableInterrupt (\r
568 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
569 IN UINT8 Slot\r
570 )\r
571{\r
572 EFI_STATUS Status;\r
573 UINT16 IntStatus;\r
574\r
575 //\r
576 // Enable all bits in Error Interrupt Status Enable Register\r
577 //\r
578 IntStatus = 0xFFFF;\r
579 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
580 if (EFI_ERROR (Status)) {\r
581 return Status;\r
582 }\r
583 //\r
584 // Enable all bits in Normal Interrupt Status Enable Register\r
585 //\r
586 IntStatus = 0xFFFF;\r
587 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
588\r
589 return Status;\r
590}\r
591\r
592/**\r
593 Get the capability data from the specified slot.\r
594\r
595 @param[in] PciIo The PCI IO protocol instance.\r
596 @param[in] Slot The slot number of the SD card to send the command to.\r
597 @param[out] Capability The buffer to store the capability data.\r
598\r
599 @retval EFI_SUCCESS The operation executes successfully.\r
600 @retval Others The operation fails.\r
601\r
602**/\r
603EFI_STATUS\r
604SdMmcHcGetCapability (\r
605 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
606 IN UINT8 Slot,\r
607 OUT SD_MMC_HC_SLOT_CAP *Capability\r
608 )\r
609{\r
610 EFI_STATUS Status;\r
611 UINT64 Cap;\r
612\r
613 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);\r
614 if (EFI_ERROR (Status)) {\r
615 return Status;\r
616 }\r
617\r
618 CopyMem (Capability, &Cap, sizeof (Cap));\r
619\r
620 return EFI_SUCCESS;\r
621}\r
622\r
623/**\r
624 Get the maximum current capability data from the specified slot.\r
625\r
626 @param[in] PciIo The PCI IO protocol instance.\r
627 @param[in] Slot The slot number of the SD card to send the command to.\r
628 @param[out] MaxCurrent The buffer to store the maximum current capability data.\r
629\r
630 @retval EFI_SUCCESS The operation executes successfully.\r
631 @retval Others The operation fails.\r
632\r
633**/\r
634EFI_STATUS\r
635SdMmcHcGetMaxCurrent (\r
636 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
637 IN UINT8 Slot,\r
638 OUT UINT64 *MaxCurrent\r
639 )\r
640{\r
641 EFI_STATUS Status;\r
642\r
643 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);\r
644\r
645 return Status;\r
646}\r
647\r
648/**\r
649 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r
650 slot.\r
651\r
652 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
653\r
654 @param[in] PciIo The PCI IO protocol instance.\r
655 @param[in] Slot The slot number of the SD card to send the command to.\r
656 @param[out] MediaPresent The pointer to the media present boolean value.\r
657\r
658 @retval EFI_SUCCESS There is no media change happened.\r
659 @retval EFI_MEDIA_CHANGED There is media change happened.\r
660 @retval Others The detection fails.\r
661\r
662**/\r
663EFI_STATUS\r
664SdMmcHcCardDetect (\r
665 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
666 IN UINT8 Slot,\r
667 OUT BOOLEAN *MediaPresent\r
668 )\r
669{\r
670 EFI_STATUS Status;\r
671 UINT16 Data;\r
672 UINT32 PresentState;\r
673\r
674 //\r
675 // Check Present State Register to see if there is a card presented.\r
676 //\r
677 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r
678 if (EFI_ERROR (Status)) {\r
679 return Status;\r
680 }\r
681\r
682 if ((PresentState & BIT16) != 0) {\r
683 *MediaPresent = TRUE;\r
684 } else {\r
685 *MediaPresent = FALSE;\r
686 }\r
687\r
688 //\r
689 // Check Normal Interrupt Status Register\r
690 //\r
691 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);\r
692 if (EFI_ERROR (Status)) {\r
693 return Status;\r
694 }\r
695\r
696 if ((Data & (BIT6 | BIT7)) != 0) {\r
697 //\r
698 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.\r
699 //\r
700 Data &= BIT6 | BIT7;\r
701 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);\r
702 if (EFI_ERROR (Status)) {\r
703 return Status;\r
704 }\r
705\r
706 return EFI_MEDIA_CHANGED;\r
707 }\r
708\r
709 return EFI_SUCCESS;\r
710}\r
711\r
712/**\r
713 Stop SD/MMC card clock.\r
714\r
715 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
716\r
717 @param[in] PciIo The PCI IO protocol instance.\r
718 @param[in] Slot The slot number of the SD card to send the command to.\r
719\r
720 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.\r
721 @retval Others Fail to stop SD/MMC clock.\r
722\r
723**/\r
724EFI_STATUS\r
725SdMmcHcStopClock (\r
726 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
727 IN UINT8 Slot\r
728 )\r
729{\r
730 EFI_STATUS Status;\r
731 UINT32 PresentState;\r
732 UINT16 ClockCtrl;\r
733\r
734 //\r
735 // Ensure no SD transactions are occurring on the SD Bus by\r
736 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)\r
737 // in the Present State register to be 0.\r
738 //\r
739 Status = SdMmcHcWaitMmioSet (\r
740 PciIo,\r
741 Slot,\r
742 SD_MMC_HC_PRESENT_STATE,\r
743 sizeof (PresentState),\r
744 BIT0 | BIT1,\r
745 0,\r
746 SD_MMC_HC_GENERIC_TIMEOUT\r
747 );\r
748 if (EFI_ERROR (Status)) {\r
749 return Status;\r
750 }\r
751\r
752 //\r
753 // Set SD Clock Enable in the Clock Control register to 0\r
754 //\r
755 ClockCtrl = (UINT16)~BIT2;\r
756 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
757\r
758 return Status;\r
759}\r
760\r
761/**\r
762 Start the SD clock.\r
763\r
764 @param[in] PciIo The PCI IO protocol instance.\r
765 @param[in] Slot The slot number.\r
766\r
767 @retval EFI_SUCCESS Succeeded to start the SD clock.\r
768 @retval Others Failed to start the SD clock.\r
769**/\r
770EFI_STATUS\r
771SdMmcHcStartSdClock (\r
772 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
773 IN UINT8 Slot\r
774 )\r
775{\r
776 UINT16 ClockCtrl;\r
777\r
778 //\r
779 // Set SD Clock Enable in the Clock Control register to 1\r
780 //\r
781 ClockCtrl = BIT2;\r
782 return SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
783}\r
784\r
785/**\r
786 SD/MMC card clock supply.\r
787\r
788 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r
789\r
790 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
791 @param[in] Slot The slot number of the SD card to send the command to.\r
792 @param[in] BusTiming BusTiming at which the frequency change is done.\r
793 @param[in] FirstTimeSetup Flag to indicate whether the clock is being setup for the first time.\r
794 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r
795\r
796 @retval EFI_SUCCESS The clock is supplied successfully.\r
797 @retval Others The clock isn't supplied successfully.\r
798\r
799**/\r
800EFI_STATUS\r
801SdMmcHcClockSupply (\r
802 IN SD_MMC_HC_PRIVATE_DATA *Private,\r
803 IN UINT8 Slot,\r
804 IN SD_MMC_BUS_MODE BusTiming,\r
805 IN BOOLEAN FirstTimeSetup,\r
806 IN UINT64 ClockFreq\r
807 )\r
808{\r
809 EFI_STATUS Status;\r
810 UINT32 SettingFreq;\r
811 UINT32 Divisor;\r
812 UINT32 Remainder;\r
813 UINT16 ClockCtrl;\r
814 UINT32 BaseClkFreq;\r
815 UINT16 ControllerVer;\r
816 EFI_PCI_IO_PROTOCOL *PciIo;\r
817\r
818 PciIo = Private->PciIo;\r
819 BaseClkFreq = Private->BaseClkFreq[Slot];\r
820 ControllerVer = Private->ControllerVersion[Slot];\r
821\r
822 if (BaseClkFreq == 0 || ClockFreq == 0) {\r
823 return EFI_INVALID_PARAMETER;\r
824 }\r
825\r
826 if (ClockFreq > (BaseClkFreq * 1000)) {\r
827 ClockFreq = BaseClkFreq * 1000;\r
828 }\r
829\r
830 //\r
831 // Calculate the divisor of base frequency.\r
832 //\r
833 Divisor = 0;\r
834 SettingFreq = BaseClkFreq * 1000;\r
835 while (ClockFreq < SettingFreq) {\r
836 Divisor++;\r
837\r
838 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);\r
839 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);\r
840 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {\r
841 break;\r
842 }\r
843 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {\r
844 SettingFreq ++;\r
845 }\r
846 }\r
847\r
848 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));\r
849\r
850 //\r
851 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r
852 //\r
853 if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&\r
854 (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {\r
855 ASSERT (Divisor <= 0x3FF);\r
856 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r
857 } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||\r
858 (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {\r
859 //\r
860 // Only the most significant bit can be used as divisor.\r
861 //\r
862 if (((Divisor - 1) & Divisor) != 0) {\r
863 Divisor = 1 << (HighBitSet32 (Divisor) + 1);\r
864 }\r
865 ASSERT (Divisor <= 0x80);\r
866 ClockCtrl = (Divisor & 0xFF) << 8;\r
867 } else {\r
868 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));\r
869 return EFI_UNSUPPORTED;\r
870 }\r
871\r
872 //\r
873 // Stop bus clock at first\r
874 //\r
875 Status = SdMmcHcStopClock (PciIo, Slot);\r
876 if (EFI_ERROR (Status)) {\r
877 return Status;\r
878 }\r
879\r
880 //\r
881 // Supply clock frequency with specified divisor\r
882 //\r
883 ClockCtrl |= BIT0;\r
884 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r
885 if (EFI_ERROR (Status)) {\r
886 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));\r
887 return Status;\r
888 }\r
889\r
890 //\r
891 // Wait Internal Clock Stable in the Clock Control register to be 1\r
892 //\r
893 Status = SdMmcHcWaitMmioSet (\r
894 PciIo,\r
895 Slot,\r
896 SD_MMC_HC_CLOCK_CTRL,\r
897 sizeof (ClockCtrl),\r
898 BIT1,\r
899 BIT1,\r
900 SD_MMC_HC_GENERIC_TIMEOUT\r
901 );\r
902 if (EFI_ERROR (Status)) {\r
903 return Status;\r
904 }\r
905\r
906 Status = SdMmcHcStartSdClock (PciIo, Slot);\r
907 if (EFI_ERROR (Status)) {\r
908 return Status;\r
909 }\r
910\r
911 //\r
912 // We don't notify the platform on first time setup to avoid changing\r
913 // legacy behavior. During first time setup we also don't know what type\r
914 // of the card slot it is and which enum value of BusTiming applies.\r
915 //\r
916 if (!FirstTimeSetup && mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
917 Status = mOverride->NotifyPhase (\r
918 Private->ControllerHandle,\r
919 Slot,\r
920 EdkiiSdMmcSwitchClockFreqPost,\r
921 &BusTiming\r
922 );\r
923 if (EFI_ERROR (Status)) {\r
924 DEBUG ((\r
925 DEBUG_ERROR,\r
926 "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",\r
927 __FUNCTION__,\r
928 Status\r
929 ));\r
930 return Status;\r
931 }\r
932 }\r
933\r
934 Private->Slot[Slot].CurrentFreq = ClockFreq;\r
935\r
936 return Status;\r
937}\r
938\r
939/**\r
940 SD/MMC bus power control.\r
941\r
942 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
943\r
944 @param[in] PciIo The PCI IO protocol instance.\r
945 @param[in] Slot The slot number of the SD card to send the command to.\r
946 @param[in] PowerCtrl The value setting to the power control register.\r
947\r
948 @retval TRUE There is a SD/MMC card attached.\r
949 @retval FALSE There is no a SD/MMC card attached.\r
950\r
951**/\r
952EFI_STATUS\r
953SdMmcHcPowerControl (\r
954 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
955 IN UINT8 Slot,\r
956 IN UINT8 PowerCtrl\r
957 )\r
958{\r
959 EFI_STATUS Status;\r
960\r
961 //\r
962 // Clr SD Bus Power\r
963 //\r
964 PowerCtrl &= (UINT8)~BIT0;\r
965 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
966 if (EFI_ERROR (Status)) {\r
967 return Status;\r
968 }\r
969\r
970 //\r
971 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r
972 //\r
973 PowerCtrl |= BIT0;\r
974 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
975\r
976 return Status;\r
977}\r
978\r
979/**\r
980 Set the SD/MMC bus width.\r
981\r
982 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
983\r
984 @param[in] PciIo The PCI IO protocol instance.\r
985 @param[in] Slot The slot number of the SD card to send the command to.\r
986 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r
987\r
988 @retval EFI_SUCCESS The bus width is set successfully.\r
989 @retval Others The bus width isn't set successfully.\r
990\r
991**/\r
992EFI_STATUS\r
993SdMmcHcSetBusWidth (\r
994 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
995 IN UINT8 Slot,\r
996 IN UINT16 BusWidth\r
997 )\r
998{\r
999 EFI_STATUS Status;\r
1000 UINT8 HostCtrl1;\r
1001\r
1002 if (BusWidth == 1) {\r
1003 HostCtrl1 = (UINT8)~(BIT5 | BIT1);\r
1004 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
1005 } else if (BusWidth == 4) {\r
1006 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
1007 if (EFI_ERROR (Status)) {\r
1008 return Status;\r
1009 }\r
1010 HostCtrl1 |= BIT1;\r
1011 HostCtrl1 &= (UINT8)~BIT5;\r
1012 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
1013 } else if (BusWidth == 8) {\r
1014 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
1015 if (EFI_ERROR (Status)) {\r
1016 return Status;\r
1017 }\r
1018 HostCtrl1 &= (UINT8)~BIT1;\r
1019 HostCtrl1 |= BIT5;\r
1020 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
1021 } else {\r
1022 ASSERT (FALSE);\r
1023 return EFI_INVALID_PARAMETER;\r
1024 }\r
1025\r
1026 return Status;\r
1027}\r
1028\r
1029/**\r
1030 Configure V4 controller enhancements at initialization.\r
1031\r
1032 @param[in] PciIo The PCI IO protocol instance.\r
1033 @param[in] Slot The slot number of the SD card to send the command to.\r
1034 @param[in] Capability The capability of the slot.\r
1035 @param[in] ControllerVer The version of host controller.\r
1036\r
1037 @retval EFI_SUCCESS The clock is supplied successfully.\r
1038\r
1039**/\r
1040EFI_STATUS\r
1041SdMmcHcInitV4Enhancements (\r
1042 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1043 IN UINT8 Slot,\r
1044 IN SD_MMC_HC_SLOT_CAP Capability,\r
1045 IN UINT16 ControllerVer\r
1046 )\r
1047{\r
1048 EFI_STATUS Status;\r
1049 UINT16 HostCtrl2;\r
1050\r
1051 //\r
1052 // Check if controller version V4 or higher\r
1053 //\r
1054 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {\r
1055 HostCtrl2 = SD_MMC_HC_V4_EN;\r
1056 //\r
1057 // Check if controller version V4.0\r
1058 //\r
1059 if (ControllerVer == SD_MMC_HC_CTRL_VER_400) {\r
1060 //\r
1061 // Check if 64bit support is available\r
1062 //\r
1063 if (Capability.SysBus64V3 != 0) {\r
1064 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;\r
1065 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));\r
1066 }\r
1067 }\r
1068 //\r
1069 // Check if controller version V4.10 or higher\r
1070 //\r
1071 else if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {\r
1072 //\r
1073 // Check if 64bit support is available\r
1074 //\r
1075 if (Capability.SysBus64V4 != 0) {\r
1076 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;\r
1077 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));\r
1078 }\r
1079 HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;\r
1080 DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));\r
1081 }\r
1082 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
1083 if (EFI_ERROR (Status)) {\r
1084 return Status;\r
1085 }\r
1086 }\r
1087\r
1088 return EFI_SUCCESS;\r
1089}\r
1090\r
1091/**\r
1092 Supply SD/MMC card with maximum voltage at initialization.\r
1093\r
1094 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
1095\r
1096 @param[in] PciIo The PCI IO protocol instance.\r
1097 @param[in] Slot The slot number of the SD card to send the command to.\r
1098 @param[in] Capability The capability of the slot.\r
1099\r
1100 @retval EFI_SUCCESS The voltage is supplied successfully.\r
1101 @retval Others The voltage isn't supplied successfully.\r
1102\r
1103**/\r
1104EFI_STATUS\r
1105SdMmcHcInitPowerVoltage (\r
1106 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1107 IN UINT8 Slot,\r
1108 IN SD_MMC_HC_SLOT_CAP Capability\r
1109 )\r
1110{\r
1111 EFI_STATUS Status;\r
1112 UINT8 MaxVoltage;\r
1113 UINT8 HostCtrl2;\r
1114\r
1115 //\r
1116 // Calculate supported maximum voltage according to SD Bus Voltage Select\r
1117 //\r
1118 if (Capability.Voltage33 != 0) {\r
1119 //\r
1120 // Support 3.3V\r
1121 //\r
1122 MaxVoltage = 0x0E;\r
1123 } else if (Capability.Voltage30 != 0) {\r
1124 //\r
1125 // Support 3.0V\r
1126 //\r
1127 MaxVoltage = 0x0C;\r
1128 } else if (Capability.Voltage18 != 0) {\r
1129 //\r
1130 // Support 1.8V\r
1131 //\r
1132 MaxVoltage = 0x0A;\r
1133 HostCtrl2 = BIT3;\r
1134 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
1135 gBS->Stall (5000);\r
1136 if (EFI_ERROR (Status)) {\r
1137 return Status;\r
1138 }\r
1139 } else {\r
1140 ASSERT (FALSE);\r
1141 return EFI_DEVICE_ERROR;\r
1142 }\r
1143\r
1144 //\r
1145 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r
1146 //\r
1147 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);\r
1148\r
1149 return Status;\r
1150}\r
1151\r
1152/**\r
1153 Initialize the Timeout Control register with most conservative value at initialization.\r
1154\r
1155 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
1156\r
1157 @param[in] PciIo The PCI IO protocol instance.\r
1158 @param[in] Slot The slot number of the SD card to send the command to.\r
1159\r
1160 @retval EFI_SUCCESS The timeout control register is configured successfully.\r
1161 @retval Others The timeout control register isn't configured successfully.\r
1162\r
1163**/\r
1164EFI_STATUS\r
1165SdMmcHcInitTimeoutCtrl (\r
1166 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1167 IN UINT8 Slot\r
1168 )\r
1169{\r
1170 EFI_STATUS Status;\r
1171 UINT8 Timeout;\r
1172\r
1173 Timeout = 0x0E;\r
1174 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);\r
1175\r
1176 return Status;\r
1177}\r
1178\r
1179/**\r
1180 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value\r
1181 at initialization.\r
1182\r
1183 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
1184 @param[in] Slot The slot number of the SD card to send the command to.\r
1185\r
1186 @retval EFI_SUCCESS The host controller is initialized successfully.\r
1187 @retval Others The host controller isn't initialized successfully.\r
1188\r
1189**/\r
1190EFI_STATUS\r
1191SdMmcHcInitHost (\r
1192 IN SD_MMC_HC_PRIVATE_DATA *Private,\r
1193 IN UINT8 Slot\r
1194 )\r
1195{\r
1196 EFI_STATUS Status;\r
1197 EFI_PCI_IO_PROTOCOL *PciIo;\r
1198 SD_MMC_HC_SLOT_CAP Capability;\r
1199\r
1200 //\r
1201 // Notify the SD/MMC override protocol that we are about to initialize\r
1202 // the SD/MMC host controller.\r
1203 //\r
1204 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
1205 Status = mOverride->NotifyPhase (\r
1206 Private->ControllerHandle,\r
1207 Slot,\r
1208 EdkiiSdMmcInitHostPre,\r
1209 NULL);\r
1210 if (EFI_ERROR (Status)) {\r
1211 DEBUG ((DEBUG_WARN,\r
1212 "%a: SD/MMC pre init notifier callback failed - %r\n",\r
1213 __FUNCTION__, Status));\r
1214 return Status;\r
1215 }\r
1216 }\r
1217\r
1218 PciIo = Private->PciIo;\r
1219 Capability = Private->Capability[Slot];\r
1220\r
1221 Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);\r
1222 if (EFI_ERROR (Status)) {\r
1223 return Status;\r
1224 }\r
1225\r
1226 //\r
1227 // Perform first time clock setup with 400 KHz frequency.\r
1228 // We send the 0 as the BusTiming value because at this time\r
1229 // we still do not know the slot type and which enum value will apply.\r
1230 // Since it is a first time setup SdMmcHcClockSupply won't notify\r
1231 // the platofrm driver anyway so it doesn't matter.\r
1232 //\r
1233 Status = SdMmcHcClockSupply (Private, Slot, 0, TRUE, 400);\r
1234 if (EFI_ERROR (Status)) {\r
1235 return Status;\r
1236 }\r
1237\r
1238 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);\r
1239 if (EFI_ERROR (Status)) {\r
1240 return Status;\r
1241 }\r
1242\r
1243 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);\r
1244 if (EFI_ERROR (Status)) {\r
1245 return Status;\r
1246 }\r
1247\r
1248 //\r
1249 // Notify the SD/MMC override protocol that we are have just initialized\r
1250 // the SD/MMC host controller.\r
1251 //\r
1252 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
1253 Status = mOverride->NotifyPhase (\r
1254 Private->ControllerHandle,\r
1255 Slot,\r
1256 EdkiiSdMmcInitHostPost,\r
1257 NULL);\r
1258 if (EFI_ERROR (Status)) {\r
1259 DEBUG ((DEBUG_WARN,\r
1260 "%a: SD/MMC post init notifier callback failed - %r\n",\r
1261 __FUNCTION__, Status));\r
1262 }\r
1263 }\r
1264 return Status;\r
1265}\r
1266\r
1267/**\r
1268 Set SD Host Controler control 2 registry according to selected speed.\r
1269\r
1270 @param[in] ControllerHandle The handle of the controller.\r
1271 @param[in] PciIo The PCI IO protocol instance.\r
1272 @param[in] Slot The slot number of the SD card to send the command to.\r
1273 @param[in] Timing The timing to select.\r
1274\r
1275 @retval EFI_SUCCESS The timing is set successfully.\r
1276 @retval Others The timing isn't set successfully.\r
1277**/\r
1278EFI_STATUS\r
1279SdMmcHcUhsSignaling (\r
1280 IN EFI_HANDLE ControllerHandle,\r
1281 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1282 IN UINT8 Slot,\r
1283 IN SD_MMC_BUS_MODE Timing\r
1284 )\r
1285{\r
1286 EFI_STATUS Status;\r
1287 UINT8 HostCtrl2;\r
1288\r
1289 HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;\r
1290 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
1291 if (EFI_ERROR (Status)) {\r
1292 return Status;\r
1293 }\r
1294\r
1295 switch (Timing) {\r
1296 case SdMmcUhsSdr12:\r
1297 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;\r
1298 break;\r
1299 case SdMmcUhsSdr25:\r
1300 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;\r
1301 break;\r
1302 case SdMmcUhsSdr50:\r
1303 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;\r
1304 break;\r
1305 case SdMmcUhsSdr104:\r
1306 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;\r
1307 break;\r
1308 case SdMmcUhsDdr50:\r
1309 HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;\r
1310 break;\r
1311 case SdMmcMmcLegacy:\r
1312 HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;\r
1313 break;\r
1314 case SdMmcMmcHsSdr:\r
1315 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;\r
1316 break;\r
1317 case SdMmcMmcHsDdr:\r
1318 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;\r
1319 break;\r
1320 case SdMmcMmcHs200:\r
1321 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;\r
1322 break;\r
1323 case SdMmcMmcHs400:\r
1324 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;\r
1325 break;\r
1326 default:\r
1327 HostCtrl2 = 0;\r
1328 break;\r
1329 }\r
1330 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
1331 if (EFI_ERROR (Status)) {\r
1332 return Status;\r
1333 }\r
1334\r
1335 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
1336 Status = mOverride->NotifyPhase (\r
1337 ControllerHandle,\r
1338 Slot,\r
1339 EdkiiSdMmcUhsSignaling,\r
1340 &Timing\r
1341 );\r
1342 if (EFI_ERROR (Status)) {\r
1343 DEBUG ((\r
1344 DEBUG_ERROR,\r
1345 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",\r
1346 __FUNCTION__,\r
1347 Status\r
1348 ));\r
1349 return Status;\r
1350 }\r
1351 }\r
1352\r
1353 return EFI_SUCCESS;\r
1354}\r
1355\r
1356/**\r
1357 Set driver strength in host controller.\r
1358\r
1359 @param[in] PciIo The PCI IO protocol instance.\r
1360 @param[in] SlotIndex The slot index of the card.\r
1361 @param[in] DriverStrength DriverStrength to set in the controller.\r
1362\r
1363 @retval EFI_SUCCESS Driver strength programmed successfully.\r
1364 @retval Others Failed to set driver strength.\r
1365**/\r
1366EFI_STATUS\r
1367SdMmcSetDriverStrength (\r
1368 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1369 IN UINT8 SlotIndex,\r
1370 IN SD_DRIVER_STRENGTH_TYPE DriverStrength\r
1371 )\r
1372{\r
1373 EFI_STATUS Status;\r
1374 UINT16 HostCtrl2;\r
1375\r
1376 if (DriverStrength == SdDriverStrengthIgnore) {\r
1377 return EFI_SUCCESS;\r
1378 }\r
1379\r
1380 HostCtrl2 = (UINT16)~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;\r
1381 Status = SdMmcHcAndMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
1382 if (EFI_ERROR (Status)) {\r
1383 return Status;\r
1384 }\r
1385\r
1386 HostCtrl2 = (DriverStrength << 4) & SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;\r
1387 return SdMmcHcOrMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
1388}\r
1389\r
1390/**\r
1391 Turn on/off LED.\r
1392\r
1393 @param[in] PciIo The PCI IO protocol instance.\r
1394 @param[in] Slot The slot number of the SD card to send the command to.\r
1395 @param[in] On The boolean to turn on/off LED.\r
1396\r
1397 @retval EFI_SUCCESS The LED is turned on/off successfully.\r
1398 @retval Others The LED isn't turned on/off successfully.\r
1399\r
1400**/\r
1401EFI_STATUS\r
1402SdMmcHcLedOnOff (\r
1403 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1404 IN UINT8 Slot,\r
1405 IN BOOLEAN On\r
1406 )\r
1407{\r
1408 EFI_STATUS Status;\r
1409 UINT8 HostCtrl1;\r
1410\r
1411 if (On) {\r
1412 HostCtrl1 = BIT0;\r
1413 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
1414 } else {\r
1415 HostCtrl1 = (UINT8)~BIT0;\r
1416 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
1417 }\r
1418\r
1419 return Status;\r
1420}\r
1421\r
1422/**\r
1423 Build ADMA descriptor table for transfer.\r
1424\r
1425 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.\r
1426\r
1427 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r
1428 @param[in] ControllerVer The version of host controller.\r
1429\r
1430 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.\r
1431 @retval Others The ADMA descriptor table isn't created successfully.\r
1432\r
1433**/\r
1434EFI_STATUS\r
1435BuildAdmaDescTable (\r
1436 IN SD_MMC_HC_TRB *Trb,\r
1437 IN UINT16 ControllerVer\r
1438 )\r
1439{\r
1440 EFI_PHYSICAL_ADDRESS Data;\r
1441 UINT64 DataLen;\r
1442 UINT64 Entries;\r
1443 UINT32 Index;\r
1444 UINT64 Remaining;\r
1445 UINT64 Address;\r
1446 UINTN TableSize;\r
1447 EFI_PCI_IO_PROTOCOL *PciIo;\r
1448 EFI_STATUS Status;\r
1449 UINTN Bytes;\r
1450 UINT32 AdmaMaxDataPerLine;\r
1451 UINT32 DescSize;\r
1452 VOID *AdmaDesc;\r
1453\r
1454 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;\r
1455 DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);\r
1456 AdmaDesc = NULL;\r
1457\r
1458 Data = Trb->DataPhy;\r
1459 DataLen = Trb->DataLen;\r
1460 PciIo = Trb->Private->PciIo;\r
1461\r
1462 //\r
1463 // Check for valid ranges in 32bit ADMA Descriptor Table\r
1464 //\r
1465 if ((Trb->Mode == SdMmcAdma32bMode) &&\r
1466 ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {\r
1467 return EFI_INVALID_PARAMETER;\r
1468 }\r
1469 //\r
1470 // Check address field alignment\r
1471 //\r
1472 if (Trb->Mode != SdMmcAdma32bMode) {\r
1473 //\r
1474 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)\r
1475 //\r
1476 if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {\r
1477 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));\r
1478 }\r
1479 } else {\r
1480 //\r
1481 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r
1482 //\r
1483 if ((Data & (BIT0 | BIT1)) != 0) {\r
1484 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r
1485 }\r
1486 }\r
1487\r
1488 //\r
1489 // Configure 64b ADMA.\r
1490 //\r
1491 if (Trb->Mode == SdMmcAdma64bV3Mode) {\r
1492 DescSize = sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE);\r
1493 }else if (Trb->Mode == SdMmcAdma64bV4Mode) {\r
1494 DescSize = sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE);\r
1495 }\r
1496 //\r
1497 // Configure 26b data length.\r
1498 //\r
1499 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r
1500 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;\r
1501 }\r
1502\r
1503 Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);\r
1504 TableSize = (UINTN)MultU64x32 (Entries, DescSize);\r
1505 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);\r
1506 Status = PciIo->AllocateBuffer (\r
1507 PciIo,\r
1508 AllocateAnyPages,\r
1509 EfiBootServicesData,\r
1510 EFI_SIZE_TO_PAGES (TableSize),\r
1511 (VOID **)&AdmaDesc,\r
1512 0\r
1513 );\r
1514 if (EFI_ERROR (Status)) {\r
1515 return EFI_OUT_OF_RESOURCES;\r
1516 }\r
1517 ZeroMem (AdmaDesc, TableSize);\r
1518 Bytes = TableSize;\r
1519 Status = PciIo->Map (\r
1520 PciIo,\r
1521 EfiPciIoOperationBusMasterCommonBuffer,\r
1522 AdmaDesc,\r
1523 &Bytes,\r
1524 &Trb->AdmaDescPhy,\r
1525 &Trb->AdmaMap\r
1526 );\r
1527\r
1528 if (EFI_ERROR (Status) || (Bytes != TableSize)) {\r
1529 //\r
1530 // Map error or unable to map the whole RFis buffer into a contiguous region.\r
1531 //\r
1532 PciIo->FreeBuffer (\r
1533 PciIo,\r
1534 EFI_SIZE_TO_PAGES (TableSize),\r
1535 AdmaDesc\r
1536 );\r
1537 return EFI_OUT_OF_RESOURCES;\r
1538 }\r
1539\r
1540 if ((Trb->Mode == SdMmcAdma32bMode) &&\r
1541 (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {\r
1542 //\r
1543 // The ADMA doesn't support 64bit addressing.\r
1544 //\r
1545 PciIo->Unmap (\r
1546 PciIo,\r
1547 Trb->AdmaMap\r
1548 );\r
1549 Trb->AdmaMap = NULL;\r
1550\r
1551 PciIo->FreeBuffer (\r
1552 PciIo,\r
1553 EFI_SIZE_TO_PAGES (TableSize),\r
1554 AdmaDesc\r
1555 );\r
1556 return EFI_DEVICE_ERROR;\r
1557 }\r
1558\r
1559 Remaining = DataLen;\r
1560 Address = Data;\r
1561 if (Trb->Mode == SdMmcAdma32bMode) {\r
1562 Trb->Adma32Desc = AdmaDesc;\r
1563 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r
1564 Trb->Adma64V3Desc = AdmaDesc;\r
1565 } else {\r
1566 Trb->Adma64V4Desc = AdmaDesc;\r
1567 }\r
1568\r
1569 for (Index = 0; Index < Entries; Index++) {\r
1570 if (Trb->Mode == SdMmcAdma32bMode) {\r
1571 if (Remaining <= AdmaMaxDataPerLine) {\r
1572 Trb->Adma32Desc[Index].Valid = 1;\r
1573 Trb->Adma32Desc[Index].Act = 2;\r
1574 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r
1575 Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r
1576 }\r
1577 Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r
1578 Trb->Adma32Desc[Index].Address = (UINT32)Address;\r
1579 break;\r
1580 } else {\r
1581 Trb->Adma32Desc[Index].Valid = 1;\r
1582 Trb->Adma32Desc[Index].Act = 2;\r
1583 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r
1584 Trb->Adma32Desc[Index].UpperLength = 0;\r
1585 }\r
1586 Trb->Adma32Desc[Index].LowerLength = 0;\r
1587 Trb->Adma32Desc[Index].Address = (UINT32)Address;\r
1588 }\r
1589 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r
1590 if (Remaining <= AdmaMaxDataPerLine) {\r
1591 Trb->Adma64V3Desc[Index].Valid = 1;\r
1592 Trb->Adma64V3Desc[Index].Act = 2;\r
1593 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r
1594 Trb->Adma64V3Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r
1595 }\r
1596 Trb->Adma64V3Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r
1597 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;\r
1598 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r
1599 break;\r
1600 } else {\r
1601 Trb->Adma64V3Desc[Index].Valid = 1;\r
1602 Trb->Adma64V3Desc[Index].Act = 2;\r
1603 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r
1604 Trb->Adma64V3Desc[Index].UpperLength = 0;\r
1605 }\r
1606 Trb->Adma64V3Desc[Index].LowerLength = 0;\r
1607 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;\r
1608 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r
1609 }\r
1610 } else {\r
1611 if (Remaining <= AdmaMaxDataPerLine) {\r
1612 Trb->Adma64V4Desc[Index].Valid = 1;\r
1613 Trb->Adma64V4Desc[Index].Act = 2;\r
1614 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r
1615 Trb->Adma64V4Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r
1616 }\r
1617 Trb->Adma64V4Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r
1618 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;\r
1619 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r
1620 break;\r
1621 } else {\r
1622 Trb->Adma64V4Desc[Index].Valid = 1;\r
1623 Trb->Adma64V4Desc[Index].Act = 2;\r
1624 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r
1625 Trb->Adma64V4Desc[Index].UpperLength = 0;\r
1626 }\r
1627 Trb->Adma64V4Desc[Index].LowerLength = 0;\r
1628 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;\r
1629 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r
1630 }\r
1631 }\r
1632\r
1633 Remaining -= AdmaMaxDataPerLine;\r
1634 Address += AdmaMaxDataPerLine;\r
1635 }\r
1636\r
1637 //\r
1638 // Set the last descriptor line as end of descriptor table\r
1639 //\r
1640 if (Trb->Mode == SdMmcAdma32bMode) {\r
1641 Trb->Adma32Desc[Index].End = 1;\r
1642 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r
1643 Trb->Adma64V3Desc[Index].End = 1;\r
1644 } else {\r
1645 Trb->Adma64V4Desc[Index].End = 1;\r
1646 }\r
1647 return EFI_SUCCESS;\r
1648}\r
1649\r
1650/**\r
1651 Create a new TRB for the SD/MMC cmd request.\r
1652\r
1653 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
1654 @param[in] Slot The slot number of the SD card to send the command to.\r
1655 @param[in] Packet A pointer to the SD command data structure.\r
1656 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is\r
1657 not NULL, then nonblocking I/O is performed, and Event\r
1658 will be signaled when the Packet completes.\r
1659\r
1660 @return Created Trb or NULL.\r
1661\r
1662**/\r
1663SD_MMC_HC_TRB *\r
1664SdMmcCreateTrb (\r
1665 IN SD_MMC_HC_PRIVATE_DATA *Private,\r
1666 IN UINT8 Slot,\r
1667 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,\r
1668 IN EFI_EVENT Event\r
1669 )\r
1670{\r
1671 SD_MMC_HC_TRB *Trb;\r
1672 EFI_STATUS Status;\r
1673 EFI_TPL OldTpl;\r
1674 EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
1675 EFI_PCI_IO_PROTOCOL *PciIo;\r
1676 UINTN MapLength;\r
1677\r
1678 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));\r
1679 if (Trb == NULL) {\r
1680 return NULL;\r
1681 }\r
1682\r
1683 Trb->Signature = SD_MMC_HC_TRB_SIG;\r
1684 Trb->Slot = Slot;\r
1685 Trb->BlockSize = 0x200;\r
1686 Trb->Packet = Packet;\r
1687 Trb->Event = Event;\r
1688 Trb->Started = FALSE;\r
1689 Trb->Timeout = Packet->Timeout;\r
1690 Trb->Retries = SD_MMC_TRB_RETRIES;\r
1691 Trb->Private = Private;\r
1692\r
1693 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {\r
1694 Trb->Data = Packet->InDataBuffer;\r
1695 Trb->DataLen = Packet->InTransferLength;\r
1696 Trb->Read = TRUE;\r
1697 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {\r
1698 Trb->Data = Packet->OutDataBuffer;\r
1699 Trb->DataLen = Packet->OutTransferLength;\r
1700 Trb->Read = FALSE;\r
1701 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {\r
1702 Trb->Data = NULL;\r
1703 Trb->DataLen = 0;\r
1704 } else {\r
1705 goto Error;\r
1706 }\r
1707\r
1708 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {\r
1709 Trb->BlockSize = (UINT16)Trb->DataLen;\r
1710 }\r
1711\r
1712 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r
1713 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r
1714 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r
1715 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r
1716 Trb->Mode = SdMmcPioMode;\r
1717 } else {\r
1718 if (Trb->Read) {\r
1719 Flag = EfiPciIoOperationBusMasterWrite;\r
1720 } else {\r
1721 Flag = EfiPciIoOperationBusMasterRead;\r
1722 }\r
1723\r
1724 PciIo = Private->PciIo;\r
1725 if (Trb->DataLen != 0) {\r
1726 MapLength = Trb->DataLen;\r
1727 Status = PciIo->Map (\r
1728 PciIo,\r
1729 Flag,\r
1730 Trb->Data,\r
1731 &MapLength,\r
1732 &Trb->DataPhy,\r
1733 &Trb->DataMap\r
1734 );\r
1735 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {\r
1736 Status = EFI_BAD_BUFFER_SIZE;\r
1737 goto Error;\r
1738 }\r
1739 }\r
1740\r
1741 if (Trb->DataLen == 0) {\r
1742 Trb->Mode = SdMmcNoData;\r
1743 } else if (Private->Capability[Slot].Adma2 != 0) {\r
1744 Trb->Mode = SdMmcAdma32bMode;\r
1745 Trb->AdmaLengthMode = SdMmcAdmaLen16b;\r
1746 if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&\r
1747 (Private->Capability[Slot].SysBus64V3 == 1)) {\r
1748 Trb->Mode = SdMmcAdma64bV3Mode;\r
1749 } else if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&\r
1750 (Private->Capability[Slot].SysBus64V3 == 1)) ||\r
1751 ((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&\r
1752 (Private->Capability[Slot].SysBus64V4 == 1))) {\r
1753 Trb->Mode = SdMmcAdma64bV4Mode;\r
1754 }\r
1755 if (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) {\r
1756 Trb->AdmaLengthMode = SdMmcAdmaLen26b;\r
1757 }\r
1758 Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);\r
1759 if (EFI_ERROR (Status)) {\r
1760 goto Error;\r
1761 }\r
1762 } else if (Private->Capability[Slot].Sdma != 0) {\r
1763 Trb->Mode = SdMmcSdmaMode;\r
1764 } else {\r
1765 Trb->Mode = SdMmcPioMode;\r
1766 }\r
1767 }\r
1768\r
1769 if (Event != NULL) {\r
1770 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
1771 InsertTailList (&Private->Queue, &Trb->TrbList);\r
1772 gBS->RestoreTPL (OldTpl);\r
1773 }\r
1774\r
1775 return Trb;\r
1776\r
1777Error:\r
1778 SdMmcFreeTrb (Trb);\r
1779 return NULL;\r
1780}\r
1781\r
1782/**\r
1783 Free the resource used by the TRB.\r
1784\r
1785 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r
1786\r
1787**/\r
1788VOID\r
1789SdMmcFreeTrb (\r
1790 IN SD_MMC_HC_TRB *Trb\r
1791 )\r
1792{\r
1793 EFI_PCI_IO_PROTOCOL *PciIo;\r
1794\r
1795 PciIo = Trb->Private->PciIo;\r
1796\r
1797 if (Trb->AdmaMap != NULL) {\r
1798 PciIo->Unmap (\r
1799 PciIo,\r
1800 Trb->AdmaMap\r
1801 );\r
1802 }\r
1803 if (Trb->Adma32Desc != NULL) {\r
1804 PciIo->FreeBuffer (\r
1805 PciIo,\r
1806 Trb->AdmaPages,\r
1807 Trb->Adma32Desc\r
1808 );\r
1809 }\r
1810 if (Trb->Adma64V3Desc != NULL) {\r
1811 PciIo->FreeBuffer (\r
1812 PciIo,\r
1813 Trb->AdmaPages,\r
1814 Trb->Adma64V3Desc\r
1815 );\r
1816 }\r
1817 if (Trb->Adma64V4Desc != NULL) {\r
1818 PciIo->FreeBuffer (\r
1819 PciIo,\r
1820 Trb->AdmaPages,\r
1821 Trb->Adma64V4Desc\r
1822 );\r
1823 }\r
1824 if (Trb->DataMap != NULL) {\r
1825 PciIo->Unmap (\r
1826 PciIo,\r
1827 Trb->DataMap\r
1828 );\r
1829 }\r
1830 FreePool (Trb);\r
1831 return;\r
1832}\r
1833\r
1834/**\r
1835 Check if the env is ready for execute specified TRB.\r
1836\r
1837 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
1838 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r
1839\r
1840 @retval EFI_SUCCESS The env is ready for TRB execution.\r
1841 @retval EFI_NOT_READY The env is not ready for TRB execution.\r
1842 @retval Others Some erros happen.\r
1843\r
1844**/\r
1845EFI_STATUS\r
1846SdMmcCheckTrbEnv (\r
1847 IN SD_MMC_HC_PRIVATE_DATA *Private,\r
1848 IN SD_MMC_HC_TRB *Trb\r
1849 )\r
1850{\r
1851 EFI_STATUS Status;\r
1852 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r
1853 EFI_PCI_IO_PROTOCOL *PciIo;\r
1854 UINT32 PresentState;\r
1855\r
1856 Packet = Trb->Packet;\r
1857\r
1858 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||\r
1859 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||\r
1860 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {\r
1861 //\r
1862 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in\r
1863 // the Present State register to be 0\r
1864 //\r
1865 PresentState = BIT0 | BIT1;\r
1866 } else {\r
1867 //\r
1868 // Wait Command Inhibit (CMD) in the Present State register\r
1869 // to be 0\r
1870 //\r
1871 PresentState = BIT0;\r
1872 }\r
1873\r
1874 PciIo = Private->PciIo;\r
1875 Status = SdMmcHcCheckMmioSet (\r
1876 PciIo,\r
1877 Trb->Slot,\r
1878 SD_MMC_HC_PRESENT_STATE,\r
1879 sizeof (PresentState),\r
1880 PresentState,\r
1881 0\r
1882 );\r
1883\r
1884 return Status;\r
1885}\r
1886\r
1887/**\r
1888 Wait for the env to be ready for execute specified TRB.\r
1889\r
1890 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
1891 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r
1892\r
1893 @retval EFI_SUCCESS The env is ready for TRB execution.\r
1894 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.\r
1895 @retval Others Some erros happen.\r
1896\r
1897**/\r
1898EFI_STATUS\r
1899SdMmcWaitTrbEnv (\r
1900 IN SD_MMC_HC_PRIVATE_DATA *Private,\r
1901 IN SD_MMC_HC_TRB *Trb\r
1902 )\r
1903{\r
1904 EFI_STATUS Status;\r
1905 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r
1906 UINT64 Timeout;\r
1907 BOOLEAN InfiniteWait;\r
1908\r
1909 //\r
1910 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r
1911 //\r
1912 Packet = Trb->Packet;\r
1913 Timeout = Packet->Timeout;\r
1914 if (Timeout == 0) {\r
1915 InfiniteWait = TRUE;\r
1916 } else {\r
1917 InfiniteWait = FALSE;\r
1918 }\r
1919\r
1920 while (InfiniteWait || (Timeout > 0)) {\r
1921 //\r
1922 // Check Trb execution result by reading Normal Interrupt Status register.\r
1923 //\r
1924 Status = SdMmcCheckTrbEnv (Private, Trb);\r
1925 if (Status != EFI_NOT_READY) {\r
1926 return Status;\r
1927 }\r
1928 //\r
1929 // Stall for 1 microsecond.\r
1930 //\r
1931 gBS->Stall (1);\r
1932\r
1933 Timeout--;\r
1934 }\r
1935\r
1936 return EFI_TIMEOUT;\r
1937}\r
1938\r
1939/**\r
1940 Execute the specified TRB.\r
1941\r
1942 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
1943 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r
1944\r
1945 @retval EFI_SUCCESS The TRB is sent to host controller successfully.\r
1946 @retval Others Some erros happen when sending this request to the host controller.\r
1947\r
1948**/\r
1949EFI_STATUS\r
1950SdMmcExecTrb (\r
1951 IN SD_MMC_HC_PRIVATE_DATA *Private,\r
1952 IN SD_MMC_HC_TRB *Trb\r
1953 )\r
1954{\r
1955 EFI_STATUS Status;\r
1956 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r
1957 EFI_PCI_IO_PROTOCOL *PciIo;\r
1958 UINT16 Cmd;\r
1959 UINT16 IntStatus;\r
1960 UINT32 Argument;\r
1961 UINT32 BlkCount;\r
1962 UINT16 BlkSize;\r
1963 UINT16 TransMode;\r
1964 UINT8 HostCtrl1;\r
1965 UINT64 SdmaAddr;\r
1966 UINT64 AdmaAddr;\r
1967 BOOLEAN AddressingMode64;\r
1968\r
1969 AddressingMode64 = FALSE;\r
1970\r
1971 Packet = Trb->Packet;\r
1972 PciIo = Trb->Private->PciIo;\r
1973 //\r
1974 // Clear all bits in Error Interrupt Status Register\r
1975 //\r
1976 IntStatus = 0xFFFF;\r
1977 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
1978 if (EFI_ERROR (Status)) {\r
1979 return Status;\r
1980 }\r
1981 //\r
1982 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.\r
1983 //\r
1984 IntStatus = 0xFF3F;\r
1985 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
1986 if (EFI_ERROR (Status)) {\r
1987 return Status;\r
1988 }\r
1989\r
1990 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r
1991 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),\r
1992 SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_64_ADDR_EN);\r
1993 if (!EFI_ERROR (Status)) {\r
1994 AddressingMode64 = TRUE;\r
1995 }\r
1996 }\r
1997\r
1998 //\r
1999 // Set Host Control 1 register DMA Select field\r
2000 //\r
2001 if ((Trb->Mode == SdMmcAdma32bMode) ||\r
2002 (Trb->Mode == SdMmcAdma64bV4Mode)) {\r
2003 HostCtrl1 = BIT4;\r
2004 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
2005 if (EFI_ERROR (Status)) {\r
2006 return Status;\r
2007 }\r
2008 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r
2009 HostCtrl1 = BIT4|BIT3;\r
2010 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
2011 if (EFI_ERROR (Status)) {\r
2012 return Status;\r
2013 }\r
2014 }\r
2015\r
2016 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);\r
2017\r
2018 if (Trb->Mode == SdMmcSdmaMode) {\r
2019 if ((!AddressingMode64) &&\r
2020 ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {\r
2021 return EFI_INVALID_PARAMETER;\r
2022 }\r
2023\r
2024 SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;\r
2025\r
2026 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r
2027 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);\r
2028 } else {\r
2029 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);\r
2030 }\r
2031\r
2032 if (EFI_ERROR (Status)) {\r
2033 return Status;\r
2034 }\r
2035 } else if ((Trb->Mode == SdMmcAdma32bMode) ||\r
2036 (Trb->Mode == SdMmcAdma64bV3Mode) ||\r
2037 (Trb->Mode == SdMmcAdma64bV4Mode)) {\r
2038 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;\r
2039 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);\r
2040 if (EFI_ERROR (Status)) {\r
2041 return Status;\r
2042 }\r
2043 }\r
2044\r
2045 BlkSize = Trb->BlockSize;\r
2046 if (Trb->Mode == SdMmcSdmaMode) {\r
2047 //\r
2048 // Set SDMA boundary to be 512K bytes.\r
2049 //\r
2050 BlkSize |= 0x7000;\r
2051 }\r
2052\r
2053 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);\r
2054 if (EFI_ERROR (Status)) {\r
2055 return Status;\r
2056 }\r
2057\r
2058 BlkCount = 0;\r
2059 if (Trb->Mode != SdMmcNoData) {\r
2060 //\r
2061 // Calcuate Block Count.\r
2062 //\r
2063 BlkCount = (Trb->DataLen / Trb->BlockSize);\r
2064 }\r
2065 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {\r
2066 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);\r
2067 } else {\r
2068 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);\r
2069 }\r
2070 if (EFI_ERROR (Status)) {\r
2071 return Status;\r
2072 }\r
2073\r
2074 Argument = Packet->SdMmcCmdBlk->CommandArgument;\r
2075 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);\r
2076 if (EFI_ERROR (Status)) {\r
2077 return Status;\r
2078 }\r
2079\r
2080 TransMode = 0;\r
2081 if (Trb->Mode != SdMmcNoData) {\r
2082 if (Trb->Mode != SdMmcPioMode) {\r
2083 TransMode |= BIT0;\r
2084 }\r
2085 if (Trb->Read) {\r
2086 TransMode |= BIT4;\r
2087 }\r
2088 if (BlkCount > 1) {\r
2089 TransMode |= BIT5 | BIT1;\r
2090 }\r
2091 //\r
2092 // Only SD memory card needs to use AUTO CMD12 feature.\r
2093 //\r
2094 if (Private->Slot[Trb->Slot].CardType == SdCardType) {\r
2095 if (BlkCount > 1) {\r
2096 TransMode |= BIT2;\r
2097 }\r
2098 }\r
2099 }\r
2100\r
2101 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);\r
2102 if (EFI_ERROR (Status)) {\r
2103 return Status;\r
2104 }\r
2105\r
2106 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);\r
2107 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {\r
2108 Cmd |= BIT5;\r
2109 }\r
2110 //\r
2111 // Convert ResponseType to value\r
2112 //\r
2113 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r
2114 switch (Packet->SdMmcCmdBlk->ResponseType) {\r
2115 case SdMmcResponseTypeR1:\r
2116 case SdMmcResponseTypeR5:\r
2117 case SdMmcResponseTypeR6:\r
2118 case SdMmcResponseTypeR7:\r
2119 Cmd |= (BIT1 | BIT3 | BIT4);\r
2120 break;\r
2121 case SdMmcResponseTypeR2:\r
2122 Cmd |= (BIT0 | BIT3);\r
2123 break;\r
2124 case SdMmcResponseTypeR3:\r
2125 case SdMmcResponseTypeR4:\r
2126 Cmd |= BIT1;\r
2127 break;\r
2128 case SdMmcResponseTypeR1b:\r
2129 case SdMmcResponseTypeR5b:\r
2130 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);\r
2131 break;\r
2132 default:\r
2133 ASSERT (FALSE);\r
2134 break;\r
2135 }\r
2136 }\r
2137 //\r
2138 // Execute cmd\r
2139 //\r
2140 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);\r
2141 return Status;\r
2142}\r
2143\r
2144/**\r
2145 Performs SW reset based on passed error status mask.\r
2146\r
2147 @param[in] Private Pointer to driver private data.\r
2148 @param[in] Slot Index of the slot to reset.\r
2149 @param[in] ErrIntStatus Error interrupt status mask.\r
2150\r
2151 @retval EFI_SUCCESS Software reset performed successfully.\r
2152 @retval Other Software reset failed.\r
2153**/\r
2154EFI_STATUS\r
2155SdMmcSoftwareReset (\r
2156 IN SD_MMC_HC_PRIVATE_DATA *Private,\r
2157 IN UINT8 Slot,\r
2158 IN UINT16 ErrIntStatus\r
2159 )\r
2160{\r
2161 UINT8 SwReset;\r
2162 EFI_STATUS Status;\r
2163\r
2164 SwReset = 0;\r
2165 if ((ErrIntStatus & 0x0F) != 0) {\r
2166 SwReset |= BIT1;\r
2167 }\r
2168 if ((ErrIntStatus & 0x70) != 0) {\r
2169 SwReset |= BIT2;\r
2170 }\r
2171\r
2172 Status = SdMmcHcRwMmio (\r
2173 Private->PciIo,\r
2174 Slot,\r
2175 SD_MMC_HC_SW_RST,\r
2176 FALSE,\r
2177 sizeof (SwReset),\r
2178 &SwReset\r
2179 );\r
2180 if (EFI_ERROR (Status)) {\r
2181 return Status;\r
2182 }\r
2183\r
2184 Status = SdMmcHcWaitMmioSet (\r
2185 Private->PciIo,\r
2186 Slot,\r
2187 SD_MMC_HC_SW_RST,\r
2188 sizeof (SwReset),\r
2189 0xFF,\r
2190 0,\r
2191 SD_MMC_HC_GENERIC_TIMEOUT\r
2192 );\r
2193 if (EFI_ERROR (Status)) {\r
2194 return Status;\r
2195 }\r
2196\r
2197 return EFI_SUCCESS;\r
2198}\r
2199\r
2200/**\r
2201 Checks the error status in error status register\r
2202 and issues appropriate software reset as described in\r
2203 SD specification section 3.10.\r
2204\r
2205 @param[in] Private Pointer to driver private data.\r
2206 @param[in] Slot Index of the slot for device.\r
2207 @param[in] IntStatus Normal interrupt status mask.\r
2208\r
2209 @retval EFI_CRC_ERROR CRC error happened during CMD execution.\r
2210 @retval EFI_SUCCESS No error reported.\r
2211 @retval Others Some other error happened.\r
2212\r
2213**/\r
2214EFI_STATUS\r
2215SdMmcCheckAndRecoverErrors (\r
2216 IN SD_MMC_HC_PRIVATE_DATA *Private,\r
2217 IN UINT8 Slot,\r
2218 IN UINT16 IntStatus\r
2219 )\r
2220{\r
2221 UINT16 ErrIntStatus;\r
2222 EFI_STATUS Status;\r
2223 EFI_STATUS ErrorStatus;\r
2224\r
2225 if ((IntStatus & BIT15) == 0) {\r
2226 return EFI_SUCCESS;\r
2227 }\r
2228\r
2229 Status = SdMmcHcRwMmio (\r
2230 Private->PciIo,\r
2231 Slot,\r
2232 SD_MMC_HC_ERR_INT_STS,\r
2233 TRUE,\r
2234 sizeof (ErrIntStatus),\r
2235 &ErrIntStatus\r
2236 );\r
2237 if (EFI_ERROR (Status)) {\r
2238 return Status;\r
2239 }\r
2240\r
2241 //\r
2242 // If the data timeout error is reported\r
2243 // but data transfer is signaled as completed we\r
2244 // have to ignore data timeout. We also assume that no\r
2245 // other error is present on the link since data transfer\r
2246 // completed successfully. Error interrupt status\r
2247 // register is going to be reset when the next command\r
2248 // is started.\r
2249 //\r
2250 if (((ErrIntStatus & BIT4) != 0) && ((IntStatus & BIT1) != 0)) {\r
2251 return EFI_SUCCESS;\r
2252 }\r
2253\r
2254 //\r
2255 // We treat both CMD and DAT CRC errors and\r
2256 // end bits errors as EFI_CRC_ERROR. This will\r
2257 // let higher layer know that the error possibly\r
2258 // happened due to random bus condition and the\r
2259 // command can be retried.\r
2260 //\r
2261 if ((ErrIntStatus & (BIT1 | BIT2 | BIT5 | BIT6)) != 0) {\r
2262 ErrorStatus = EFI_CRC_ERROR;\r
2263 } else {\r
2264 ErrorStatus = EFI_DEVICE_ERROR;\r
2265 }\r
2266\r
2267 Status = SdMmcSoftwareReset (Private, Slot, ErrIntStatus);\r
2268 if (EFI_ERROR (Status)) {\r
2269 return Status;\r
2270 }\r
2271\r
2272 return ErrorStatus;\r
2273}\r
2274\r
2275/**\r
2276 Check the TRB execution result.\r
2277\r
2278 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
2279 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r
2280\r
2281 @retval EFI_SUCCESS The TRB is executed successfully.\r
2282 @retval EFI_NOT_READY The TRB is not completed for execution.\r
2283 @retval Others Some erros happen when executing this request.\r
2284\r
2285**/\r
2286EFI_STATUS\r
2287SdMmcCheckTrbResult (\r
2288 IN SD_MMC_HC_PRIVATE_DATA *Private,\r
2289 IN SD_MMC_HC_TRB *Trb\r
2290 )\r
2291{\r
2292 EFI_STATUS Status;\r
2293 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r
2294 UINT16 IntStatus;\r
2295 UINT32 Response[4];\r
2296 UINT64 SdmaAddr;\r
2297 UINT8 Index;\r
2298 UINT32 PioLength;\r
2299\r
2300 Packet = Trb->Packet;\r
2301 //\r
2302 // Check Trb execution result by reading Normal Interrupt Status register.\r
2303 //\r
2304 Status = SdMmcHcRwMmio (\r
2305 Private->PciIo,\r
2306 Trb->Slot,\r
2307 SD_MMC_HC_NOR_INT_STS,\r
2308 TRUE,\r
2309 sizeof (IntStatus),\r
2310 &IntStatus\r
2311 );\r
2312 if (EFI_ERROR (Status)) {\r
2313 goto Done;\r
2314 }\r
2315\r
2316 //\r
2317 // Check if there are any errors reported by host controller\r
2318 // and if neccessary recover the controller before next command is executed.\r
2319 //\r
2320 Status = SdMmcCheckAndRecoverErrors (Private, Trb->Slot, IntStatus);\r
2321 if (EFI_ERROR (Status)) {\r
2322 goto Done;\r
2323 }\r
2324\r
2325 //\r
2326 // Check Transfer Complete bit is set or not.\r
2327 //\r
2328 if ((IntStatus & BIT1) == BIT1) {\r
2329 goto Done;\r
2330 }\r
2331\r
2332 //\r
2333 // Check if DMA interrupt is signalled for the SDMA transfer.\r
2334 //\r
2335 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {\r
2336 //\r
2337 // Clear DMA interrupt bit.\r
2338 //\r
2339 IntStatus = BIT3;\r
2340 Status = SdMmcHcRwMmio (\r
2341 Private->PciIo,\r
2342 Trb->Slot,\r
2343 SD_MMC_HC_NOR_INT_STS,\r
2344 FALSE,\r
2345 sizeof (IntStatus),\r
2346 &IntStatus\r
2347 );\r
2348 if (EFI_ERROR (Status)) {\r
2349 goto Done;\r
2350 }\r
2351 //\r
2352 // Update SDMA Address register.\r
2353 //\r
2354 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);\r
2355\r
2356 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r
2357 Status = SdMmcHcRwMmio (\r
2358 Private->PciIo,\r
2359 Trb->Slot,\r
2360 SD_MMC_HC_ADMA_SYS_ADDR,\r
2361 FALSE,\r
2362 sizeof (UINT64),\r
2363 &SdmaAddr\r
2364 );\r
2365 } else {\r
2366 Status = SdMmcHcRwMmio (\r
2367 Private->PciIo,\r
2368 Trb->Slot,\r
2369 SD_MMC_HC_SDMA_ADDR,\r
2370 FALSE,\r
2371 sizeof (UINT32),\r
2372 &SdmaAddr\r
2373 );\r
2374 }\r
2375\r
2376 if (EFI_ERROR (Status)) {\r
2377 goto Done;\r
2378 }\r
2379 Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;\r
2380 }\r
2381\r
2382 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&\r
2383 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&\r
2384 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {\r
2385 if ((IntStatus & BIT0) == BIT0) {\r
2386 Status = EFI_SUCCESS;\r
2387 goto Done;\r
2388 }\r
2389 }\r
2390\r
2391 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r
2392 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r
2393 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r
2394 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r
2395 //\r
2396 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,\r
2397 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.\r
2398 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.\r
2399 //\r
2400 if ((IntStatus & BIT5) == BIT5) {\r
2401 //\r
2402 // Clear Buffer Read Ready interrupt at first.\r
2403 //\r
2404 IntStatus = BIT5;\r
2405 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
2406 //\r
2407 // Read data out from Buffer Port register\r
2408 //\r
2409 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {\r
2410 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);\r
2411 }\r
2412 Status = EFI_SUCCESS;\r
2413 goto Done;\r
2414 }\r
2415 }\r
2416\r
2417 Status = EFI_NOT_READY;\r
2418Done:\r
2419 //\r
2420 // Get response data when the cmd is executed successfully.\r
2421 //\r
2422 if (!EFI_ERROR (Status)) {\r
2423 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r
2424 for (Index = 0; Index < 4; Index++) {\r
2425 Status = SdMmcHcRwMmio (\r
2426 Private->PciIo,\r
2427 Trb->Slot,\r
2428 SD_MMC_HC_RESPONSE + Index * 4,\r
2429 TRUE,\r
2430 sizeof (UINT32),\r
2431 &Response[Index]\r
2432 );\r
2433 if (EFI_ERROR (Status)) {\r
2434 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r
2435 return Status;\r
2436 }\r
2437 }\r
2438 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));\r
2439 }\r
2440 }\r
2441\r
2442 if (Status != EFI_NOT_READY) {\r
2443 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r
2444 }\r
2445\r
2446 return Status;\r
2447}\r
2448\r
2449/**\r
2450 Wait for the TRB execution result.\r
2451\r
2452 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
2453 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r
2454\r
2455 @retval EFI_SUCCESS The TRB is executed successfully.\r
2456 @retval Others Some erros happen when executing this request.\r
2457\r
2458**/\r
2459EFI_STATUS\r
2460SdMmcWaitTrbResult (\r
2461 IN SD_MMC_HC_PRIVATE_DATA *Private,\r
2462 IN SD_MMC_HC_TRB *Trb\r
2463 )\r
2464{\r
2465 EFI_STATUS Status;\r
2466 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r
2467 UINT64 Timeout;\r
2468 BOOLEAN InfiniteWait;\r
2469\r
2470 Packet = Trb->Packet;\r
2471 //\r
2472 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r
2473 //\r
2474 Timeout = Packet->Timeout;\r
2475 if (Timeout == 0) {\r
2476 InfiniteWait = TRUE;\r
2477 } else {\r
2478 InfiniteWait = FALSE;\r
2479 }\r
2480\r
2481 while (InfiniteWait || (Timeout > 0)) {\r
2482 //\r
2483 // Check Trb execution result by reading Normal Interrupt Status register.\r
2484 //\r
2485 Status = SdMmcCheckTrbResult (Private, Trb);\r
2486 if (Status != EFI_NOT_READY) {\r
2487 return Status;\r
2488 }\r
2489 //\r
2490 // Stall for 1 microsecond.\r
2491 //\r
2492 gBS->Stall (1);\r
2493\r
2494 Timeout--;\r
2495 }\r
2496\r
2497 return EFI_TIMEOUT;\r
2498}\r
2499\r
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