[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / X64 / VirtualMemory.h

/** @file\r
  x64 Long Mode Virtual Memory Management Definitions\r
\r
  References:\r
    1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
    2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
    3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
    4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
\r
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _VIRTUAL_MEMORY_H_\r
#define _VIRTUAL_MEMORY_H_\r
\r
#define SYS_CODE64_SEL  0x38\r
\r
#pragma pack(1)\r
\r
typedef union {\r
  struct {\r
    UINT32    LimitLow    : 16;\r
    UINT32    BaseLow     : 16;\r
    UINT32    BaseMid     : 8;\r
    UINT32    Type        : 4;\r
    UINT32    System      : 1;\r
    UINT32    Dpl         : 2;\r
    UINT32    Present     : 1;\r
    UINT32    LimitHigh   : 4;\r
    UINT32    Software    : 1;\r
    UINT32    Reserved    : 1;\r
    UINT32    DefaultSize : 1;\r
    UINT32    Granularity : 1;\r
    UINT32    BaseHigh    : 8;\r
  } Bits;\r
  UINT64    Uint64;\r
} IA32_GDT;\r
\r
typedef struct {\r
  IA32_IDT_GATE_DESCRIPTOR    Ia32IdtEntry;\r
  UINT32                      Offset32To63;\r
  UINT32                      Reserved;\r
} X64_IDT_GATE_DESCRIPTOR;\r
\r
//\r
// Page-Map Level-4 Offset (PML4) and\r
// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
//\r
\r
typedef union {\r
  struct {\r
    UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory\r
    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
    UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64    Reserved             : 1;  // Reserved\r
    UINT64    MustBeZero           : 2;  // Must Be Zero\r
    UINT64    Available            : 3;  // Available for use by system software\r
    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
    UINT64    Nx                   : 1;  // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_MAP_AND_DIRECTORY_POINTER;\r
\r
//\r
// Page Table Entry 4KB\r
//\r
typedef union {\r
  struct {\r
    UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory\r
    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
    UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64    PAT                  : 1;  //\r
    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64    Available            : 3;  // Available for use by system software\r
    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
    UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_4K_ENTRY;\r
\r
//\r
// Page Table Entry 2MB\r
//\r
typedef union {\r
  struct {\r
    UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory\r
    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
    UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64    MustBe1              : 1;  // Must be 1\r
    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64    Available            : 3;  // Available for use by system software\r
    UINT64    PAT                  : 1;  //\r
    UINT64    MustBeZero           : 8;  // Must be zero;\r
    UINT64    PageTableBaseAddress : 31; // Page Table Base Address\r
    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
    UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_ENTRY;\r
\r
//\r
// Page Table Entry 1GB\r
//\r
typedef union {\r
  struct {\r
    UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory\r
    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
    UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64    MustBe1              : 1;  // Must be 1\r
    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64    Available            : 3;  // Available for use by system software\r
    UINT64    PAT                  : 1;  //\r
    UINT64    MustBeZero           : 17; // Must be zero;\r
    UINT64    PageTableBaseAddress : 22; // Page Table Base Address\r
    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
    UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_1G_ENTRY;\r
\r
#pragma pack()\r
\r
#define CR0_WP  BIT16\r
\r
#define IA32_PG_P   BIT0\r
#define IA32_PG_RW  BIT1\r
#define IA32_PG_PS  BIT7\r
\r
#define PAGING_PAE_INDEX_MASK  0x1FF\r
\r
#define PAGING_4K_ADDRESS_MASK_64  0x000FFFFFFFFFF000ull\r
#define PAGING_2M_ADDRESS_MASK_64  0x000FFFFFFFE00000ull\r
#define PAGING_1G_ADDRESS_MASK_64  0x000FFFFFC0000000ull\r
\r
#define PAGING_L1_ADDRESS_SHIFT  12\r
#define PAGING_L2_ADDRESS_SHIFT  21\r
#define PAGING_L3_ADDRESS_SHIFT  30\r
#define PAGING_L4_ADDRESS_SHIFT  39\r
\r
#define PAGING_PML4E_NUMBER  4\r
\r
#define PAGE_TABLE_POOL_ALIGNMENT   BASE_2MB\r
#define PAGE_TABLE_POOL_UNIT_SIZE   SIZE_2MB\r
#define PAGE_TABLE_POOL_UNIT_PAGES  EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
#define PAGE_TABLE_POOL_ALIGN_MASK  \\r
  (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
\r
typedef struct {\r
  VOID     *NextPool;\r
  UINTN    Offset;\r
  UINTN    FreePages;\r
} PAGE_TABLE_POOL;\r
\r
/**\r
  Check if Execute Disable Bit (IA32_EFER.NXE) should be enabled or not.\r
\r
  @retval TRUE    IA32_EFER.NXE should be enabled.\r
  @retval FALSE   IA32_EFER.NXE should not be enabled.\r
\r
**/\r
BOOLEAN\r
IsEnableNonExecNeeded (\r
  VOID\r
  );\r
\r
/**\r
  Enable Execute Disable Bit.\r
\r
**/\r
VOID\r
EnableExecuteDisableBit (\r
  VOID\r
  );\r
\r
/**\r
  Split 2M page to 4K.\r
\r
  @param[in]      PhysicalAddress       Start physical address the 2M page covered.\r
  @param[in, out] PageEntry2M           Pointer to 2M page entry.\r
  @param[in]      StackBase             Stack base address.\r
  @param[in]      StackSize             Stack size.\r
  @param[in]      GhcbBase              GHCB page area base address.\r
  @param[in]      GhcbSize              GHCB page area size.\r
\r
**/\r
VOID\r
Split2MPageTo4K (\r
  IN EFI_PHYSICAL_ADDRESS  PhysicalAddress,\r
  IN OUT UINT64            *PageEntry2M,\r
  IN EFI_PHYSICAL_ADDRESS  StackBase,\r
  IN UINTN                 StackSize,\r
  IN EFI_PHYSICAL_ADDRESS  GhcbBase,\r
  IN UINTN                 GhcbSize\r
  );\r
\r
/**\r
  Allocates and fills in the Page Directory and Page Table Entries to\r
  establish a 1:1 Virtual to Physical mapping.\r
\r
  @param[in] StackBase  Stack base address.\r
  @param[in] StackSize  Stack size.\r
  @param[in] GhcbBase   GHCB page area base address.\r
  @param[in] GhcbSize   GHCB page area size.\r
\r
  @return The address of 4 level page map.\r
\r
**/\r
UINTN\r
CreateIdentityMappingPageTables (\r
  IN EFI_PHYSICAL_ADDRESS  StackBase,\r
  IN UINTN                 StackSize,\r
  IN EFI_PHYSICAL_ADDRESS  GhcbBase,\r
  IN UINTN                 GhcbkSize\r
  );\r
\r
/**\r
\r
  Fix up the vector number in the vector code.\r
\r
  @param VectorBase   Base address of the vector handler.\r
  @param VectorNum    Index of vector.\r
\r
**/\r
VOID\r
EFIAPI\r
AsmVectorFixup (\r
  VOID   *VectorBase,\r
  UINT8  VectorNum\r
  );\r
\r
/**\r
\r
  Get the information of vector template.\r
\r
  @param TemplateBase   Base address of the template code.\r
\r
  @return               Size of the Template code.\r
\r
**/\r
UINTN\r
EFIAPI\r
AsmGetVectorTemplatInfo (\r
  OUT   VOID  **TemplateBase\r
  );\r
\r
/**\r
  Clear legacy memory located at the first 4K-page.\r
\r
  This function traverses the whole HOB list to check if memory from 0 to 4095\r
  exists and has not been allocated, and then clear it if so.\r
\r
  @param HobStart         The start of HobList passed to DxeCore.\r
\r
**/\r
VOID\r
ClearFirst4KPage (\r
  IN  VOID  *HobStart\r
  );\r
\r
/**\r
  Return configure status of NULL pointer detection feature.\r
\r
  @return TRUE   NULL pointer detection feature is enabled\r
  @return FALSE  NULL pointer detection feature is disabled\r
**/\r
BOOLEAN\r
IsNullDetectionEnabled (\r
  VOID\r
  );\r
\r
/**\r
  Prevent the memory pages used for page table from been overwritten.\r
\r
  @param[in] PageTableBase    Base address of page table (CR3).\r
  @param[in] Level4Paging     Level 4 paging flag.\r
\r
**/\r
VOID\r
EnablePageTableProtection (\r
  IN  UINTN    PageTableBase,\r
  IN  BOOLEAN  Level4Paging\r
  );\r
\r
/**\r
  This API provides a way to allocate memory for page table.\r
\r
  This API can be called more than once to allocate memory for page tables.\r
\r
  Allocates the number of 4KB pages and returns a pointer to the allocated\r
  buffer. The buffer returned is aligned on a 4KB boundary.\r
\r
  If Pages is 0, then NULL is returned.\r
  If there is not enough memory remaining to satisfy the request, then NULL is\r
  returned.\r
\r
  @param  Pages                 The number of 4 KB pages to allocate.\r
\r
  @return A pointer to the allocated buffer or NULL if allocation fails.\r
\r
**/\r
VOID *\r
AllocatePageTableMemory (\r
  IN UINTN  Pages\r
  );\r
\r
#endif\r
Commit	Line	Data
	1	/** @file\r
	2	x64 Long Mode Virtual Memory Management Definitions\r
	3	\r
	4	References:\r
	5	1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
	6	2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
	7	3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
	8	4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
	9	\r
	10	Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
	11	Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
	12	\r
	13	SPDX-License-Identifier: BSD-2-Clause-Patent\r
	14	\r
	15	**/\r
	16	\r
	17	#ifndef _VIRTUAL_MEMORY_H_\r
	18	#define _VIRTUAL_MEMORY_H_\r
	19	\r
	20	#define SYS_CODE64_SEL 0x38\r
	21	\r
	22	#pragma pack(1)\r
	23	\r
	24	typedef union {\r
	25	struct {\r
	26	UINT32 LimitLow : 16;\r
	27	UINT32 BaseLow : 16;\r
	28	UINT32 BaseMid : 8;\r
	29	UINT32 Type : 4;\r
	30	UINT32 System : 1;\r
	31	UINT32 Dpl : 2;\r
	32	UINT32 Present : 1;\r
	33	UINT32 LimitHigh : 4;\r
	34	UINT32 Software : 1;\r
	35	UINT32 Reserved : 1;\r
	36	UINT32 DefaultSize : 1;\r
	37	UINT32 Granularity : 1;\r
	38	UINT32 BaseHigh : 8;\r
	39	} Bits;\r
	40	UINT64 Uint64;\r
	41	} IA32_GDT;\r
	42	\r
	43	typedef struct {\r
	44	IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;\r
	45	UINT32 Offset32To63;\r
	46	UINT32 Reserved;\r
	47	} X64_IDT_GATE_DESCRIPTOR;\r
	48	\r
	49	//\r
	50	// Page-Map Level-4 Offset (PML4) and\r
	51	// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
	52	//\r
	53	\r
	54	typedef union {\r
	55	struct {\r
	56	UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory\r
	57	UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write\r
	58	UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User\r
	59	UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching\r
	60	UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached\r
	61	UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	62	UINT64 Reserved : 1; // Reserved\r
	63	UINT64 MustBeZero : 2; // Must Be Zero\r
	64	UINT64 Available : 3; // Available for use by system software\r
	65	UINT64 PageTableBaseAddress : 40; // Page Table Base Address\r
	66	UINT64 AvabilableHigh : 11; // Available for use by system software\r
	67	UINT64 Nx : 1; // No Execute bit\r
	68	} Bits;\r
	69	UINT64 Uint64;\r
	70	} PAGE_MAP_AND_DIRECTORY_POINTER;\r
	71	\r
	72	//\r
	73	// Page Table Entry 4KB\r
	74	//\r
	75	typedef union {\r
	76	struct {\r
	77	UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory\r
	78	UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write\r
	79	UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User\r
	80	UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching\r
	81	UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached\r
	82	UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	83	UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page\r
	84	UINT64 PAT : 1; //\r
	85	UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	86	UINT64 Available : 3; // Available for use by system software\r
	87	UINT64 PageTableBaseAddress : 40; // Page Table Base Address\r
	88	UINT64 AvabilableHigh : 11; // Available for use by system software\r
	89	UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution\r
	90	} Bits;\r
	91	UINT64 Uint64;\r
	92	} PAGE_TABLE_4K_ENTRY;\r
	93	\r
	94	//\r
	95	// Page Table Entry 2MB\r
	96	//\r
	97	typedef union {\r
	98	struct {\r
	99	UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory\r
	100	UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write\r
	101	UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User\r
	102	UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching\r
	103	UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached\r
	104	UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	105	UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page\r
	106	UINT64 MustBe1 : 1; // Must be 1\r
	107	UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	108	UINT64 Available : 3; // Available for use by system software\r
	109	UINT64 PAT : 1; //\r
	110	UINT64 MustBeZero : 8; // Must be zero;\r
	111	UINT64 PageTableBaseAddress : 31; // Page Table Base Address\r
	112	UINT64 AvabilableHigh : 11; // Available for use by system software\r
	113	UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution\r
	114	} Bits;\r
	115	UINT64 Uint64;\r
	116	} PAGE_TABLE_ENTRY;\r
	117	\r
	118	//\r
	119	// Page Table Entry 1GB\r
	120	//\r
	121	typedef union {\r
	122	struct {\r
	123	UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory\r
	124	UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write\r
	125	UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User\r
	126	UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching\r
	127	UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached\r
	128	UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	129	UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page\r
	130	UINT64 MustBe1 : 1; // Must be 1\r
	131	UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	132	UINT64 Available : 3; // Available for use by system software\r
	133	UINT64 PAT : 1; //\r
	134	UINT64 MustBeZero : 17; // Must be zero;\r
	135	UINT64 PageTableBaseAddress : 22; // Page Table Base Address\r
	136	UINT64 AvabilableHigh : 11; // Available for use by system software\r
	137	UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution\r
	138	} Bits;\r
	139	UINT64 Uint64;\r
	140	} PAGE_TABLE_1G_ENTRY;\r
	141	\r
	142	#pragma pack()\r
	143	\r
	144	#define CR0_WP BIT16\r
	145	\r
	146	#define IA32_PG_P BIT0\r
	147	#define IA32_PG_RW BIT1\r
	148	#define IA32_PG_PS BIT7\r
	149	\r
	150	#define PAGING_PAE_INDEX_MASK 0x1FF\r
	151	\r
	152	#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
	153	#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
	154	#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
	155	\r
	156	#define PAGING_L1_ADDRESS_SHIFT 12\r
	157	#define PAGING_L2_ADDRESS_SHIFT 21\r
	158	#define PAGING_L3_ADDRESS_SHIFT 30\r
	159	#define PAGING_L4_ADDRESS_SHIFT 39\r
	160	\r
	161	#define PAGING_PML4E_NUMBER 4\r
	162	\r
	163	#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB\r
	164	#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB\r
	165	#define PAGE_TABLE_POOL_UNIT_PAGES EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
	166	#define PAGE_TABLE_POOL_ALIGN_MASK \\r
	167	(~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
	168	\r
	169	typedef struct {\r
	170	VOID *NextPool;\r
	171	UINTN Offset;\r
	172	UINTN FreePages;\r
	173	} PAGE_TABLE_POOL;\r
	174	\r
	175	/**\r
	176	Check if Execute Disable Bit (IA32_EFER.NXE) should be enabled or not.\r
	177	\r
	178	@retval TRUE IA32_EFER.NXE should be enabled.\r
	179	@retval FALSE IA32_EFER.NXE should not be enabled.\r
	180	\r
	181	**/\r
	182	BOOLEAN\r
	183	IsEnableNonExecNeeded (\r
	184	VOID\r
	185	);\r
	186	\r
	187	/**\r
	188	Enable Execute Disable Bit.\r
	189	\r
	190	**/\r
	191	VOID\r
	192	EnableExecuteDisableBit (\r
	193	VOID\r
	194	);\r
	195	\r
	196	/**\r
	197	Split 2M page to 4K.\r
	198	\r
	199	@param[in] PhysicalAddress Start physical address the 2M page covered.\r
	200	@param[in, out] PageEntry2M Pointer to 2M page entry.\r
	201	@param[in] StackBase Stack base address.\r
	202	@param[in] StackSize Stack size.\r
	203	@param[in] GhcbBase GHCB page area base address.\r
	204	@param[in] GhcbSize GHCB page area size.\r
	205	\r
	206	**/\r
	207	VOID\r
	208	Split2MPageTo4K (\r
	209	IN EFI_PHYSICAL_ADDRESS PhysicalAddress,\r
	210	IN OUT UINT64 *PageEntry2M,\r
	211	IN EFI_PHYSICAL_ADDRESS StackBase,\r
	212	IN UINTN StackSize,\r
	213	IN EFI_PHYSICAL_ADDRESS GhcbBase,\r
	214	IN UINTN GhcbSize\r
	215	);\r
	216	\r
	217	/**\r
	218	Allocates and fills in the Page Directory and Page Table Entries to\r
	219	establish a 1:1 Virtual to Physical mapping.\r
	220	\r
	221	@param[in] StackBase Stack base address.\r
	222	@param[in] StackSize Stack size.\r
	223	@param[in] GhcbBase GHCB page area base address.\r
	224	@param[in] GhcbSize GHCB page area size.\r
	225	\r
	226	@return The address of 4 level page map.\r
	227	\r
	228	**/\r
	229	UINTN\r
	230	CreateIdentityMappingPageTables (\r
	231	IN EFI_PHYSICAL_ADDRESS StackBase,\r
	232	IN UINTN StackSize,\r
	233	IN EFI_PHYSICAL_ADDRESS GhcbBase,\r
	234	IN UINTN GhcbkSize\r
	235	);\r
	236	\r
	237	/**\r
	238	\r
	239	Fix up the vector number in the vector code.\r
	240	\r
	241	@param VectorBase Base address of the vector handler.\r
	242	@param VectorNum Index of vector.\r
	243	\r
	244	**/\r
	245	VOID\r
	246	EFIAPI\r
	247	AsmVectorFixup (\r
	248	VOID *VectorBase,\r
	249	UINT8 VectorNum\r
	250	);\r
	251	\r
	252	/**\r
	253	\r
	254	Get the information of vector template.\r
	255	\r
	256	@param TemplateBase Base address of the template code.\r
	257	\r
	258	@return Size of the Template code.\r
	259	\r
	260	**/\r
	261	UINTN\r
	262	EFIAPI\r
	263	AsmGetVectorTemplatInfo (\r
	264	OUT VOID **TemplateBase\r
	265	);\r
	266	\r
	267	/**\r
	268	Clear legacy memory located at the first 4K-page.\r
	269	\r
	270	This function traverses the whole HOB list to check if memory from 0 to 4095\r
	271	exists and has not been allocated, and then clear it if so.\r
	272	\r
	273	@param HobStart The start of HobList passed to DxeCore.\r
	274	\r
	275	**/\r
	276	VOID\r
	277	ClearFirst4KPage (\r
	278	IN VOID *HobStart\r
	279	);\r
	280	\r
	281	/**\r
	282	Return configure status of NULL pointer detection feature.\r
	283	\r
	284	@return TRUE NULL pointer detection feature is enabled\r
	285	@return FALSE NULL pointer detection feature is disabled\r
	286	**/\r
	287	BOOLEAN\r
	288	IsNullDetectionEnabled (\r
	289	VOID\r
	290	);\r
	291	\r
	292	/**\r
	293	Prevent the memory pages used for page table from been overwritten.\r
	294	\r
	295	@param[in] PageTableBase Base address of page table (CR3).\r
	296	@param[in] Level4Paging Level 4 paging flag.\r
	297	\r
	298	**/\r
	299	VOID\r
	300	EnablePageTableProtection (\r
	301	IN UINTN PageTableBase,\r
	302	IN BOOLEAN Level4Paging\r
	303	);\r
	304	\r
	305	/**\r
	306	This API provides a way to allocate memory for page table.\r
	307	\r
	308	This API can be called more than once to allocate memory for page tables.\r
	309	\r
	310	Allocates the number of 4KB pages and returns a pointer to the allocated\r
	311	buffer. The buffer returned is aligned on a 4KB boundary.\r
	312	\r
	313	If Pages is 0, then NULL is returned.\r
	314	If there is not enough memory remaining to satisfy the request, then NULL is\r
	315	returned.\r
	316	\r
	317	@param Pages The number of 4 KB pages to allocate.\r
	318	\r
	319	@return A pointer to the allocated buffer or NULL if allocation fails.\r
	320	\r
	321	**/\r
	322	VOID *\r
	323	AllocatePageTableMemory (\r
	324	IN UINTN Pages\r
	325	);\r
	326	\r
	327	#endif\r