[mirror_edk2.git] / MdeModulePkg / Universal / CapsulePei / Capsule.h

/** @file\r
\r
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _CAPSULE_PEIM_H_\r
#define _CAPSULE_PEIM_H_\r
\r
#include <PiPei.h>\r
#include <Uefi/UefiSpec.h>\r
\r
#include <Ppi/Capsule.h>\r
#include <Ppi/LoadFile.h>\r
#include <Ppi/ReadOnlyVariable2.h>\r
#include <Guid/CapsuleVendor.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/PeiServicesTablePointerLib.h>\r
#include <Library/PrintLib.h>\r
#include <Library/PeCoffLib.h>\r
#include <Library/PeCoffGetEntryPointLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/DebugAgentLib.h>\r
#include <IndustryStandard/PeImage.h>\r
#include "Common/CommonHeader.h"\r
\r
#ifdef MDE_CPU_IA32\r
\r
#pragma pack(1)\r
\r
//\r
// Page-Map Level-4 Offset (PML4) and\r
// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
//\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Reserved:1;               // Reserved\r
    UINT64  MustBeZero:2;             // Must Be Zero\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_MAP_AND_DIRECTORY_POINTER;\r
\r
//\r
// Page Table Entry 2MB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:8;             // Must be zero;\r
    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_ENTRY;\r
\r
//\r
// Page Table Entry 1GB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:17;            // Must be zero;\r
    UINT64  PageTableBaseAddress:22;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_1G_ENTRY;\r
\r
#pragma pack()\r
\r
typedef\r
EFI_STATUS\r
(*COALESCE_ENTRY) (\r
  SWITCH_32_TO_64_CONTEXT       *EntrypointContext,\r
  SWITCH_64_TO_32_CONTEXT       *ReturnContext\r
  );\r
\r
#endif\r
\r
#endif\r
Commit	Line	Data
	1	/** @file\r
	2	\r
	3	Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
	4	\r
	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
	6	\r
	7	**/\r
	8	\r
	9	#ifndef _CAPSULE_PEIM_H_\r
	10	#define _CAPSULE_PEIM_H_\r
	11	\r
	12	#include <PiPei.h>\r
	13	#include <Uefi/UefiSpec.h>\r
	14	\r
	15	#include <Ppi/Capsule.h>\r
	16	#include <Ppi/LoadFile.h>\r
	17	#include <Ppi/ReadOnlyVariable2.h>\r
	18	#include <Guid/CapsuleVendor.h>\r
	19	\r
	20	#include <Library/BaseLib.h>\r
	21	#include <Library/DebugLib.h>\r
	22	#include <Library/PeimEntryPoint.h>\r
	23	#include <Library/PeiServicesLib.h>\r
	24	#include <Library/BaseMemoryLib.h>\r
	25	#include <Library/HobLib.h>\r
	26	#include <Library/PeiServicesTablePointerLib.h>\r
	27	#include <Library/PrintLib.h>\r
	28	#include <Library/PeCoffLib.h>\r
	29	#include <Library/PeCoffGetEntryPointLib.h>\r
	30	#include <Library/PcdLib.h>\r
	31	#include <Library/ReportStatusCodeLib.h>\r
	32	#include <Library/DebugAgentLib.h>\r
	33	#include <IndustryStandard/PeImage.h>\r
	34	#include "Common/CommonHeader.h"\r
	35	\r
	36	#ifdef MDE_CPU_IA32\r
	37	\r
	38	#pragma pack(1)\r
	39	\r
	40	//\r
	41	// Page-Map Level-4 Offset (PML4) and\r
	42	// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
	43	//\r
	44	\r
	45	typedef union {\r
	46	struct {\r
	47	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	48	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	49	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	50	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	51	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	52	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	53	UINT64 Reserved:1; // Reserved\r
	54	UINT64 MustBeZero:2; // Must Be Zero\r
	55	UINT64 Available:3; // Available for use by system software\r
	56	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
	57	UINT64 AvabilableHigh:11; // Available for use by system software\r
	58	UINT64 Nx:1; // No Execute bit\r
	59	} Bits;\r
	60	UINT64 Uint64;\r
	61	} PAGE_MAP_AND_DIRECTORY_POINTER;\r
	62	\r
	63	//\r
	64	// Page Table Entry 2MB\r
	65	//\r
	66	typedef union {\r
	67	struct {\r
	68	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	69	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	70	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	71	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	72	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	73	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	74	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
	75	UINT64 MustBe1:1; // Must be 1\r
	76	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	77	UINT64 Available:3; // Available for use by system software\r
	78	UINT64 PAT:1; //\r
	79	UINT64 MustBeZero:8; // Must be zero;\r
	80	UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
	81	UINT64 AvabilableHigh:11; // Available for use by system software\r
	82	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
	83	} Bits;\r
	84	UINT64 Uint64;\r
	85	} PAGE_TABLE_ENTRY;\r
	86	\r
	87	//\r
	88	// Page Table Entry 1GB\r
	89	//\r
	90	typedef union {\r
	91	struct {\r
	92	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	93	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	94	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	95	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	96	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	97	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	98	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
	99	UINT64 MustBe1:1; // Must be 1\r
	100	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	101	UINT64 Available:3; // Available for use by system software\r
	102	UINT64 PAT:1; //\r
	103	UINT64 MustBeZero:17; // Must be zero;\r
	104	UINT64 PageTableBaseAddress:22; // Page Table Base Address\r
	105	UINT64 AvabilableHigh:11; // Available for use by system software\r
	106	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
	107	} Bits;\r
	108	UINT64 Uint64;\r
	109	} PAGE_TABLE_1G_ENTRY;\r
	110	\r
	111	#pragma pack()\r
	112	\r
	113	typedef\r
	114	EFI_STATUS\r
	115	(*COALESCE_ENTRY) (\r
	116	SWITCH_32_TO_64_CONTEXT *EntrypointContext,\r
	117	SWITCH_64_TO_32_CONTEXT *ReturnContext\r
	118	);\r
	119	\r
	120	#endif\r
	121	\r
	122	#endif\r