[mirror_edk2.git] / MdeModulePkg / Universal / CapsulePei / Capsule.h

/** @file\r
\r
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
of the BSD License which accompanies this distribution.  The\r
full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _CAPSULE_PEIM_H_\r
#define _CAPSULE_PEIM_H_\r
\r
#include <PiPei.h>\r
#include <Uefi/UefiSpec.h>\r
\r
#include <Ppi/Capsule.h>\r
#include <Ppi/LoadFile.h>\r
#include <Ppi/ReadOnlyVariable2.h>\r
#include <Guid/CapsuleVendor.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/PeiServicesTablePointerLib.h>\r
#include <Library/PrintLib.h>\r
#include <Library/PeCoffLib.h>\r
#include <Library/PeCoffGetEntryPointLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/DebugAgentLib.h>\r
#include <IndustryStandard/PeImage.h>\r
#include "Common/CommonHeader.h"\r
\r
#ifdef MDE_CPU_IA32\r
\r
#pragma pack(1)\r
\r
//\r
// Page-Map Level-4 Offset (PML4) and\r
// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
//\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Reserved:1;               // Reserved\r
    UINT64  MustBeZero:2;             // Must Be Zero\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_MAP_AND_DIRECTORY_POINTER;\r
\r
//\r
// Page Table Entry 2MB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:8;             // Must be zero;\r
    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_ENTRY;\r
\r
//\r
// Page Table Entry 1GB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:17;            // Must be zero;\r
    UINT64  PageTableBaseAddress:22;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_1G_ENTRY;\r
\r
#pragma pack()\r
\r
typedef\r
EFI_STATUS\r
(*COALESCE_ENTRY) (\r
  SWITCH_32_TO_64_CONTEXT       *EntrypointContext,\r
  SWITCH_64_TO_32_CONTEXT       *ReturnContext\r
  );\r
\r
#endif\r
\r
#endif\r
Commit	Line	Data
	1	/** @file\r
	2	\r
	3	Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
	4	\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions\r
	7	of the BSD License which accompanies this distribution. The\r
	8	full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef _CAPSULE_PEIM_H_\r
	17	#define _CAPSULE_PEIM_H_\r
	18	\r
	19	#include <PiPei.h>\r
	20	#include <Uefi/UefiSpec.h>\r
	21	\r
	22	#include <Ppi/Capsule.h>\r
	23	#include <Ppi/LoadFile.h>\r
	24	#include <Ppi/ReadOnlyVariable2.h>\r
	25	#include <Guid/CapsuleVendor.h>\r
	26	\r
	27	#include <Library/BaseLib.h>\r
	28	#include <Library/DebugLib.h>\r
	29	#include <Library/PeimEntryPoint.h>\r
	30	#include <Library/PeiServicesLib.h>\r
	31	#include <Library/BaseMemoryLib.h>\r
	32	#include <Library/HobLib.h>\r
	33	#include <Library/PeiServicesTablePointerLib.h>\r
	34	#include <Library/PrintLib.h>\r
	35	#include <Library/PeCoffLib.h>\r
	36	#include <Library/PeCoffGetEntryPointLib.h>\r
	37	#include <Library/PcdLib.h>\r
	38	#include <Library/ReportStatusCodeLib.h>\r
	39	#include <Library/DebugAgentLib.h>\r
	40	#include <IndustryStandard/PeImage.h>\r
	41	#include "Common/CommonHeader.h"\r
	42	\r
	43	#ifdef MDE_CPU_IA32\r
	44	\r
	45	#pragma pack(1)\r
	46	\r
	47	//\r
	48	// Page-Map Level-4 Offset (PML4) and\r
	49	// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
	50	//\r
	51	\r
	52	typedef union {\r
	53	struct {\r
	54	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	55	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	56	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	57	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	58	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	59	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	60	UINT64 Reserved:1; // Reserved\r
	61	UINT64 MustBeZero:2; // Must Be Zero\r
	62	UINT64 Available:3; // Available for use by system software\r
	63	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
	64	UINT64 AvabilableHigh:11; // Available for use by system software\r
	65	UINT64 Nx:1; // No Execute bit\r
	66	} Bits;\r
	67	UINT64 Uint64;\r
	68	} PAGE_MAP_AND_DIRECTORY_POINTER;\r
	69	\r
	70	//\r
	71	// Page Table Entry 2MB\r
	72	//\r
	73	typedef union {\r
	74	struct {\r
	75	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	76	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	77	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	78	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	79	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	80	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	81	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
	82	UINT64 MustBe1:1; // Must be 1\r
	83	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	84	UINT64 Available:3; // Available for use by system software\r
	85	UINT64 PAT:1; //\r
	86	UINT64 MustBeZero:8; // Must be zero;\r
	87	UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
	88	UINT64 AvabilableHigh:11; // Available for use by system software\r
	89	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
	90	} Bits;\r
	91	UINT64 Uint64;\r
	92	} PAGE_TABLE_ENTRY;\r
	93	\r
	94	//\r
	95	// Page Table Entry 1GB\r
	96	//\r
	97	typedef union {\r
	98	struct {\r
	99	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	100	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	101	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	102	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	103	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	104	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	105	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
	106	UINT64 MustBe1:1; // Must be 1\r
	107	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	108	UINT64 Available:3; // Available for use by system software\r
	109	UINT64 PAT:1; //\r
	110	UINT64 MustBeZero:17; // Must be zero;\r
	111	UINT64 PageTableBaseAddress:22; // Page Table Base Address\r
	112	UINT64 AvabilableHigh:11; // Available for use by system software\r
	113	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
	114	} Bits;\r
	115	UINT64 Uint64;\r
	116	} PAGE_TABLE_1G_ENTRY;\r
	117	\r
	118	#pragma pack()\r
	119	\r
	120	typedef\r
	121	EFI_STATUS\r
	122	(*COALESCE_ENTRY) (\r
	123	SWITCH_32_TO_64_CONTEXT *EntrypointContext,\r
	124	SWITCH_64_TO_32_CONTEXT *ReturnContext\r
	125	);\r
	126	\r
	127	#endif\r
	128	\r
	129	#endif\r