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1 | /** @file\r | |
2 | ACPI Low Power Idle Table (LPIT) definitions\r | |
3 | \r | |
4 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | \r | |
7 | @par Revision Reference:\r | |
8 | - ACPI Low Power Idle Table (LPIT) Revision 001, dated July 2014\r | |
9 | http://www.uefi.org/sites/default/files/resources/ACPI_Low_Power_Idle_Table.pdf\r | |
10 | \r | |
11 | @par Glossary:\r | |
12 | - GAS - Generic Address Structure\r | |
13 | - LPI - Low Power Idle\r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _LOW_POWER_IDLE_TABLE_H_\r | |
17 | #define _LOW_POWER_IDLE_TABLE_H_\r | |
18 | \r | |
19 | #include <IndustryStandard/Acpi.h>\r | |
20 | \r | |
21 | #pragma pack(1)\r | |
22 | \r | |
23 | ///\r | |
24 | /// LPI Structure Types\r | |
25 | ///\r | |
26 | #define ACPI_LPI_STRUCTURE_TYPE_NATIVE_CSTATE 0x00\r | |
27 | \r | |
28 | ///\r | |
29 | /// Low Power Idle (LPI) State Flags\r | |
30 | ///\r | |
31 | typedef union {\r | |
32 | struct {\r | |
33 | UINT32 Disabled : 1; ///< If set, LPI state is not used\r | |
34 | \r | |
35 | /**\r | |
36 | If set, Residency counter is not available for this LPI state and\r | |
37 | Residency Counter Frequency is invalid\r | |
38 | **/\r | |
39 | UINT32 CounterUnavailable : 1;\r | |
40 | UINT32 Reserved : 30; ///< Reserved for future use. Must be zero\r | |
41 | } Bits;\r | |
42 | UINT32 Data32;\r | |
43 | } ACPI_LPI_STATE_FLAGS;\r | |
44 | \r | |
45 | ///\r | |
46 | /// Low Power Idle (LPI) structure with Native C-state instruction entry trigger descriptor\r | |
47 | ///\r | |
48 | typedef struct {\r | |
49 | UINT32 Type; ///< LPI State descriptor Type 0\r | |
50 | UINT32 Length; ///< Length of LPI state Descriptor Structure\r | |
51 | ///\r | |
52 | /// Unique LPI state identifier: zero based, monotonically increasing identifier\r | |
53 | ///\r | |
54 | UINT16 UniqueId;\r | |
55 | UINT8 Reserved[2]; ///< Must be Zero\r | |
56 | ACPI_LPI_STATE_FLAGS Flags; ///< LPI state flags\r | |
57 | \r | |
58 | /**\r | |
59 | The LPI entry trigger, matching an existing _CST.Register object, represented as a\r | |
60 | Generic Address Structure. All processors must request this state or deeper to trigger.\r | |
61 | **/\r | |
62 | EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EntryTrigger;\r | |
63 | UINT32 Residency; ///< Minimum residency or break-even in uSec\r | |
64 | UINT32 Latency; ///< Worst case exit latency in uSec\r | |
65 | \r | |
66 | /**\r | |
67 | [optional] Residency counter, represented as a Generic Address Structure.\r | |
68 | If not present, Flags[1] bit should be set.\r | |
69 | **/\r | |
70 | EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResidencyCounter;\r | |
71 | \r | |
72 | /**\r | |
73 | [optional] Residency counter frequency in cycles per second. Value 0 indicates that\r | |
74 | counter runs at TSC frequency. Valid only if Residency Counter is present.\r | |
75 | **/\r | |
76 | UINT64 ResidencyCounterFrequency;\r | |
77 | } ACPI_LPI_NATIVE_CSTATE_DESCRIPTOR;\r | |
78 | \r | |
79 | #pragma pack()\r | |
80 | \r | |
81 | #endif\r |