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1/** @file\r
2 Definitions based on NVMe spec. version 1.1.\r
3\r
4 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r
5 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
6 SPDX-License-Identifier: BSD-2-Clause-Patent\r
7\r
8 @par Specification Reference:\r
9 NVMe Specification 1.1\r
10\r
11**/\r
12\r
13#ifndef __NVM_E_H__\r
14#define __NVM_E_H__\r
15\r
16#pragma pack(1)\r
17\r
18//\r
19// controller register offsets\r
20//\r
21#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r
22#define NVME_VER_OFFSET 0x0008 // Version\r
23#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r
24#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r
25#define NVME_CC_OFFSET 0x0014 // Controller Configuration\r
26#define NVME_CSTS_OFFSET 0x001c // Controller Status\r
27#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset\r
28#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r
29#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r
30#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r
31#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r
32#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r
33\r
34//\r
35// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))\r
36// Get the doorbell stride bit shift value from the controller capabilities.\r
37//\r
38#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell\r
39#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell\r
40\r
41\r
42#pragma pack(1)\r
43\r
44//\r
45// 3.1.1 Offset 00h: CAP - Controller Capabilities\r
46//\r
47typedef struct {\r
48 UINT16 Mqes; // Maximum Queue Entries Supported\r
49 UINT8 Cqr:1; // Contiguous Queues Required\r
50 UINT8 Ams:2; // Arbitration Mechanism Supported\r
51 UINT8 Rsvd1:5;\r
52 UINT8 To; // Timeout\r
53 UINT16 Dstrd:4;\r
54 UINT16 Nssrs:1; // NVM Subsystem Reset Supported NSSRS\r
55 UINT16 Css:4; // Command Sets Supported - Bit 37\r
56 UINT16 Rsvd3:7;\r
57 UINT8 Mpsmin:4;\r
58 UINT8 Mpsmax:4;\r
59 UINT8 Rsvd4;\r
60} NVME_CAP;\r
61\r
62//\r
63// 3.1.2 Offset 08h: VS - Version\r
64//\r
65typedef struct {\r
66 UINT16 Mnr; // Minor version number\r
67 UINT16 Mjr; // Major version number\r
68} NVME_VER;\r
69\r
70//\r
71// 3.1.5 Offset 14h: CC - Controller Configuration\r
72//\r
73typedef struct {\r
74 UINT16 En:1; // Enable\r
75 UINT16 Rsvd1:3;\r
76 UINT16 Css:3; // I/O Command Set Selected\r
77 UINT16 Mps:4; // Memory Page Size\r
78 UINT16 Ams:3; // Arbitration Mechanism Selected\r
79 UINT16 Shn:2; // Shutdown Notification\r
80 UINT8 Iosqes:4; // I/O Submission Queue Entry Size\r
81 UINT8 Iocqes:4; // I/O Completion Queue Entry Size\r
82 UINT8 Rsvd2;\r
83} NVME_CC;\r
84#define NVME_CC_SHN_NORMAL_SHUTDOWN 1\r
85#define NVME_CC_SHN_ABRUPT_SHUTDOWN 2\r
86\r
87//\r
88// 3.1.6 Offset 1Ch: CSTS - Controller Status\r
89//\r
90typedef struct {\r
91 UINT32 Rdy:1; // Ready\r
92 UINT32 Cfs:1; // Controller Fatal Status\r
93 UINT32 Shst:2; // Shutdown Status\r
94 UINT32 Nssro:1; // NVM Subsystem Reset Occurred\r
95 UINT32 Rsvd1:27;\r
96} NVME_CSTS;\r
97#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1\r
98#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2\r
99//\r
100// 3.1.8 Offset 24h: AQA - Admin Queue Attributes\r
101//\r
102typedef struct {\r
103 UINT16 Asqs:12; // Submission Queue Size\r
104 UINT16 Rsvd1:4;\r
105 UINT16 Acqs:12; // Completion Queue Size\r
106 UINT16 Rsvd2:4;\r
107} NVME_AQA;\r
108\r
109//\r
110// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r
111//\r
112#define NVME_ASQ UINT64\r
113//\r
114// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r
115//\r
116#define NVME_ACQ UINT64\r
117\r
118//\r
119// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
120//\r
121typedef struct {\r
122 UINT16 Sqt;\r
123 UINT16 Rsvd1;\r
124} NVME_SQTDBL;\r
125\r
126//\r
127// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell\r
128//\r
129typedef struct {\r
130 UINT16 Cqh;\r
131 UINT16 Rsvd1;\r
132} NVME_CQHDBL;\r
133\r
134//\r
135// NVM command set structures\r
136//\r
137// Read Command\r
138//\r
139typedef struct {\r
140 //\r
141 // CDW 10, 11\r
142 //\r
143 UINT64 Slba; /* Starting Sector Address */\r
144 //\r
145 // CDW 12\r
146 //\r
147 UINT16 Nlb; /* Number of Sectors */\r
148 UINT16 Rsvd1:10;\r
149 UINT16 Prinfo:4; /* Protection Info Check */\r
150 UINT16 Fua:1; /* Force Unit Access */\r
151 UINT16 Lr:1; /* Limited Retry */\r
152 //\r
153 // CDW 13\r
154 //\r
155 UINT32 Af:4; /* Access Frequency */\r
156 UINT32 Al:2; /* Access Latency */\r
157 UINT32 Sr:1; /* Sequential Request */\r
158 UINT32 In:1; /* Incompressible */\r
159 UINT32 Rsvd2:24;\r
160 //\r
161 // CDW 14\r
162 //\r
163 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
164 //\r
165 // CDW 15\r
166 //\r
167 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
168 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
169} NVME_READ;\r
170\r
171//\r
172// Write Command\r
173//\r
174typedef struct {\r
175 //\r
176 // CDW 10, 11\r
177 //\r
178 UINT64 Slba; /* Starting Sector Address */\r
179 //\r
180 // CDW 12\r
181 //\r
182 UINT16 Nlb; /* Number of Sectors */\r
183 UINT16 Rsvd1:10;\r
184 UINT16 Prinfo:4; /* Protection Info Check */\r
185 UINT16 Fua:1; /* Force Unit Access */\r
186 UINT16 Lr:1; /* Limited Retry */\r
187 //\r
188 // CDW 13\r
189 //\r
190 UINT32 Af:4; /* Access Frequency */\r
191 UINT32 Al:2; /* Access Latency */\r
192 UINT32 Sr:1; /* Sequential Request */\r
193 UINT32 In:1; /* Incompressible */\r
194 UINT32 Rsvd2:24;\r
195 //\r
196 // CDW 14\r
197 //\r
198 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
199 //\r
200 // CDW 15\r
201 //\r
202 UINT16 Lbat; /* Logical Block Application Tag */\r
203 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
204} NVME_WRITE;\r
205\r
206//\r
207// Flush\r
208//\r
209typedef struct {\r
210 //\r
211 // CDW 10\r
212 //\r
213 UINT32 Flush; /* Flush */\r
214} NVME_FLUSH;\r
215\r
216//\r
217// Write Uncorrectable command\r
218//\r
219typedef struct {\r
220 //\r
221 // CDW 10, 11\r
222 //\r
223 UINT64 Slba; /* Starting LBA */\r
224 //\r
225 // CDW 12\r
226 //\r
227 UINT32 Nlb:16; /* Number of Logical Blocks */\r
228 UINT32 Rsvd1:16;\r
229} NVME_WRITE_UNCORRECTABLE;\r
230\r
231//\r
232// Write Zeroes command\r
233//\r
234typedef struct {\r
235 //\r
236 // CDW 10, 11\r
237 //\r
238 UINT64 Slba; /* Starting LBA */\r
239 //\r
240 // CDW 12\r
241 //\r
242 UINT16 Nlb; /* Number of Logical Blocks */\r
243 UINT16 Rsvd1:10;\r
244 UINT16 Prinfo:4; /* Protection Info Check */\r
245 UINT16 Fua:1; /* Force Unit Access */\r
246 UINT16 Lr:1; /* Limited Retry */\r
247 //\r
248 // CDW 13\r
249 //\r
250 UINT32 Rsvd2;\r
251 //\r
252 // CDW 14\r
253 //\r
254 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
255 //\r
256 // CDW 15\r
257 //\r
258 UINT16 Lbat; /* Logical Block Application Tag */\r
259 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
260} NVME_WRITE_ZEROES;\r
261\r
262//\r
263// Compare command\r
264//\r
265typedef struct {\r
266 //\r
267 // CDW 10, 11\r
268 //\r
269 UINT64 Slba; /* Starting LBA */\r
270 //\r
271 // CDW 12\r
272 //\r
273 UINT16 Nlb; /* Number of Logical Blocks */\r
274 UINT16 Rsvd1:10;\r
275 UINT16 Prinfo:4; /* Protection Info Check */\r
276 UINT16 Fua:1; /* Force Unit Access */\r
277 UINT16 Lr:1; /* Limited Retry */\r
278 //\r
279 // CDW 13\r
280 //\r
281 UINT32 Rsvd2;\r
282 //\r
283 // CDW 14\r
284 //\r
285 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
286 //\r
287 // CDW 15\r
288 //\r
289 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
290 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
291} NVME_COMPARE;\r
292\r
293typedef union {\r
294 NVME_READ Read;\r
295 NVME_WRITE Write;\r
296 NVME_FLUSH Flush;\r
297 NVME_WRITE_UNCORRECTABLE WriteUncorrectable;\r
298 NVME_WRITE_ZEROES WriteZeros;\r
299 NVME_COMPARE Compare;\r
300} NVME_CMD;\r
301\r
302typedef struct {\r
303 UINT16 Mp; /* Maximum Power */\r
304 UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */\r
305 UINT8 Mps:1; /* Max Power Scale */\r
306 UINT8 Nops:1; /* Non-Operational State */\r
307 UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */\r
308 UINT32 Enlat; /* Entry Latency */\r
309 UINT32 Exlat; /* Exit Latency */\r
310 UINT8 Rrt:5; /* Relative Read Throughput */\r
311 UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */\r
312 UINT8 Rrl:5; /* Relative Read Leatency */\r
313 UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */\r
314 UINT8 Rwt:5; /* Relative Write Throughput */\r
315 UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */\r
316 UINT8 Rwl:5; /* Relative Write Leatency */\r
317 UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */\r
318 UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */\r
319} NVME_PSDESCRIPTOR;\r
320\r
321//\r
322// Identify Controller Data\r
323//\r
324typedef struct {\r
325 //\r
326 // Controller Capabilities and Features 0-255\r
327 //\r
328 UINT16 Vid; /* PCI Vendor ID */\r
329 UINT16 Ssvid; /* PCI sub-system vendor ID */\r
330 UINT8 Sn[20]; /* Product serial number */\r
331\r
332 UINT8 Mn[40]; /* Proeduct model number */\r
333 UINT8 Fr[8]; /* Firmware Revision */\r
334 UINT8 Rab; /* Recommended Arbitration Burst */\r
335 UINT8 Ieee_oui[3]; /* Organization Unique Identifier */\r
336 UINT8 Cmic; /* Multi-interface Capabilities */\r
337 UINT8 Mdts; /* Maximum Data Transfer Size */\r
338 UINT8 Cntlid[2]; /* Controller ID */\r
339 UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */\r
340 //\r
341 // Admin Command Set Attributes\r
342 //\r
343 UINT16 Oacs; /* Optional Admin Command Support */\r
344 #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3\r
345 #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2\r
346 #define FORMAT_NVM_SUPPORTED BIT1\r
347 #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0\r
348 UINT8 Acl; /* Abort Command Limit */\r
349 UINT8 Aerl; /* Async Event Request Limit */\r
350 UINT8 Frmw; /* Firmware updates */\r
351 UINT8 Lpa; /* Log Page Attributes */\r
352 UINT8 Elpe; /* Error Log Page Entries */\r
353 UINT8 Npss; /* Number of Power States Support */\r
354 UINT8 Avscc; /* Admin Vendor Specific Command Configuration */\r
355 UINT8 Apsta; /* Autonomous Power State Transition Attributes */\r
356 UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */\r
357 //\r
358 // NVM Command Set Attributes\r
359 //\r
360 UINT8 Sqes; /* Submission Queue Entry Size */\r
361 UINT8 Cqes; /* Completion Queue Entry Size */\r
362 UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */\r
363 UINT32 Nn; /* Number of Namespaces */\r
364 UINT16 Oncs; /* Optional NVM Command Support */\r
365 UINT16 Fuses; /* Fused Operation Support */\r
366 UINT8 Fna; /* Format NVM Attributes */\r
367 UINT8 Vwc; /* Volatile Write Cache */\r
368 UINT16 Awun; /* Atomic Write Unit Normal */\r
369 UINT16 Awupf; /* Atomic Write Unit Power Fail */\r
370 UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */\r
371 UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */\r
372 UINT16 Acwu; /* Atomic Compare & Write Unit */\r
373 UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */\r
374 UINT32 Sgls; /* SGL Support */\r
375 UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */\r
376 //\r
377 // I/O Command set Attributes\r
378 //\r
379 UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */\r
380 //\r
381 // Power State Descriptors\r
382 //\r
383 NVME_PSDESCRIPTOR PsDescriptor[32];\r
384\r
385 UINT8 VendorData[1024]; /* Vendor specific data */\r
386} NVME_ADMIN_CONTROLLER_DATA;\r
387\r
388typedef struct {\r
389 UINT16 Ms; /* Metadata Size */\r
390 UINT8 Lbads; /* LBA Data Size */\r
391 UINT8 Rp:2; /* Relative Performance */\r
392 #define LBAF_RP_BEST 00b\r
393 #define LBAF_RP_BETTER 01b\r
394 #define LBAF_RP_GOOD 10b\r
395 #define LBAF_RP_DEGRADED 11b\r
396 UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */\r
397} NVME_LBAFORMAT;\r
398\r
399//\r
400// Identify Namespace Data\r
401//\r
402typedef struct {\r
403 //\r
404 // NVM Command Set Specific\r
405 //\r
406 UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */\r
407 UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */\r
408 UINT64 Nuse; /* Namespace Utilization */\r
409 UINT8 Nsfeat; /* Namespace Features */\r
410 UINT8 Nlbaf; /* Number of LBA Formats */\r
411 UINT8 Flbas; /* Formatted LBA size */\r
412 UINT8 Mc; /* Metadata Capabilities */\r
413 UINT8 Dpc; /* End-to-end Data Protection capabilities */\r
414 UINT8 Dps; /* End-to-end Data Protection Type Settings */\r
415 UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */\r
416 UINT8 Rescap; /* Reservation Capabilities */\r
417 UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */\r
418 UINT64 Eui64; /* IEEE Extended Unique Identifier */\r
419 //\r
420 // LBA Format\r
421 //\r
422 NVME_LBAFORMAT LbaFormat[16];\r
423\r
424 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */\r
425 UINT8 VendorData[3712]; /* Vendor specific data */\r
426} NVME_ADMIN_NAMESPACE_DATA;\r
427\r
428//\r
429// NvmExpress Admin Identify Cmd\r
430//\r
431typedef struct {\r
432 //\r
433 // CDW 10\r
434 //\r
435 UINT32 Cns:2;\r
436 UINT32 Rsvd1:30;\r
437} NVME_ADMIN_IDENTIFY;\r
438\r
439//\r
440// NvmExpress Admin Create I/O Completion Queue\r
441//\r
442typedef struct {\r
443 //\r
444 // CDW 10\r
445 //\r
446 UINT32 Qid:16; /* Queue Identifier */\r
447 UINT32 Qsize:16; /* Queue Size */\r
448\r
449 //\r
450 // CDW 11\r
451 //\r
452 UINT32 Pc:1; /* Physically Contiguous */\r
453 UINT32 Ien:1; /* Interrupts Enabled */\r
454 UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */\r
455 UINT32 Iv:16; /* Interrupt Vector for MSI-X or MSI*/\r
456} NVME_ADMIN_CRIOCQ;\r
457\r
458//\r
459// NvmExpress Admin Create I/O Submission Queue\r
460//\r
461typedef struct {\r
462 //\r
463 // CDW 10\r
464 //\r
465 UINT32 Qid:16; /* Queue Identifier */\r
466 UINT32 Qsize:16; /* Queue Size */\r
467\r
468 //\r
469 // CDW 11\r
470 //\r
471 UINT32 Pc:1; /* Physically Contiguous */\r
472 UINT32 Qprio:2; /* Queue Priority */\r
473 UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */\r
474 UINT32 Cqid:16; /* Completion Queue ID */\r
475} NVME_ADMIN_CRIOSQ;\r
476\r
477//\r
478// NvmExpress Admin Delete I/O Completion Queue\r
479//\r
480typedef struct {\r
481 //\r
482 // CDW 10\r
483 //\r
484 UINT16 Qid;\r
485 UINT16 Rsvd1;\r
486} NVME_ADMIN_DEIOCQ;\r
487\r
488//\r
489// NvmExpress Admin Delete I/O Submission Queue\r
490//\r
491typedef struct {\r
492 //\r
493 // CDW 10\r
494 //\r
495 UINT16 Qid;\r
496 UINT16 Rsvd1;\r
497} NVME_ADMIN_DEIOSQ;\r
498\r
499//\r
500// NvmExpress Admin Abort Command\r
501//\r
502typedef struct {\r
503 //\r
504 // CDW 10\r
505 //\r
506 UINT32 Sqid:16; /* Submission Queue identifier */\r
507 UINT32 Cid:16; /* Command Identifier */\r
508} NVME_ADMIN_ABORT;\r
509\r
510//\r
511// NvmExpress Admin Firmware Activate Command\r
512//\r
513typedef struct {\r
514 //\r
515 // CDW 10\r
516 //\r
517 UINT32 Fs:3; /* Submission Queue identifier */\r
518 UINT32 Aa:2; /* Command Identifier */\r
519 UINT32 Rsvd1:27;\r
520} NVME_ADMIN_FIRMWARE_ACTIVATE;\r
521\r
522//\r
523// NvmExpress Admin Firmware Image Download Command\r
524//\r
525typedef struct {\r
526 //\r
527 // CDW 10\r
528 //\r
529 UINT32 Numd; /* Number of Dwords */\r
530 //\r
531 // CDW 11\r
532 //\r
533 UINT32 Ofst; /* Offset */\r
534} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;\r
535\r
536//\r
537// NvmExpress Admin Get Features Command\r
538//\r
539typedef struct {\r
540 //\r
541 // CDW 10\r
542 //\r
543 UINT32 Fid:8; /* Feature Identifier */\r
544 UINT32 Sel:3; /* Select */\r
545 UINT32 Rsvd1:21;\r
546} NVME_ADMIN_GET_FEATURES;\r
547\r
548//\r
549// NvmExpress Admin Get Log Page Command\r
550//\r
551typedef struct {\r
552 //\r
553 // CDW 10\r
554 //\r
555 UINT32 Lid:8; /* Log Page Identifier */\r
556 #define LID_ERROR_INFO 0x1\r
557 #define LID_SMART_INFO 0x2\r
558 #define LID_FW_SLOT_INFO 0x3\r
559 UINT32 Rsvd1:8;\r
560 UINT32 Numd:12; /* Number of Dwords */\r
561 UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */\r
562} NVME_ADMIN_GET_LOG_PAGE;\r
563\r
564//\r
565// NvmExpress Admin Set Features Command\r
566//\r
567typedef struct {\r
568 //\r
569 // CDW 10\r
570 //\r
571 UINT32 Fid:8; /* Feature Identifier */\r
572 UINT32 Rsvd1:23;\r
573 UINT32 Sv:1; /* Save */\r
574} NVME_ADMIN_SET_FEATURES;\r
575\r
576//\r
577// NvmExpress Admin Format NVM Command\r
578//\r
579typedef struct {\r
580 //\r
581 // CDW 10\r
582 //\r
583 UINT32 Lbaf:4; /* LBA Format */\r
584 UINT32 Ms:1; /* Metadata Settings */\r
585 UINT32 Pi:3; /* Protection Information */\r
586 UINT32 Pil:1; /* Protection Information Location */\r
587 UINT32 Ses:3; /* Secure Erase Settings */\r
588 UINT32 Rsvd1:20;\r
589} NVME_ADMIN_FORMAT_NVM;\r
590\r
591//\r
592// NvmExpress Admin Security Receive Command\r
593//\r
594typedef struct {\r
595 //\r
596 // CDW 10\r
597 //\r
598 UINT32 Rsvd1:8;\r
599 UINT32 Spsp:16; /* SP Specific */\r
600 UINT32 Secp:8; /* Security Protocol */\r
601 //\r
602 // CDW 11\r
603 //\r
604 UINT32 Al; /* Allocation Length */\r
605} NVME_ADMIN_SECURITY_RECEIVE;\r
606\r
607//\r
608// NvmExpress Admin Security Send Command\r
609//\r
610typedef struct {\r
611 //\r
612 // CDW 10\r
613 //\r
614 UINT32 Rsvd1:8;\r
615 UINT32 Spsp:16; /* SP Specific */\r
616 UINT32 Secp:8; /* Security Protocol */\r
617 //\r
618 // CDW 11\r
619 //\r
620 UINT32 Tl; /* Transfer Length */\r
621} NVME_ADMIN_SECURITY_SEND;\r
622\r
623typedef union {\r
624 NVME_ADMIN_IDENTIFY Identify;\r
625 NVME_ADMIN_CRIOCQ CrIoCq;\r
626 NVME_ADMIN_CRIOSQ CrIoSq;\r
627 NVME_ADMIN_DEIOCQ DeIoCq;\r
628 NVME_ADMIN_DEIOSQ DeIoSq;\r
629 NVME_ADMIN_ABORT Abort;\r
630 NVME_ADMIN_FIRMWARE_ACTIVATE Activate;\r
631 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;\r
632 NVME_ADMIN_GET_FEATURES GetFeatures;\r
633 NVME_ADMIN_GET_LOG_PAGE GetLogPage;\r
634 NVME_ADMIN_SET_FEATURES SetFeatures;\r
635 NVME_ADMIN_FORMAT_NVM FormatNvm;\r
636 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;\r
637 NVME_ADMIN_SECURITY_SEND SecuritySend;\r
638} NVME_ADMIN_CMD;\r
639\r
640typedef struct {\r
641 UINT32 Cdw10;\r
642 UINT32 Cdw11;\r
643 UINT32 Cdw12;\r
644 UINT32 Cdw13;\r
645 UINT32 Cdw14;\r
646 UINT32 Cdw15;\r
647} NVME_RAW;\r
648\r
649typedef union {\r
650 NVME_ADMIN_CMD Admin; // Union of Admin commands\r
651 NVME_CMD Nvm; // Union of Nvm commands\r
652 NVME_RAW Raw;\r
653} NVME_PAYLOAD;\r
654\r
655//\r
656// Submission Queue\r
657//\r
658typedef struct {\r
659 //\r
660 // CDW 0, Common to all comnmands\r
661 //\r
662 UINT8 Opc; // Opcode\r
663 UINT8 Fuse:2; // Fused Operation\r
664 UINT8 Rsvd1:5;\r
665 UINT8 Psdt:1; // PRP or SGL for Data Transfer\r
666 UINT16 Cid; // Command Identifier\r
667\r
668 //\r
669 // CDW 1\r
670 //\r
671 UINT32 Nsid; // Namespace Identifier\r
672\r
673 //\r
674 // CDW 2,3\r
675 //\r
676 UINT64 Rsvd2;\r
677\r
678 //\r
679 // CDW 4,5\r
680 //\r
681 UINT64 Mptr; // Metadata Pointer\r
682\r
683 //\r
684 // CDW 6-9\r
685 //\r
686 UINT64 Prp[2]; // First and second PRP entries\r
687\r
688 NVME_PAYLOAD Payload;\r
689\r
690} NVME_SQ;\r
691\r
692//\r
693// Completion Queue\r
694//\r
695typedef struct {\r
696 //\r
697 // CDW 0\r
698 //\r
699 UINT32 Dword0;\r
700 //\r
701 // CDW 1\r
702 //\r
703 UINT32 Rsvd1;\r
704 //\r
705 // CDW 2\r
706 //\r
707 UINT16 Sqhd; // Submission Queue Head Pointer\r
708 UINT16 Sqid; // Submission Queue Identifier\r
709 //\r
710 // CDW 3\r
711 //\r
712 UINT16 Cid; // Command Identifier\r
713 UINT16 Pt:1; // Phase Tag\r
714 UINT16 Sc:8; // Status Code\r
715 UINT16 Sct:3; // Status Code Type\r
716 UINT16 Rsvd2:2;\r
717 UINT16 Mo:1; // More\r
718 UINT16 Dnr:1; // Do Not Retry\r
719} NVME_CQ;\r
720\r
721//\r
722// Nvm Express Admin cmd opcodes\r
723//\r
724#define NVME_ADMIN_DEIOSQ_CMD 0x00\r
725#define NVME_ADMIN_CRIOSQ_CMD 0x01\r
726#define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02\r
727#define NVME_ADMIN_DEIOCQ_CMD 0x04\r
728#define NVME_ADMIN_CRIOCQ_CMD 0x05\r
729#define NVME_ADMIN_IDENTIFY_CMD 0x06\r
730#define NVME_ADMIN_ABORT_CMD 0x08\r
731#define NVME_ADMIN_SET_FEATURES_CMD 0x09\r
732#define NVME_ADMIN_GET_FEATURES_CMD 0x0A\r
733#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C\r
734#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D\r
735#define NVME_ADMIN_FW_COMMIT_CMD 0x10\r
736#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11\r
737#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15\r
738#define NVME_ADMIN_FORMAT_NVM_CMD 0x80\r
739#define NVME_ADMIN_SECURITY_SEND_CMD 0x81\r
740#define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82\r
741\r
742#define NVME_IO_FLUSH_OPC 0\r
743#define NVME_IO_WRITE_OPC 1\r
744#define NVME_IO_READ_OPC 2\r
745\r
746typedef enum {\r
747 DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,\r
748 CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,\r
749 GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,\r
750 DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,\r
751 CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,\r
752 IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,\r
753 AbortOpcode = NVME_ADMIN_ABORT_CMD,\r
754 SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,\r
755 GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,\r
756 AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,\r
757 NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,\r
758 FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,\r
759 FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,\r
760 NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,\r
761 FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,\r
762 SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,\r
763 SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD\r
764} NVME_ADMIN_COMMAND_OPCODE;\r
765\r
766//\r
767// Controller or Namespace Structure (CNS) field\r
768// (ref. spec. v1.1 figure 82).\r
769//\r
770typedef enum {\r
771IdentifyNamespaceCns = 0x0,\r
772IdentifyControllerCns = 0x1,\r
773IdentifyActiveNsListCns = 0x2\r
774} NVME_ADMIN_IDENTIFY_CNS;\r
775\r
776//\r
777// Commit Action\r
778// (ref. spec. 1.1 figure 60).\r
779//\r
780typedef enum {\r
781 ActivateActionReplace = 0x0,\r
782 ActivateActionReplaceActivate = 0x1,\r
783 ActivateActionActivate = 0x2\r
784} NVME_FW_ACTIVATE_ACTION;\r
785\r
786//\r
787// Firmware Slot\r
788// (ref. spec. 1.1 Figure 60).\r
789//\r
790typedef enum {\r
791 FirmwareSlotCtrlChooses = 0x0,\r
792 FirmwareSlot1 = 0x1,\r
793 FirmwareSlot2 = 0x2,\r
794 FirmwareSlot3 = 0x3,\r
795 FirmwareSlot4 = 0x4,\r
796 FirmwareSlot5 = 0x5,\r
797 FirmwareSlot6 = 0x6,\r
798 FirmwareSlot7 = 0x7\r
799} NVME_FW_ACTIVATE_SLOT;\r
800\r
801//\r
802// Get Log Page ? Log Page Identifiers\r
803// (ref. spec. v1.1 Figure 73).\r
804//\r
805typedef enum {\r
806 ErrorInfoLogID = LID_ERROR_INFO,\r
807 SmartHealthInfoLogID = LID_SMART_INFO,\r
808 FirmwareSlotInfoLogID = LID_FW_SLOT_INFO\r
809} NVME_LOG_ID;\r
810\r
811//\r
812// Get Log Page ? Firmware Slot Information Log\r
813// (ref. spec. v1.1 Figure 77).\r
814//\r
815typedef struct {\r
816 //\r
817 // Indicates the firmware slot from which the actively running firmware revision was loaded.\r
818 //\r
819 UINT8 ActivelyRunningFwSlot:3;\r
820 UINT8 :1;\r
821 //\r
822 // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.\r
823 //\r
824 UINT8 NextActiveFwSlot:3;\r
825 UINT8 :1;\r
826} NVME_ACTIVE_FW_INFO;\r
827\r
828//\r
829// Get Log Page ? Firmware Slot Information Log\r
830// (ref. spec. v1.1 Figure 77).\r
831//\r
832typedef struct {\r
833 //\r
834 // Specifies information about the active firmware revision.\r
835 //s\r
836 NVME_ACTIVE_FW_INFO ActiveFwInfo;\r
837 UINT8 Reserved1[7];\r
838 //\r
839 // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.\r
840 //\r
841 CHAR8 FwRevisionSlot[7][8];\r
842 UINT8 Reserved2[448];\r
843} NVME_FW_SLOT_INFO_LOG;\r
844\r
845//\r
846// SMART / Health Information (Log Identifier 02h)\r
847// (ref. spec. v1.1 5.10.1.2)\r
848//\r
849typedef struct {\r
850 //\r
851 // This field indicates critical warnings for the state of the controller.\r
852 //\r
853 UINT8 CriticalWarningAvailableSpare:1;\r
854 UINT8 CriticalWarningTemperature:1;\r
855 UINT8 CriticalWarningReliability:1;\r
856 UINT8 CriticalWarningMediaReadOnly:1;\r
857 UINT8 CriticalWarningVolatileBackup:1;\r
858 UINT8 CriticalWarningReserved:3;\r
859 //\r
860 // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.\r
861 //\r
862 UINT16 CompositeTemp;\r
863 //\r
864 // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.\r
865 //\r
866 UINT8 AvailableSpare;\r
867 //\r
868 // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).\r
869 //\r
870 UINT8 AvailableSpareThreshold;\r
871 //\r
872 // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer?s prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).\r
873 //\r
874 UINT8 PercentageUsed;\r
875 UINT8 Reserved1[26];\r
876 //\r
877 // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.\r
878 //\r
879 UINT8 DataUnitsRead[16];\r
880 //\r
881 // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.\r
882 //\r
883 UINT8 DataUnitsWritten[16];\r
884 //\r
885 // Contains the number of read commands completed by the controller.\r
886 //\r
887 UINT8 HostReadCommands[16];\r
888 //\r
889 // Contains the number of write commands completed by the controller.\r
890 //\r
891 UINT8 HostWriteCommands[16];\r
892 //\r
893 // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.\r
894 //\r
895 UINT8 ControllerBusyTime[16];\r
896 //\r
897 // Contains the number of power cycles.\r
898 //\r
899 UINT8 PowerCycles[16];\r
900 //\r
901 // Contains the number of power-on hours.\r
902 //\r
903 UINT8 PowerOnHours[16];\r
904 //\r
905 // Contains the number of unsafe shutdowns.\r
906 //\r
907 UINT8 UnsafeShutdowns[16];\r
908 //\r
909 // Contains the number of occurrences where the controller detected an unrecovered data integrity error.\r
910 //\r
911 UINT8 MediaAndDataIntegrityErrors[16];\r
912 //\r
913 // Contains the number of Error Information log entries over the life of the controller.\r
914 //\r
915 UINT8 NumberErrorInformationLogEntries[16];\r
916 //\r
917 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.\r
918 //\r
919 UINT32 WarningCompositeTemperatureTime;\r
920 //\r
921 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.\r
922 //\r
923 UINT32 CriticalCompositeTemperatureTime;\r
924 //\r
925 // Contains the current temperature in degrees Kelvin reported by the temperature sensor. An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.\r
926 //\r
927 UINT16 TemperatureSensor[8];\r
928 UINT8 Reserved2[296];\r
929} NVME_SMART_HEALTH_INFO_LOG;\r
930\r
931#pragma pack()\r
932\r
933#endif\r
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