]> git.proxmox.com Git - mirror_edk2.git/blame_incremental - MdePkg/Include/IndustryStandard/Pci22.h
projects / mirror_edk2.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
BaseTools: Add missing EfiPersistentMemory to EFI_MEMORY_TYPE
[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pci22.h
... / ...
CommitLineData
1/** @file\r
2 Support for PCI 2.2 standard.\r
3\r
4 This file includes the definitions in the following specifications,\r
5 PCI Local Bus Specification, 2.2\r
6 PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
7 PC Card Standard, 8.0\r
8\r
9 \r
10\r
11 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
12 Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR>\r
13 This program and the accompanying materials \r
14 are licensed and made available under the terms and conditions of the BSD License \r
15 which accompanies this distribution. The full text of the license may be found at \r
16 http://opensource.org/licenses/bsd-license.php \r
17\r
18 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
19 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
20\r
21**/\r
22\r
23#ifndef _PCI22_H_\r
24#define _PCI22_H_\r
25\r
26#define PCI_MAX_BUS 255\r
27#define PCI_MAX_DEVICE 31\r
28#define PCI_MAX_FUNC 7\r
29\r
30#pragma pack(1)\r
31\r
32///\r
33/// Common header region in PCI Configuration Space\r
34/// Section 6.1, PCI Local Bus Specification, 2.2\r
35///\r
36typedef struct {\r
37 UINT16 VendorId;\r
38 UINT16 DeviceId;\r
39 UINT16 Command;\r
40 UINT16 Status;\r
41 UINT8 RevisionID;\r
42 UINT8 ClassCode[3];\r
43 UINT8 CacheLineSize;\r
44 UINT8 LatencyTimer;\r
45 UINT8 HeaderType;\r
46 UINT8 BIST;\r
47} PCI_DEVICE_INDEPENDENT_REGION;\r
48\r
49///\r
50/// PCI Device header region in PCI Configuration Space\r
51/// Section 6.1, PCI Local Bus Specification, 2.2\r
52///\r
53typedef struct {\r
54 UINT32 Bar[6];\r
55 UINT32 CISPtr;\r
56 UINT16 SubsystemVendorID;\r
57 UINT16 SubsystemID;\r
58 UINT32 ExpansionRomBar;\r
59 UINT8 CapabilityPtr;\r
60 UINT8 Reserved1[3];\r
61 UINT32 Reserved2;\r
62 UINT8 InterruptLine;\r
63 UINT8 InterruptPin;\r
64 UINT8 MinGnt;\r
65 UINT8 MaxLat;\r
66} PCI_DEVICE_HEADER_TYPE_REGION;\r
67\r
68///\r
69/// PCI Device Configuration Space\r
70/// Section 6.1, PCI Local Bus Specification, 2.2\r
71///\r
72typedef struct {\r
73 PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
74 PCI_DEVICE_HEADER_TYPE_REGION Device;\r
75} PCI_TYPE00;\r
76\r
77///\r
78/// PCI-PCI Bridge header region in PCI Configuration Space\r
79/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
80///\r
81typedef struct {\r
82 UINT32 Bar[2];\r
83 UINT8 PrimaryBus;\r
84 UINT8 SecondaryBus;\r
85 UINT8 SubordinateBus;\r
86 UINT8 SecondaryLatencyTimer;\r
87 UINT8 IoBase;\r
88 UINT8 IoLimit;\r
89 UINT16 SecondaryStatus;\r
90 UINT16 MemoryBase;\r
91 UINT16 MemoryLimit;\r
92 UINT16 PrefetchableMemoryBase;\r
93 UINT16 PrefetchableMemoryLimit;\r
94 UINT32 PrefetchableBaseUpper32;\r
95 UINT32 PrefetchableLimitUpper32;\r
96 UINT16 IoBaseUpper16;\r
97 UINT16 IoLimitUpper16;\r
98 UINT8 CapabilityPtr;\r
99 UINT8 Reserved[3];\r
100 UINT32 ExpansionRomBAR;\r
101 UINT8 InterruptLine;\r
102 UINT8 InterruptPin;\r
103 UINT16 BridgeControl;\r
104} PCI_BRIDGE_CONTROL_REGISTER;\r
105\r
106///\r
107/// PCI-to-PCI Bridge Configuration Space\r
108/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
109///\r
110typedef struct {\r
111 PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
112 PCI_BRIDGE_CONTROL_REGISTER Bridge;\r
113} PCI_TYPE01;\r
114\r
115typedef union {\r
116 PCI_TYPE00 Device;\r
117 PCI_TYPE01 Bridge;\r
118} PCI_TYPE_GENERIC;\r
119\r
120/// \r
121/// CardBus Conroller Configuration Space, \r
122/// Section 4.5.1, PC Card Standard. 8.0\r
123///\r
124typedef struct {\r
125 UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base\r
126 UINT8 Cap_Ptr;\r
127 UINT8 Reserved;\r
128 UINT16 SecondaryStatus; ///< Secondary Status\r
129 UINT8 PciBusNumber; ///< PCI Bus Number\r
130 UINT8 CardBusBusNumber; ///< CardBus Bus Number\r
131 UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r
132 UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r
133 UINT32 MemoryBase0; ///< Memory Base Register 0\r
134 UINT32 MemoryLimit0; ///< Memory Limit Register 0\r
135 UINT32 MemoryBase1;\r
136 UINT32 MemoryLimit1;\r
137 UINT32 IoBase0;\r
138 UINT32 IoLimit0; ///< I/O Base Register 0\r
139 UINT32 IoBase1; ///< I/O Limit Register 0\r
140 UINT32 IoLimit1;\r
141 UINT8 InterruptLine; ///< Interrupt Line\r
142 UINT8 InterruptPin; ///< Interrupt Pin\r
143 UINT16 BridgeControl; ///< Bridge Control\r
144} PCI_CARDBUS_CONTROL_REGISTER;\r
145\r
146//\r
147// Definitions of PCI class bytes and manipulation macros.\r
148//\r
149#define PCI_CLASS_OLD 0x00\r
150#define PCI_CLASS_OLD_OTHER 0x00\r
151#define PCI_CLASS_OLD_VGA 0x01\r
152\r
153#define PCI_CLASS_MASS_STORAGE 0x01\r
154#define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r
155#define PCI_CLASS_MASS_STORAGE_IDE 0x01\r
156#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
157#define PCI_CLASS_MASS_STORAGE_IPI 0x03\r
158#define PCI_CLASS_MASS_STORAGE_RAID 0x04\r
159#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r
160\r
161#define PCI_CLASS_NETWORK 0x02\r
162#define PCI_CLASS_NETWORK_ETHERNET 0x00 \r
163#define PCI_CLASS_NETWORK_TOKENRING 0x01\r
164#define PCI_CLASS_NETWORK_FDDI 0x02\r
165#define PCI_CLASS_NETWORK_ATM 0x03\r
166#define PCI_CLASS_NETWORK_ISDN 0x04\r
167#define PCI_CLASS_NETWORK_OTHER 0x80\r
168\r
169#define PCI_CLASS_DISPLAY 0x03\r
170#define PCI_CLASS_DISPLAY_VGA 0x00\r
171#define PCI_IF_VGA_VGA 0x00\r
172#define PCI_IF_VGA_8514 0x01\r
173#define PCI_CLASS_DISPLAY_XGA 0x01\r
174#define PCI_CLASS_DISPLAY_3D 0x02\r
175#define PCI_CLASS_DISPLAY_OTHER 0x80 \r
176\r
177#define PCI_CLASS_MEDIA 0x04\r
178#define PCI_CLASS_MEDIA_VIDEO 0x00\r
179#define PCI_CLASS_MEDIA_AUDIO 0x01\r
180#define PCI_CLASS_MEDIA_TELEPHONE 0x02\r
181#define PCI_CLASS_MEDIA_OTHER 0x80\r
182\r
183#define PCI_CLASS_MEMORY_CONTROLLER 0x05\r
184#define PCI_CLASS_MEMORY_RAM 0x00\r
185#define PCI_CLASS_MEMORY_FLASH 0x01\r
186#define PCI_CLASS_MEMORY_OTHER 0x80\r
187\r
188#define PCI_CLASS_BRIDGE 0x06\r
189#define PCI_CLASS_BRIDGE_HOST 0x00\r
190#define PCI_CLASS_BRIDGE_ISA 0x01\r
191#define PCI_CLASS_BRIDGE_EISA 0x02\r
192#define PCI_CLASS_BRIDGE_MCA 0x03\r
193#define PCI_CLASS_BRIDGE_P2P 0x04\r
194#define PCI_IF_BRIDGE_P2P 0x00\r
195#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r
196#define PCI_CLASS_BRIDGE_PCMCIA 0x05\r
197#define PCI_CLASS_BRIDGE_NUBUS 0x06\r
198#define PCI_CLASS_BRIDGE_CARDBUS 0x07\r
199#define PCI_CLASS_BRIDGE_RACEWAY 0x08\r
200#define PCI_CLASS_BRIDGE_OTHER 0x80\r
201#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
202\r
203#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers \r
204#define PCI_SUBCLASS_SERIAL 0x00\r
205#define PCI_IF_GENERIC_XT 0x00\r
206#define PCI_IF_16450 0x01\r
207#define PCI_IF_16550 0x02\r
208#define PCI_IF_16650 0x03\r
209#define PCI_IF_16750 0x04\r
210#define PCI_IF_16850 0x05\r
211#define PCI_IF_16950 0x06\r
212#define PCI_SUBCLASS_PARALLEL 0x01\r
213#define PCI_IF_PARALLEL_PORT 0x00\r
214#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r
215#define PCI_IF_ECP_PARALLEL_PORT 0x02\r
216#define PCI_IF_1284_CONTROLLER 0x03\r
217#define PCI_IF_1284_DEVICE 0xFE\r
218#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
219#define PCI_SUBCLASS_MODEM 0x03\r
220#define PCI_IF_GENERIC_MODEM 0x00\r
221#define PCI_IF_16450_MODEM 0x01\r
222#define PCI_IF_16550_MODEM 0x02\r
223#define PCI_IF_16650_MODEM 0x03\r
224#define PCI_IF_16750_MODEM 0x04\r
225#define PCI_SUBCLASS_SCC_OTHER 0x80\r
226\r
227#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
228#define PCI_SUBCLASS_PIC 0x00\r
229#define PCI_IF_8259_PIC 0x00\r
230#define PCI_IF_ISA_PIC 0x01\r
231#define PCI_IF_EISA_PIC 0x02\r
232#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory. \r
233#define PCI_IF_APIC_CONTROLLER2 0x20 \r
234#define PCI_SUBCLASS_DMA 0x01\r
235#define PCI_IF_8237_DMA 0x00\r
236#define PCI_IF_ISA_DMA 0x01\r
237#define PCI_IF_EISA_DMA 0x02\r
238#define PCI_SUBCLASS_TIMER 0x02\r
239#define PCI_IF_8254_TIMER 0x00\r
240#define PCI_IF_ISA_TIMER 0x01\r
241#define PCI_IF_EISA_TIMER 0x02\r
242#define PCI_SUBCLASS_RTC 0x03\r
243#define PCI_IF_GENERIC_RTC 0x00\r
244#define PCI_IF_ISA_RTC 0x01\r
245#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r
246#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r
247\r
248#define PCI_CLASS_INPUT_DEVICE 0x09\r
249#define PCI_SUBCLASS_KEYBOARD 0x00\r
250#define PCI_SUBCLASS_PEN 0x01\r
251#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
252#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
253#define PCI_SUBCLASS_GAMEPORT 0x04\r
254#define PCI_IF_GAMEPORT 0x00\r
255#define PCI_IF_GAMEPORT1 0x10\r
256#define PCI_SUBCLASS_INPUT_OTHER 0x80\r
257\r
258#define PCI_CLASS_DOCKING_STATION 0x0A\r
259#define PCI_SUBCLASS_DOCKING_GENERIC 0x00\r
260#define PCI_SUBCLASS_DOCKING_OTHER 0x80\r
261\r
262#define PCI_CLASS_PROCESSOR 0x0B\r
263#define PCI_SUBCLASS_PROC_386 0x00\r
264#define PCI_SUBCLASS_PROC_486 0x01\r
265#define PCI_SUBCLASS_PROC_PENTIUM 0x02\r
266#define PCI_SUBCLASS_PROC_ALPHA 0x10\r
267#define PCI_SUBCLASS_PROC_POWERPC 0x20\r
268#define PCI_SUBCLASS_PROC_MIPS 0x30\r
269#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r
270\r
271#define PCI_CLASS_SERIAL 0x0C\r
272#define PCI_CLASS_SERIAL_FIREWIRE 0x00\r
273#define PCI_IF_1394 0x00\r
274#define PCI_IF_1394_OPEN_HCI 0x10\r
275#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r
276#define PCI_CLASS_SERIAL_SSA 0x02\r
277#define PCI_CLASS_SERIAL_USB 0x03\r
278#define PCI_IF_UHCI 0x00\r
279#define PCI_IF_OHCI 0x10\r
280#define PCI_IF_USB_OTHER 0x80\r
281#define PCI_IF_USB_DEVICE 0xFE\r
282#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
283#define PCI_CLASS_SERIAL_SMB 0x05\r
284\r
285#define PCI_CLASS_WIRELESS 0x0D\r
286#define PCI_SUBCLASS_IRDA 0x00\r
287#define PCI_SUBCLASS_IR 0x01\r
288#define PCI_SUBCLASS_RF 0x10\r
289#define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r
290\r
291#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
292\r
293#define PCI_CLASS_SATELLITE 0x0F\r
294#define PCI_SUBCLASS_TV 0x01\r
295#define PCI_SUBCLASS_AUDIO 0x02\r
296#define PCI_SUBCLASS_VOICE 0x03\r
297#define PCI_SUBCLASS_DATA 0x04\r
298\r
299#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r
300#define PCI_SUBCLASS_NET_COMPUT 0x00\r
301#define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r
302#define PCI_SUBCLASS_SECURITY_OTHER 0x80\r
303\r
304#define PCI_CLASS_DPIO 0x11\r
305#define PCI_SUBCLASS_DPIO 0x00\r
306#define PCI_SUBCLASS_DPIO_OTHER 0x80\r
307\r
308/** \r
309 Macro that checks whether the Base Class code of device matched.\r
310\r
311 @param _p Specified device.\r
312 @param c Base Class code needs matching.\r
313\r
314 @retval TRUE Base Class code matches the specified device.\r
315 @retval FALSE Base Class code doesn't match the specified device. \r
316\r
317**/\r
318#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
319/** \r
320 Macro that checks whether the Base Class code and Sub-Class code of device matched.\r
321\r
322 @param _p Specified device.\r
323 @param c Base Class code needs matching.\r
324 @param s Sub-Class code needs matching.\r
325\r
326 @retval TRUE Base Class code and Sub-Class code match the specified device.\r
327 @retval FALSE Base Class code and Sub-Class code don't match the specified device. \r
328\r
329**/\r
330#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
331/** \r
332 Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.\r
333\r
334 @param _p Specified device.\r
335 @param c Base Class code needs matching.\r
336 @param s Sub-Class code needs matching.\r
337 @param p Interface code needs matching.\r
338\r
339 @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.\r
340 @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device. \r
341\r
342**/\r
343#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
344\r
345/** \r
346 Macro that checks whether device is a display controller.\r
347\r
348 @param _p Specified device.\r
349\r
350 @retval TRUE Device is a display controller.\r
351 @retval FALSE Device is not a display controller.\r
352\r
353**/\r
354#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
355/** \r
356 Macro that checks whether device is a VGA-compatible controller.\r
357\r
358 @param _p Specified device.\r
359\r
360 @retval TRUE Device is a VGA-compatible controller.\r
361 @retval FALSE Device is not a VGA-compatible controller.\r
362\r
363**/\r
364#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\r
365/** \r
366 Macro that checks whether device is an 8514-compatible controller.\r
367\r
368 @param _p Specified device.\r
369\r
370 @retval TRUE Device is an 8514-compatible controller.\r
371 @retval FALSE Device is not an 8514-compatible controller.\r
372\r
373**/\r
374#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\r
375/** \r
376 Macro that checks whether device is built before the Class Code field was defined.\r
377\r
378 @param _p Specified device.\r
379\r
380 @retval TRUE Device is an old device.\r
381 @retval FALSE Device is not an old device.\r
382\r
383**/\r
384#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
385/** \r
386 Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.\r
387\r
388 @param _p Specified device.\r
389\r
390 @retval TRUE Device is an old VGA-compatible device.\r
391 @retval FALSE Device is not an old VGA-compatible device.\r
392\r
393**/\r
394#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
395/** \r
396 Macro that checks whether device is an IDE controller.\r
397\r
398 @param _p Specified device.\r
399\r
400 @retval TRUE Device is an IDE controller.\r
401 @retval FALSE Device is not an IDE controller.\r
402\r
403**/\r
404#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
405/** \r
406 Macro that checks whether device is a SCSI bus controller.\r
407\r
408 @param _p Specified device.\r
409\r
410 @retval TRUE Device is a SCSI bus controller.\r
411 @retval FALSE Device is not a SCSI bus controller.\r
412\r
413**/\r
414#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\r
415/** \r
416 Macro that checks whether device is a RAID controller.\r
417\r
418 @param _p Specified device.\r
419\r
420 @retval TRUE Device is a RAID controller.\r
421 @retval FALSE Device is not a RAID controller.\r
422\r
423**/\r
424#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\r
425/** \r
426 Macro that checks whether device is an ISA bridge.\r
427\r
428 @param _p Specified device.\r
429\r
430 @retval TRUE Device is an ISA bridge.\r
431 @retval FALSE Device is not an ISA bridge.\r
432\r
433**/\r
434#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\r
435/** \r
436 Macro that checks whether device is a PCI-to-PCI bridge.\r
437\r
438 @param _p Specified device.\r
439\r
440 @retval TRUE Device is a PCI-to-PCI bridge.\r
441 @retval FALSE Device is not a PCI-to-PCI bridge.\r
442\r
443**/\r
444#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\r
445/** \r
446 Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.\r
447\r
448 @param _p Specified device.\r
449\r
450 @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.\r
451 @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.\r
452\r
453**/\r
454#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\r
455/** \r
456 Macro that checks whether device is a 16550-compatible serial controller.\r
457\r
458 @param _p Specified device.\r
459\r
460 @retval TRUE Device is a 16550-compatible serial controller.\r
461 @retval FALSE Device is not a 16550-compatible serial controller.\r
462\r
463**/\r
464#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
465/** \r
466 Macro that checks whether device is a Universal Serial Bus controller.\r
467\r
468 @param _p Specified device.\r
469\r
470 @retval TRUE Device is a Universal Serial Bus controller.\r
471 @retval FALSE Device is not a Universal Serial Bus controller.\r
472\r
473**/\r
474#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
475\r
476//\r
477// the definition of Header Type \r
478//\r
479#define HEADER_TYPE_DEVICE 0x00\r
480#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
481#define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r
482#define HEADER_TYPE_MULTI_FUNCTION 0x80\r
483//\r
484// Mask of Header type\r
485//\r
486#define HEADER_LAYOUT_CODE 0x7f\r
487/** \r
488 Macro that checks whether device is a PCI-PCI bridge.\r
489\r
490 @param _p Specified device.\r
491\r
492 @retval TRUE Device is a PCI-PCI bridge.\r
493 @retval FALSE Device is not a PCI-PCI bridge.\r
494\r
495**/\r
496#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
497/** \r
498 Macro that checks whether device is a CardBus bridge.\r
499\r
500 @param _p Specified device.\r
501\r
502 @retval TRUE Device is a CardBus bridge.\r
503 @retval FALSE Device is not a CardBus bridge.\r
504\r
505**/\r
506#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
507/** \r
508 Macro that checks whether device is a multiple functions device.\r
509\r
510 @param _p Specified device.\r
511\r
512 @retval TRUE Device is a multiple functions device.\r
513 @retval FALSE Device is not a multiple functions device.\r
514\r
515**/\r
516#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
517\r
518///\r
519/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,\r
520///\r
521#define PCI_BRIDGE_ROMBAR 0x38\r
522\r
523#define PCI_MAX_BAR 0x0006\r
524#define PCI_MAX_CONFIG_OFFSET 0x0100\r
525\r
526#define PCI_VENDOR_ID_OFFSET 0x00\r
527#define PCI_DEVICE_ID_OFFSET 0x02\r
528#define PCI_COMMAND_OFFSET 0x04\r
529#define PCI_PRIMARY_STATUS_OFFSET 0x06\r
530#define PCI_REVISION_ID_OFFSET 0x08\r
531#define PCI_CLASSCODE_OFFSET 0x09\r
532#define PCI_CACHELINE_SIZE_OFFSET 0x0C\r
533#define PCI_LATENCY_TIMER_OFFSET 0x0D\r
534#define PCI_HEADER_TYPE_OFFSET 0x0E\r
535#define PCI_BIST_OFFSET 0x0F\r
536#define PCI_BASE_ADDRESSREG_OFFSET 0x10\r
537#define PCI_CARDBUS_CIS_OFFSET 0x28\r
538#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r
539#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r
540#define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r
541#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r
542#define PCI_EXPANSION_ROM_BASE 0x30\r
543#define PCI_CAPBILITY_POINTER_OFFSET 0x34\r
544#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r
545#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r
546#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r
547#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r
548\r
549//\r
550// defined in PCI-to-PCI Bridge Architecture Specification\r
551//\r
552#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r
553#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r
554#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r
555#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E \r
556#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E \r
557\r
558///\r
559/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
560///\r
561#define PCI_INT_LINE_UNKNOWN 0xFF \r
562\r
563///\r
564/// PCI Access Data Format\r
565///\r
566typedef union {\r
567 struct {\r
568 UINT32 Reg : 8;\r
569 UINT32 Func : 3;\r
570 UINT32 Dev : 5;\r
571 UINT32 Bus : 8;\r
572 UINT32 Reserved : 7;\r
573 UINT32 Enable : 1;\r
574 } Bits;\r
575 UINT32 Uint32;\r
576} PCI_CONFIG_ACCESS_CF8;\r
577\r
578#pragma pack()\r
579\r
580#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r
581#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r
582#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r
583#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r
584#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r
585#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r
586#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r
587#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r
588#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r
589#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r
590\r
591//\r
592// defined in PCI-to-PCI Bridge Architecture Specification\r
593//\r
594#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\r
595#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\r
596#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\r
597#define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008\r
598#define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010\r
599#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020\r
600#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040\r
601#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080\r
602#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100\r
603#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200\r
604#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\r
605#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\r
606\r
607//\r
608// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
609//\r
610#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r
611#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r
612#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r
613#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r
614\r
615//\r
616// Following are the PCI status control bit\r
617//\r
618#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r
619#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r
620#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r
621#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r
622\r
623///\r
624/// defined in PC Card Standard\r
625///\r
626#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
627\r
628#pragma pack(1)\r
629//\r
630// PCI Capability List IDs and records\r
631//\r
632#define EFI_PCI_CAPABILITY_ID_PMI 0x01\r
633#define EFI_PCI_CAPABILITY_ID_AGP 0x02\r
634#define EFI_PCI_CAPABILITY_ID_VPD 0x03\r
635#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
636#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
637#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
638\r
639///\r
640/// Capabilities List Header\r
641/// Section 6.7, PCI Local Bus Specification, 2.2\r
642///\r
643typedef struct {\r
644 UINT8 CapabilityID;\r
645 UINT8 NextItemPtr;\r
646} EFI_PCI_CAPABILITY_HDR;\r
647\r
648///\r
649/// Power Management Register Block Definition \r
650/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
651///\r
652typedef struct {\r
653 EFI_PCI_CAPABILITY_HDR Hdr;\r
654 UINT16 PMC;\r
655 UINT16 PMCSR;\r
656 UINT8 BridgeExtention;\r
657 UINT8 Data;\r
658} EFI_PCI_CAPABILITY_PMI;\r
659\r
660///\r
661/// PMC - Power Management Capabilities\r
662/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2\r
663///\r
664typedef union {\r
665 struct {\r
666 UINT16 Version : 3;\r
667 UINT16 PmeClock : 1;\r
668 UINT16 : 1;\r
669 UINT16 DeviceSpecificInitialization : 1;\r
670 UINT16 AuxCurrent : 3;\r
671 UINT16 D1Support : 1;\r
672 UINT16 D2Support : 1;\r
673 UINT16 PmeSupport : 5;\r
674 } Bits;\r
675 UINT16 Data;\r
676} EFI_PCI_PMC;\r
677\r
678#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)\r
679\r
680///\r
681/// PMCSR - Power Management Control/Status\r
682/// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2\r
683///\r
684typedef union {\r
685 struct {\r
686 UINT16 PowerState : 2;\r
687 UINT16 : 6;\r
688 UINT16 PmeEnable : 1;\r
689 UINT16 DataSelect : 4;\r
690 UINT16 DataScale : 2;\r
691 UINT16 PmeStatus : 1;\r
692 } Bits;\r
693 UINT16 Data;\r
694} EFI_PCI_PMCSR;\r
695\r
696///\r
697/// A.G.P Capability\r
698/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r
699///\r
700typedef struct {\r
701 EFI_PCI_CAPABILITY_HDR Hdr;\r
702 UINT8 Rev;\r
703 UINT8 Reserved;\r
704 UINT32 Status;\r
705 UINT32 Command;\r
706} EFI_PCI_CAPABILITY_AGP;\r
707\r
708///\r
709/// VPD Capability Structure\r
710/// Appendix I, PCI Local Bus Specification, 2.2\r
711///\r
712typedef struct {\r
713 EFI_PCI_CAPABILITY_HDR Hdr;\r
714 UINT16 AddrReg;\r
715 UINT32 DataReg;\r
716} EFI_PCI_CAPABILITY_VPD;\r
717\r
718///\r
719/// Slot Numbering Capabilities Register\r
720/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2\r
721///\r
722typedef struct {\r
723 EFI_PCI_CAPABILITY_HDR Hdr;\r
724 UINT8 ExpnsSlotReg;\r
725 UINT8 ChassisNo;\r
726} EFI_PCI_CAPABILITY_SLOTID;\r
727\r
728///\r
729/// Message Capability Structure for 32-bit Message Address\r
730/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
731///\r
732typedef struct {\r
733 EFI_PCI_CAPABILITY_HDR Hdr;\r
734 UINT16 MsgCtrlReg;\r
735 UINT32 MsgAddrReg;\r
736 UINT16 MsgDataReg;\r
737} EFI_PCI_CAPABILITY_MSI32;\r
738\r
739///\r
740/// Message Capability Structure for 64-bit Message Address\r
741/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
742///\r
743typedef struct {\r
744 EFI_PCI_CAPABILITY_HDR Hdr;\r
745 UINT16 MsgCtrlReg;\r
746 UINT32 MsgAddrRegLsdw;\r
747 UINT32 MsgAddrRegMsdw;\r
748 UINT16 MsgDataReg;\r
749} EFI_PCI_CAPABILITY_MSI64;\r
750\r
751///\r
752/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, \r
753/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r
754///\r
755typedef struct {\r
756 EFI_PCI_CAPABILITY_HDR Hdr;\r
757 ///\r
758 /// not finished - fields need to go here\r
759 ///\r
760} EFI_PCI_CAPABILITY_HOTPLUG;\r
761\r
762#define DEVICE_ID_NOCARE 0xFFFF\r
763\r
764#define PCI_ACPI_UNUSED 0\r
765#define PCI_BAR_NOCHANGE 0\r
766#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL\r
767#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL\r
768#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r
769#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r
770\r
771#define PCI_BAR_IDX0 0x00\r
772#define PCI_BAR_IDX1 0x01\r
773#define PCI_BAR_IDX2 0x02\r
774#define PCI_BAR_IDX3 0x03\r
775#define PCI_BAR_IDX4 0x04\r
776#define PCI_BAR_IDX5 0x05\r
777#define PCI_BAR_ALL 0xFF\r
778\r
779///\r
780/// EFI PCI Option ROM definitions\r
781/// \r
782#define EFI_ROOT_BRIDGE_LIST 'eprb' \r
783#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r
784\r
785#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
786#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r
787#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
788#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\r
789\r
790///\r
791/// Standard PCI Expansion ROM Header\r
792/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
793///\r
794typedef struct {\r
795 UINT16 Signature; ///< 0xaa55\r
796 UINT8 Reserved[0x16];\r
797 UINT16 PcirOffset;\r
798} PCI_EXPANSION_ROM_HEADER;\r
799\r
800///\r
801/// Legacy ROM Header Extensions\r
802/// Section 6.3.3.1, PCI Local Bus Specification, 2.2\r
803///\r
804typedef struct {\r
805 UINT16 Signature; ///< 0xaa55\r
806 UINT8 Size512;\r
807 UINT8 InitEntryPoint[3];\r
808 UINT8 Reserved[0x12];\r
809 UINT16 PcirOffset;\r
810} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
811\r
812///\r
813/// PCI Data Structure Format\r
814/// Section 6.3.1.2, PCI Local Bus Specification, 2.2\r
815///\r
816typedef struct {\r
817 UINT32 Signature; ///< "PCIR"\r
818 UINT16 VendorId;\r
819 UINT16 DeviceId;\r
820 UINT16 Reserved0;\r
821 UINT16 Length;\r
822 UINT8 Revision;\r
823 UINT8 ClassCode[3];\r
824 UINT16 ImageLength;\r
825 UINT16 CodeRevision;\r
826 UINT8 CodeType;\r
827 UINT8 Indicator;\r
828 UINT16 Reserved1;\r
829} PCI_DATA_STRUCTURE;\r
830\r
831///\r
832/// EFI PCI Expansion ROM Header\r
833/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
834///\r
835typedef struct {\r
836 UINT16 Signature; ///< 0xaa55\r
837 UINT16 InitializationSize;\r
838 UINT32 EfiSignature; ///< 0x0EF1\r
839 UINT16 EfiSubsystem;\r
840 UINT16 EfiMachineType;\r
841 UINT16 CompressionType;\r
842 UINT8 Reserved[8];\r
843 UINT16 EfiImageHeaderOffset;\r
844 UINT16 PcirOffset;\r
845} EFI_PCI_EXPANSION_ROM_HEADER;\r
846\r
847typedef union {\r
848 UINT8 *Raw;\r
849 PCI_EXPANSION_ROM_HEADER *Generic;\r
850 EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r
851 EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r
852} EFI_PCI_ROM_HEADER;\r
853\r
854#pragma pack()\r
855\r
856#endif\r
EFI Development Kit II mirror for PVE