[mirror_edk2.git] / MdePkg / Include / IndustryStandard / TpmTis.h

/** @file\r
  TPM Interface Specification definition.\r
  It covers both TPM1.2 and TPM2.0.\r
\r
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _TPM_TIS_H_\r
#define _TPM_TIS_H_\r
\r
//\r
// Set structure alignment to 1-byte\r
//\r
#pragma pack (1)\r
\r
//\r
// Register set map as specified in TIS specification Chapter 10\r
//\r
typedef struct {\r
  ///\r
  /// Used to gain ownership for this particular port.\r
  ///\r
  UINT8     Access;                                     // 0\r
  UINT8     Reserved1[7];                               // 1\r
  ///\r
  /// Controls interrupts.\r
  ///\r
  UINT32    IntEnable;                                  // 8\r
  ///\r
  /// SIRQ vector to be used by the TPM.\r
  ///\r
  UINT8     IntVector;                                  // 0ch\r
  UINT8     Reserved2[3];                               // 0dh\r
  ///\r
  /// What caused interrupt.\r
  ///\r
  UINT32    IntSts;                                     // 10h\r
  ///\r
  /// Shows which interrupts are supported by that particular TPM.\r
  ///\r
  UINT32    IntfCapability;                             // 14h\r
  ///\r
  /// Status Register. Provides status of the TPM.\r
  ///\r
  UINT8     Status;                                     // 18h\r
  ///\r
  /// Number of consecutive writes that can be done to the TPM.\r
  ///\r
  UINT16    BurstCount;                                 // 19h\r
  UINT8     Reserved3[9];\r
  ///\r
  /// Read or write FIFO, depending on transaction.\r
  ///\r
  UINT32    DataFifo;                                   // 24h\r
  UINT8     Reserved4[0xed8];                           // 28h\r
  ///\r
  /// Vendor ID\r
  ///\r
  UINT16    Vid;                                        // 0f00h\r
  ///\r
  /// Device ID\r
  ///\r
  UINT16    Did;                                        // 0f02h\r
  ///\r
  /// Revision ID\r
  ///\r
  UINT8     Rid;                                        // 0f04h\r
  UINT8     Reserved[0x7b];                             // 0f05h\r
  ///\r
  /// Alias to I/O legacy space.\r
  ///\r
  UINT32    LegacyAddress1;                             // 0f80h\r
  ///\r
  /// Additional 8 bits for I/O legacy space extension.\r
  ///\r
  UINT32    LegacyAddress1Ex;                           // 0f84h\r
  ///\r
  /// Alias to second I/O legacy space.\r
  ///\r
  UINT32    LegacyAddress2;                             // 0f88h\r
  ///\r
  /// Additional 8 bits for second I/O legacy space extension.\r
  ///\r
  UINT32    LegacyAddress2Ex;                           // 0f8ch\r
  ///\r
  /// Vendor-defined configuration registers.\r
  ///\r
  UINT8     VendorDefined[0x70];                        // 0f90h\r
} TIS_PC_REGISTERS;\r
\r
//\r
// Restore original structure alignment\r
//\r
#pragma pack ()\r
\r
//\r
// Define pointer types used to access TIS registers on PC\r
//\r
typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
\r
//\r
// Define bits of ACCESS and STATUS registers\r
//\r
\r
///\r
/// This bit is a 1 to indicate that the other bits in this register are valid.\r
///\r
#define TIS_PC_VALID  BIT7\r
///\r
/// Indicate that this locality is active.\r
///\r
#define TIS_PC_ACC_ACTIVE  BIT5\r
///\r
/// Set to 1 to indicate that this locality had the TPM taken away while\r
/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
///\r
#define TIS_PC_ACC_SEIZED  BIT4\r
///\r
/// Set to 1 to indicate that TPM MUST reset the\r
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
/// locality that is writing this bit.\r
///\r
#define TIS_PC_ACC_SEIZE  BIT3\r
///\r
/// When this bit is 1, another locality is requesting usage of the TPM.\r
///\r
#define TIS_PC_ACC_PENDIND  BIT2\r
///\r
/// Set to 1 to indicate that this locality is requesting to use TPM.\r
///\r
#define TIS_PC_ACC_RQUUSE  BIT1\r
///\r
/// A value of 1 indicates that a T/OS has not been established on the platform\r
///\r
#define TIS_PC_ACC_ESTABLISH  BIT0\r
\r
///\r
/// Write a 1 to this bit to notify TPM to cancel currently executing command\r
///\r
#define TIS_PC_STS_CANCEL  BIT24\r
///\r
/// This field indicates that STS_DATA and STS_EXPECT are valid\r
///\r
#define TIS_PC_STS_VALID  BIT7\r
///\r
/// When this bit is 1, TPM is in the Ready state,\r
/// indicating it is ready to receive a new command.\r
///\r
#define TIS_PC_STS_READY  BIT6\r
///\r
/// Write a 1 to this bit to cause the TPM to execute that command.\r
///\r
#define TIS_PC_STS_GO  BIT5\r
///\r
/// This bit indicates that the TPM has data available as a response.\r
///\r
#define TIS_PC_STS_DATA  BIT4\r
///\r
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
///\r
#define TIS_PC_STS_EXPECT  BIT3\r
///\r
/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
///\r
#define TIS_PC_STS_SELFTEST_DONE  BIT2\r
///\r
/// Writes a 1 to this bit to force the TPM to re-send the response.\r
///\r
#define TIS_PC_STS_RETRY  BIT1\r
\r
//\r
// Default TimeOut value\r
//\r
#define TIS_TIMEOUT_A  (750  * 1000)               // 750ms\r
#define TIS_TIMEOUT_B  (2000 * 1000)               // 2s\r
#define TIS_TIMEOUT_C  (750  * 1000)               // 750ms\r
#define TIS_TIMEOUT_D  (750  * 1000)               // 750ms\r
\r
#endif\r
Commit	Line	Data
	1	/** @file\r
	2	TPM Interface Specification definition.\r
	3	It covers both TPM1.2 and TPM2.0.\r
	4	\r
	5	Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
	7	\r
	8	**/\r
	9	\r
	10	#ifndef _TPM_TIS_H_\r
	11	#define _TPM_TIS_H_\r
	12	\r
	13	//\r
	14	// Set structure alignment to 1-byte\r
	15	//\r
	16	#pragma pack (1)\r
	17	\r
	18	//\r
	19	// Register set map as specified in TIS specification Chapter 10\r
	20	//\r
	21	typedef struct {\r
	22	///\r
	23	/// Used to gain ownership for this particular port.\r
	24	///\r
	25	UINT8 Access; // 0\r
	26	UINT8 Reserved1[7]; // 1\r
	27	///\r
	28	/// Controls interrupts.\r
	29	///\r
	30	UINT32 IntEnable; // 8\r
	31	///\r
	32	/// SIRQ vector to be used by the TPM.\r
	33	///\r
	34	UINT8 IntVector; // 0ch\r
	35	UINT8 Reserved2[3]; // 0dh\r
	36	///\r
	37	/// What caused interrupt.\r
	38	///\r
	39	UINT32 IntSts; // 10h\r
	40	///\r
	41	/// Shows which interrupts are supported by that particular TPM.\r
	42	///\r
	43	UINT32 IntfCapability; // 14h\r
	44	///\r
	45	/// Status Register. Provides status of the TPM.\r
	46	///\r
	47	UINT8 Status; // 18h\r
	48	///\r
	49	/// Number of consecutive writes that can be done to the TPM.\r
	50	///\r
	51	UINT16 BurstCount; // 19h\r
	52	UINT8 Reserved3[9];\r
	53	///\r
	54	/// Read or write FIFO, depending on transaction.\r
	55	///\r
	56	UINT32 DataFifo; // 24h\r
	57	UINT8 Reserved4[0xed8]; // 28h\r
	58	///\r
	59	/// Vendor ID\r
	60	///\r
	61	UINT16 Vid; // 0f00h\r
	62	///\r
	63	/// Device ID\r
	64	///\r
	65	UINT16 Did; // 0f02h\r
	66	///\r
	67	/// Revision ID\r
	68	///\r
	69	UINT8 Rid; // 0f04h\r
	70	UINT8 Reserved[0x7b]; // 0f05h\r
	71	///\r
	72	/// Alias to I/O legacy space.\r
	73	///\r
	74	UINT32 LegacyAddress1; // 0f80h\r
	75	///\r
	76	/// Additional 8 bits for I/O legacy space extension.\r
	77	///\r
	78	UINT32 LegacyAddress1Ex; // 0f84h\r
	79	///\r
	80	/// Alias to second I/O legacy space.\r
	81	///\r
	82	UINT32 LegacyAddress2; // 0f88h\r
	83	///\r
	84	/// Additional 8 bits for second I/O legacy space extension.\r
	85	///\r
	86	UINT32 LegacyAddress2Ex; // 0f8ch\r
	87	///\r
	88	/// Vendor-defined configuration registers.\r
	89	///\r
	90	UINT8 VendorDefined[0x70]; // 0f90h\r
	91	} TIS_PC_REGISTERS;\r
	92	\r
	93	//\r
	94	// Restore original structure alignment\r
	95	//\r
	96	#pragma pack ()\r
	97	\r
	98	//\r
	99	// Define pointer types used to access TIS registers on PC\r
	100	//\r
	101	typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
	102	\r
	103	//\r
	104	// Define bits of ACCESS and STATUS registers\r
	105	//\r
	106	\r
	107	///\r
	108	/// This bit is a 1 to indicate that the other bits in this register are valid.\r
	109	///\r
	110	#define TIS_PC_VALID BIT7\r
	111	///\r
	112	/// Indicate that this locality is active.\r
	113	///\r
	114	#define TIS_PC_ACC_ACTIVE BIT5\r
	115	///\r
	116	/// Set to 1 to indicate that this locality had the TPM taken away while\r
	117	/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
	118	///\r
	119	#define TIS_PC_ACC_SEIZED BIT4\r
	120	///\r
	121	/// Set to 1 to indicate that TPM MUST reset the\r
	122	/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
	123	/// locality that is writing this bit.\r
	124	///\r
	125	#define TIS_PC_ACC_SEIZE BIT3\r
	126	///\r
	127	/// When this bit is 1, another locality is requesting usage of the TPM.\r
	128	///\r
	129	#define TIS_PC_ACC_PENDIND BIT2\r
	130	///\r
	131	/// Set to 1 to indicate that this locality is requesting to use TPM.\r
	132	///\r
	133	#define TIS_PC_ACC_RQUUSE BIT1\r
	134	///\r
	135	/// A value of 1 indicates that a T/OS has not been established on the platform\r
	136	///\r
	137	#define TIS_PC_ACC_ESTABLISH BIT0\r
	138	\r
	139	///\r
	140	/// Write a 1 to this bit to notify TPM to cancel currently executing command\r
	141	///\r
	142	#define TIS_PC_STS_CANCEL BIT24\r
	143	///\r
	144	/// This field indicates that STS_DATA and STS_EXPECT are valid\r
	145	///\r
	146	#define TIS_PC_STS_VALID BIT7\r
	147	///\r
	148	/// When this bit is 1, TPM is in the Ready state,\r
	149	/// indicating it is ready to receive a new command.\r
	150	///\r
	151	#define TIS_PC_STS_READY BIT6\r
	152	///\r
	153	/// Write a 1 to this bit to cause the TPM to execute that command.\r
	154	///\r
	155	#define TIS_PC_STS_GO BIT5\r
	156	///\r
	157	/// This bit indicates that the TPM has data available as a response.\r
	158	///\r
	159	#define TIS_PC_STS_DATA BIT4\r
	160	///\r
	161	/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
	162	///\r
	163	#define TIS_PC_STS_EXPECT BIT3\r
	164	///\r
	165	/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
	166	///\r
	167	#define TIS_PC_STS_SELFTEST_DONE BIT2\r
	168	///\r
	169	/// Writes a 1 to this bit to force the TPM to re-send the response.\r
	170	///\r
	171	#define TIS_PC_STS_RETRY BIT1\r
	172	\r
	173	//\r
	174	// Default TimeOut value\r
	175	//\r
	176	#define TIS_TIMEOUT_A (750 * 1000) // 750ms\r
	177	#define TIS_TIMEOUT_B (2000 * 1000) // 2s\r
	178	#define TIS_TIMEOUT_C (750 * 1000) // 750ms\r
	179	#define TIS_TIMEOUT_D (750 * 1000) // 750ms\r
	180	\r
	181	#endif\r