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1/** @file\r
2 PAL Call Services\r
3\r
4 Copyright (c) 2006 -2008, Intel Corporation All rights\r
5 reserved. This program and the accompanying materials are\r
6 licensed and made available under the terms and conditions of\r
7 the BSD License which accompanies this distribution. The full\r
8 text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef __PAL_CALL_LIB_H__\r
17#define __PAL_CALL_LIB_H__\r
18\r
19#define PAL_SUCCESS 0x0\r
20\r
21//\r
22// CacheType of PAL_CACHE_FLUSH.\r
23//\r
24#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r
25#define PAL_CACHE_FLUSH_DATA_ALL 2\r
26#define PAL_CACHE_FLUSH_ALL 3\r
27#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r
28\r
29\r
30//\r
31// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
32//\r
33#define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0\r
34#define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0\r
35#define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1\r
36#define PAL_CACHE_FLUSH_NO_INTERRUPT 0\r
37\r
38/**\r
39 PAL Procedure - PAL_CACHE_FLUSH.\r
40\r
41 Flush the instruction or data caches. It is required by IPF.\r
42 The PAL procedure supports the Static Registers calling\r
43 convention. It could be called at virtual mode and physical\r
44 mode.\r
45\r
46 @param Index Index of PAL_CACHE_FLUSH within the\r
47 list of PAL procedures.\r
48 @param CacheType Unsigned 64-bit integer indicating\r
49 which cache to flush.\r
50 @param Operation Formatted bit vector indicating the\r
51 operation of this call.\r
52 @param ProgressIndicator Unsigned 64-bit integer specifying\r
53 the starting position of the flush\r
54 operation.\r
55\r
56 @retval 2 Call completed without error, but a PMI\r
57 was taken during the execution of this\r
58 procedure.\r
59 @retval 1 Call has not completed flushing due to\r
60 a pending interrupt.\r
61 @retval 0 Call completed without error\r
62 @retval -2 Invalid argument\r
63 @retval -3 Call completed with error\r
64\r
65 @return R9 Unsigned 64-bit integer specifying the vector\r
66 number of the pending interrupt.\r
67 @return R10 Unsigned 64-bit integer specifying the\r
68 starting position of the flush operation.\r
69 @return R11 Unsigned 64-bit integer specifying the vector\r
70 number of the pending interrupt.\r
71\r
72**/\r
73#define PAL_CACHE_FLUSH 1\r
74\r
75\r
76//\r
77// Attributes of PAL_CACHE_CONFIG_INFO1\r
78//\r
79#define PAL_CACHE_ATTR_WT 0\r
80#define PAL_CACHE_ATTR_WB 1\r
81\r
82//\r
83// PAL_CACHE_CONFIG_INFO1.StoreHint\r
84//\r
85#define PAL_CACHE_STORE_TEMPORAL 0\r
86#define PAL_CACHE_STORE_NONE_TEMPORAL 3\r
87\r
88//\r
89// PAL_CACHE_CONFIG_INFO1.StoreHint\r
90//\r
91#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r
92#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r
93\r
94//\r
95// PAL_CACHE_CONFIG_INFO1.StoreHint\r
96//\r
97#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r
98#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r
99#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r
100\r
101//\r
102// Detail the characteristics of a given processor controlled\r
103// cache in the cache hierarchy.\r
104//\r
105typedef struct {\r
106 UINT64 IsUnified : 1;\r
107 UINT64 Attributes : 2;\r
108 UINT64 Associativity:8;\r
109 UINT64 LineSize:8;\r
110 UINT64 Stride:8;\r
111 UINT64 StoreLatency:8;\r
112 UINT64 StoreHint:8;\r
113 UINT64 LoadHint:8;\r
114} PAL_CACHE_INFO_RETURN1;\r
115\r
116//\r
117// Detail the characteristics of a given processor controlled\r
118// cache in the cache hierarchy.\r
119//\r
120typedef struct {\r
121 UINT64 CacheSize:32;\r
122 UINT64 AliasBoundary:8;\r
123 UINT64 TagLsBits:8;\r
124 UINT64 TagMsBits:8;\r
125} PAL_CACHE_INFO_RETURN2;\r
126\r
127/**\r
128 PAL Procedure - PAL_CACHE_INFO.\r
129\r
130 Return detailed instruction or data cache information. It is\r
131 required by IPF. The PAL procedure supports the Static\r
132 Registers calling convention. It could be called at virtual\r
133 mode and physical mode.\r
134\r
135 @param Index Index of PAL_CACHE_INFO within the list of\r
136 PAL procedures.\r
137 @param CacheLevel Unsigned 64-bit integer specifying the\r
138 level in the cache hierarchy for which\r
139 information is requested. This value must\r
140 be between 0 and one less than the value\r
141 returned in the cache_levels return value\r
142 from PAL_CACHE_SUMMARY.\r
143 @param CacheType Unsigned 64-bit integer with a value of 1\r
144 for instruction cache and 2 for data or\r
145 unified cache. All other values are\r
146 reserved.\r
147 @param Reserved Should be 0.\r
148\r
149 @retval 0 Call completed without error\r
150 @retval -2 Invalid argument\r
151 @retval -3 Call completed with error\r
152\r
153 @return R9 Detail the characteristics of a given\r
154 processor controlled cache in the cache\r
155 hierarchy. See PAL_CACHE_INFO_RETURN1.\r
156 @return R10 Detail the characteristics of a given\r
157 processor controlled cache in the cache\r
158 hierarchy. See PAL_CACHE_INFO_RETURN2.\r
159 @return R11 Reserved with 0.\r
160\r
161**/\r
162#define PAL_CACHE_INFO 2\r
163\r
164\r
165\r
166//\r
167// Level of PAL_CACHE_INIT.\r
168//\r
169#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r
170\r
171//\r
172// CacheType\r
173//\r
174#define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1\r
175#define PAL_CACHE_INIT_TYPE_DATA 0x2\r
176#define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3\r
177\r
178//\r
179// Restrict of PAL_CACHE_INIT.\r
180//\r
181#define PAL_CACHE_INIT_NO_RESTRICT 0\r
182#define PAL_CACHE_INIT_RESTRICTED 1\r
183\r
184/**\r
185 PAL Procedure - PAL_CACHE_INIT.\r
186\r
187 Initialize the instruction or data caches. It is required by\r
188 IPF. The PAL procedure supports the Static Registers calling\r
189 convention. It could be called at physical mode.\r
190\r
191 @param Index Index of PAL_CACHE_INIT within the list of PAL\r
192 procedures.\r
193 @param Level Unsigned 64-bit integer containing the level of\r
194 cache to initialize. If the cache level can be\r
195 initialized independently, only that level will\r
196 be initialized. Otherwise\r
197 implementation-dependent side-effects will\r
198 occur.\r
199 @param CacheType Unsigned 64-bit integer with a value of 1 to\r
200 initialize the instruction cache, 2 to\r
201 initialize the data cache, or 3 to\r
202 initialize both. All other values are\r
203 reserved.\r
204 @param Restrict Unsigned 64-bit integer with a value of 0 or\r
205 1. All other values are reserved. If\r
206 restrict is 1 and initializing the specified\r
207 level and cache_type of the cache would\r
208 cause side-effects, PAL_CACHE_INIT will\r
209 return -4 instead of initializing the cache.\r
210\r
211 @retval 0 Call completed without error\r
212 @retval -2 Invalid argument\r
213 @retval -3 Call completed with error.\r
214 @retval -4 Call could not initialize the specified\r
215 level and cache_type of the cache without\r
216 side-effects and restrict was 1.\r
217\r
218**/\r
219#define PAL_CACHE_INIT 3\r
220\r
221\r
222//\r
223// PAL_CACHE_PROTECTION.Method.\r
224//\r
225#define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r
226#define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r
227#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r
228#define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r
229\r
230\r
231\r
232//\r
233// PAL_CACHE_PROTECTION.TagOrData.\r
234//\r
235#define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r
236#define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r
237#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r
238#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r
239\r
240//\r
241// 32-bit protection information structures.\r
242//\r
243typedef struct {\r
244 UINT32 DataBits:8;\r
245 UINT32 TagProtLsb:6;\r
246 UINT32 TagProtMsb:6;\r
247 UINT32 ProtBits:6;\r
248 UINT32 Method:4;\r
249 UINT32 TagOrData:2;\r
250} PAL_CACHE_PROTECTION;\r
251\r
252/**\r
253 PAL Procedure - PAL_CACHE_PROT_INFO.\r
254\r
255 Return instruction or data cache protection information. It is\r
256 required by IPF. The PAL procedure supports the Static\r
257 Registers calling convention. It could be called at physical\r
258 mode and Virtual mode.\r
259\r
260 @param Index Index of PAL_CACHE_PROT_INFO within the list of\r
261 PAL procedures.\r
262 @param CacheLevel Unsigned 64-bit integer specifying the level\r
263 in the cache hierarchy for which information\r
264 is requested. This value must be between 0\r
265 and one less than the value returned in the\r
266 cache_levels return value from\r
267 PAL_CACHE_SUMMARY.\r
268 @param CacheType Unsigned 64-bit integer with a value of 1\r
269 for instruction cache and 2 for data or\r
270 unified cache. All other values are\r
271 reserved.\r
272\r
273 @retval 0 Call completed without error\r
274 @retval -2 Invalid argument\r
275 @retval -3 Call completed with error.\r
276\r
277 @return R9 Detail the characteristics of a given\r
278 processor controlled cache in the cache\r
279 hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
280 @return R10 Detail the characteristics of a given\r
281 processor controlled cache in the cache\r
282 hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
283 @return R11 Detail the characteristics of a given\r
284 processor controlled cache in the cache\r
285 hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
286\r
287**/\r
288#define PAL_CACHE_PROT_INFO 38\r
289\r
290/**\r
291\r
292 @param ThreadId The thread identifier of the logical\r
293 processor for which information is being\r
294 returned. This value will be unique on a per\r
295 core basis.\r
296\r
297 @param CoreId The core identifier of the logical processor\r
298 for which information is being returned.\r
299 This value will be unique on a per physical\r
300 processor package basis.\r
301\r
302**/\r
303typedef struct {\r
304 UINT64 ThreadId : 16;\r
305 UINT64 Reserved1: 16;\r
306 UINT64 CoreId: 16;\r
307 UINT64 Reserved2: 16;\r
308} PAL_PCOC_N_CACHE_INFO1;\r
309\r
310/**\r
311\r
312 @param LogicalAddress Logical address: geographical address\r
313 of the logical processor for which\r
314 information is being returned. This is\r
315 the same value that is returned by the\r
316 PAL_FIXED_ADDR procedure when it is\r
317 called on the logical processor.\r
318\r
319**/\r
320typedef struct {\r
321 UINT64 LogicalAddress : 16;\r
322 UINT64 Reserved1: 16;\r
323 UINT64 Reserved2: 32;\r
324} PAL_PCOC_N_CACHE_INFO2;\r
325\r
326/**\r
327 PAL Procedure - PAL_CACHE_SHARED_INFO.\r
328\r
329 Returns information on which logical processors share caches.\r
330 It is optional. The PAL procedure supports the Static\r
331 Registers calling convention. It could be called at physical\r
332 mode and Virtual mode.\r
333\r
334 @param Index Index of PAL_CACHE_SHARED_INFO within the list\r
335 of PAL procedures.\r
336 @param CacheLevel Unsigned 64-bit integer specifying the\r
337 level in the cache hierarchy for which\r
338 information is requested. This value must\r
339 be between 0 and one less than the value\r
340 returned in the cache_levels return value\r
341 from PAL_CACHE_SUMMARY.\r
342 @param CacheType Unsigned 64-bit integer with a value of 1\r
343 for instruction cache and 2 for data or\r
344 unified cache. All other values are\r
345 reserved.\r
346 @param ProcNumber Unsigned 64-bit integer that specifies for\r
347 which logical processor information is\r
348 being requested. This input argument must\r
349 be zero for the first call to this\r
350 procedure and can be a maximum value of\r
351 one less than the number of logical\r
352 processors sharing this cache, which is\r
353 returned by the num_shared return value.\r
354\r
355 @retval 0 Call completed without error\r
356 @retval -1 Unimplemented procedure\r
357 @retval -2 Invalid argument\r
358 @retval -3 Call completed with error.\r
359\r
360 @return R9 Unsigned integer that returns the number of\r
361 logical processors that share the processor\r
362 cache level and type, for which information was\r
363 requested.\r
364 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.\r
365 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.\r
366\r
367**/\r
368#define PAL_CACHE_SHARED_INFO 43\r
369\r
370\r
371/**\r
372 PAL Procedure - PAL_CACHE_SUMMARY.\r
373\r
374 Return a summary of the cache hierarchy. It is required by\r
375 IPF. The PAL procedure supports the Static Registers calling\r
376 convention. It could be called at physical mode and Virtual\r
377 mode.\r
378\r
379 @param Index Index of PAL_CACHE_SUMMARY within the list of\r
380 PAL procedures.\r
381\r
382 @retval 0 Call completed without error\r
383 @retval -2 Invalid argument\r
384 @retval -3 Call completed with error.\r
385\r
386 @return R9 CacheLevels Unsigned 64-bit integer denoting the\r
387 number of levels of cache\r
388 implemented by the processor.\r
389 Strictly, this is the number of\r
390 levels for which the cache\r
391 controller is integrated into the\r
392 processor (the cache SRAMs may be\r
393 external to the processor).\r
394 @return R10 UniqueCaches Unsigned 64-bit integer denoting the\r
395 number of unique caches implemented\r
396 by the processor. This has a maximum\r
397 of 2*cache_levels, but may be less\r
398 if any of the levels in the cache\r
399 hierarchy are unified caches or do\r
400 not have both instruction and data\r
401 caches.\r
402\r
403**/\r
404#define PAL_CACHE_SUMMARY 4\r
405\r
406\r
407//\r
408// Virtual Memory Attributes implemented by processor.\r
409//\r
410#define PAL_MEMORY_ATTR_WB 0\r
411#define PAL_MEMORY_ATTR_WC 6\r
412#define PAL_MEMORY_ATTR_UC 4\r
413#define PAL_MEMORY_ATTR_UCE 5\r
414#define PAL_MEMORY_ATTR_NATPAGE 7\r
415\r
416/**\r
417 PAL Procedure - PAL_MEM_ATTRIB.\r
418\r
419 Return a list of supported memory attributes.. It is required\r
420 by IPF. The PAL procedure supports the Static Registers calling\r
421 convention. It could be called at physical mode and Virtual\r
422 mode.\r
423\r
424 @param Index Index of PAL_MEM_ATTRIB within the list of PAL\r
425 procedures.\r
426\r
427 @retval 0 Call completed without error\r
428 @retval -2 Invalid argument\r
429 @retval -3 Call completed with error.\r
430\r
431 @return R9 Attributes 8-bit vector of memory attributes\r
432 implemented by processor. See Virtual\r
433 Memory Attributes above.\r
434\r
435**/\r
436\r
437#define PAL_MEM_ATTRIB 5\r
438\r
439/**\r
440 PAL Procedure - PAL_PREFETCH_VISIBILITY.\r
441\r
442 Used in architected sequence to transition pages from a\r
443 cacheable, speculative attribute to an uncacheable attribute.\r
444 It is required by IPF. The PAL procedure supports the Static\r
445 Registers calling convention. It could be called at physical\r
446 mode and Virtual mode.\r
447\r
448 @param Index Index of PAL_PREFETCH_VISIBILITY within the list\r
449 of PAL procedures.\r
450 @param TransitionType Unsigned integer specifying the type\r
451 of memory attribute transition that is\r
452 being performed.\r
453\r
454 @retval 1 Call completed without error; this\r
455 call is not necessary on remote\r
456 processors.\r
457 @retval 0 Call completed without error\r
458 @retval -2 Invalid argument\r
459 @retval -3 Call completed with error.\r
460\r
461**/\r
462#define PAL_PREFETCH_VISIBILITY 41\r
463\r
464/**\r
465 PAL Procedure - PAL_PTCE_INFO.\r
466\r
467 Return information needed for ptc.e instruction to purge\r
468 entire TC. It is required by IPF. The PAL procedure supports\r
469 the Static Registers calling convention. It could be called at\r
470 physical mode and Virtual mode.\r
471\r
472 @param Index Index of PAL_PTCE_INFO within the list\r
473 of PAL procedures.\r
474\r
475 @retval 0 Call completed without error\r
476 @retval -2 Invalid argument\r
477 @retval -3 Call completed with error.\r
478\r
479 @return R9 Unsigned 64-bit integer denoting the beginning\r
480 address to be used by the first PTCE instruction\r
481 in the purge loop.\r
482 @return R10 Two unsigned 32-bit integers denoting the loop\r
483 counts of the outer (loop 1) and inner (loop 2)\r
484 purge loops. count1 (loop 1) is contained in bits\r
485 63:32 of the parameter, and count2 (loop 2) is\r
486 contained in bits 31:0 of the parameter.\r
487 @return R11 Two unsigned 32-bit integers denoting the loop\r
488 strides of the outer (loop 1) and inner (loop 2)\r
489 purge loops. stride1 (loop 1) is contained in bits\r
490 63:32 of the parameter, and stride2 (loop 2) is\r
491 contained in bits 31:0 of the parameter.\r
492\r
493**/\r
494#define PAL_PTCE_INFO 6\r
495\r
496\r
497\r
498/**\r
499\r
500 @param NumberSets Unsigned 8-bit integer denoting the number\r
501 of hash sets for the specified level\r
502 (1=fully associative)\r
503\r
504 @param NumberWays Unsigned 8-bit integer denoting the\r
505 associativity of the specified level\r
506 (1=direct).\r
507\r
508 @param NumberEntries Unsigned 16-bit integer denoting the\r
509 number of entries in the specified TC.\r
510\r
511\r
512 @param PageSizeIsOptimized Flag denoting whether the\r
513 specified level is optimized for\r
514 the region's preferred page size\r
515 (1=optimized) tc_pages indicates\r
516 which page sizes are usable by\r
517 this translation cache.\r
518\r
519 @param TcIsUnified Flag denoting whether the specified TC is\r
520 unified (1=unified).\r
521\r
522 @param EntriesReduction Flag denoting whether installed\r
523 translation registers will reduce\r
524 the number of entries within the\r
525 specified TC.\r
526\r
527**/\r
528typedef struct {\r
529 UINT64 NumberSets:8;\r
530 UINT64 NumberWays:8;\r
531 UINT64 NumberEntries:16;\r
532 UINT64 PageSizeIsOptimized:1;\r
533 UINT64 TcIsUnified:1;\r
534 UINT64 EntriesReduction:1;\r
535} PAL_TC_INFO;\r
536\r
537/**\r
538 PAL Procedure - PAL_VM_INFO.\r
539\r
540 Return detailed information about virtual memory features\r
541 supported in the processor. It is required by IPF. The PAL\r
542 procedure supports the Static Registers calling convention. It\r
543 could be called at physical mode and Virtual mode.\r
544\r
545 @param Index Index of PAL_VM_INFO within the list\r
546 of PAL procedures.\r
547 @param TcLevel Unsigned 64-bit integer specifying the level\r
548 in the TLB hierarchy for which information is\r
549 required. This value must be between 0 and one\r
550 less than the value returned in the\r
551 vm_info_1.num_tc_levels return value from\r
552 PAL_VM_SUMMARY.\r
553 @param TcType Unsigned 64-bit integer with a value of 1 for\r
554 instruction translation cache and 2 for data\r
555 or unified translation cache. All other values\r
556 are reserved.\r
557\r
558 @retval 0 Call completed without error\r
559 @retval -2 Invalid argument\r
560 @retval -3 Call completed with error.\r
561\r
562 @return R9 8-byte formatted value returning information\r
563 about the specified TC. See PAL_TC_INFO above.\r
564 @return R10 64-bit vector containing a bit for each page\r
565 size supported in the specified TC, where bit\r
566 position n indicates a page size of 2**n.\r
567\r
568**/\r
569#define PAL_VM_INFO 7\r
570\r
571\r
572/**\r
573 PAL Procedure - PAL_VM_PAGE_SIZE.\r
574\r
575 Return virtual memory TC and hardware walker page sizes\r
576 supported in the processor. It is required by IPF. The PAL\r
577 procedure supports the Static Registers calling convention. It\r
578 could be called at physical mode and Virtual mode.\r
579\r
580 @param Index Index of PAL_VM_PAGE_SIZE within the list\r
581 of PAL procedures.\r
582\r
583 @retval 0 Call completed without error\r
584 @retval -2 Invalid argument\r
585 @retval -3 Call completed with error.\r
586\r
587 @return R9 64-bit vector containing a bit for each\r
588 architected page size that is supported for\r
589 TLB insertions and region registers.\r
590 @return R10 64-bit vector containing a bit for each\r
591 architected page size supported for TLB purge\r
592 operations.\r
593\r
594**/\r
595#define PAL_VM_PAGE_SIZE 34\r
596\r
597/**\r
598\r
599 @param WalkerPresent 1-bit flag indicating whether a hardware\r
600 TLB walker is implemented (1 = walker\r
601 present).\r
602\r
603 @param WidthOfPhysicalAddress Unsigned 7-bit integer\r
604 denoting the number of bits of\r
605 physical address implemented.\r
606\r
607 @param WidthOfKey Unsigned 8-bit integer denoting the number\r
608 of bits mplemented in the PKR.key field.\r
609\r
610 @param MaxPkrIndex Unsigned 8-bit integer denoting the\r
611 maximum PKR index (number of PKRs-1).\r
612\r
613 @param HashTagId Unsigned 8-bit integer which uniquely\r
614 identifies the processor hash and tag\r
615 algorithm.\r
616\r
617 @param MaxDtrIndex Unsigned 8 bit integer denoting the\r
618 maximum data translation register index\r
619 (number of dtr entries - 1).\r
620\r
621 @param MaxItrIndex Unsigned 8 bit integer denoting the\r
622 maximum instruction translation register\r
623 index (number of itr entries - 1).\r
624\r
625 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the\r
626 number of unique TCs implemented.\r
627 This is a maximum of\r
628 2*num_tc_levels.\r
629\r
630 @param NumberOfTcLevels Unsigned 8-bit integer denoting the\r
631 number of TC levels.\r
632\r
633**/\r
634typedef struct {\r
635 UINT64 WalkerPresent:1;\r
636 UINT64 WidthOfPhysicalAddress: 7;\r
637 UINT64 WidthOfKey:8;\r
638 UINT64 MaxPkrIndex:8;\r
639 UINT64 HashTagId:8;\r
640 UINT64 MaxDtrIndex:8;\r
641 UINT64 MaxItrIndex:8;\r
642 UINT64 NumberOfUniqueTc:8;\r
643 UINT64 NumberOfTcLevels:8;\r
644} PAL_VM_INFO1;\r
645\r
646/**\r
647\r
648 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting\r
649 is the total number of virtual\r
650 address bits - 1.\r
651\r
652 @param WidthOfRid Unsigned 8-bit integer denoting the number\r
653 of bits implemented in the RR.rid field.\r
654\r
655 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the\r
656 maximum number of concurrent outstanding\r
657 TLB purges allowed by the processor. A\r
658 value of 0 indicates one outstanding\r
659 purge allowed. A value of 216-1\r
660 indicates no limit on outstanding\r
661 purges. All other values indicate the\r
662 actual number of concurrent outstanding\r
663 purges allowed.\r
664\r
665**/\r
666typedef struct {\r
667 UINT64 WidthOfVirtualAddress:8;\r
668 UINT64 WidthOfRid:8;\r
669 UINT64 MaxPurgedTlbs:16;\r
670 UINT64 Reserved:32;\r
671} PAL_VM_INFO2;\r
672\r
673/**\r
674 PAL Procedure - PAL_VM_SUMMARY.\r
675\r
676 Return summary information about virtual memory features\r
677 supported in the processor. It is required by IPF. The PAL\r
678 procedure supports the Static Registers calling convention. It\r
679 could be called at physical mode and Virtual mode.\r
680\r
681 @param Index Index of PAL_VM_SUMMARY within the list\r
682 of PAL procedures.\r
683\r
684 @retval 0 Call completed without error\r
685 @retval -2 Invalid argument\r
686 @retval -3 Call completed with error.\r
687\r
688 @return R9 8-byte formatted value returning global virtual\r
689 memory information. See PAL_VM_INFO1 above.\r
690 @return R10 8-byte formatted value returning global virtual\r
691 memory information. See PAL_VM_INFO2 above.\r
692\r
693**/\r
694#define PAL_VM_SUMMARY 8\r
695\r
696\r
697//\r
698// Bit mask of TR_valid flag.\r
699//\r
700#define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0\r
701#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1\r
702#define PAL_TR_DIRTY_IS_VALID BIT2\r
703#define PAL_TR_MEMORY_ATTR_IS_VALID BIT3\r
704\r
705\r
706/**\r
707 PAL Procedure - PAL_VM_TR_READ.\r
708\r
709 Read contents of a translation register. It is required by\r
710 IPF. The PAL procedure supports the Stacked Register calling\r
711 convention. It could be called at physical mode.\r
712\r
713 @param Index Index of PAL_VM_TR_READ within the list\r
714 of PAL procedures.\r
715 @param RegNumber Unsigned 64-bit number denoting which TR to\r
716 read.\r
717 @param TrType Unsigned 64-bit number denoting whether to\r
718 read an ITR (0) or DTR (1). All other values\r
719 are reserved.\r
720 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in\r
721 which translation data is returned.\r
722\r
723 @retval 0 Call completed without error\r
724 @retval -2 Invalid argument\r
725 @retval -3 Call completed with error.\r
726\r
727 @return R9 Formatted bit vector denoting which fields are\r
728 valid. See TR_valid above.\r
729\r
730**/\r
731#define PAL_VM_TR_READ 261\r
732\r
733\r
734\r
735\r
736//\r
737// Bit Mask of Processor Bus Fesatures .\r
738//\r
739\r
740/**\r
741\r
742 When 0, bus data errors are detected and single bit errors are\r
743 corrected. When 1, no error detection or correction is done.\r
744\r
745**/\r
746#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63\r
747\r
748\r
749/**\r
750\r
751 When 0, bus address errors are signalled on the bus. When 1,\r
752 no bus errors are signalled on the bus. If Disable Bus Address\r
753 Error Checking is 1, this bit is ignored.\r
754\r
755**/\r
756#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62\r
757\r
758\r
759\r
760\r
761/**\r
762\r
763 When 0, bus errors are detected, single bit errors are\r
764 corrected., and a CMCI or MCA is generated internally to the\r
765 processor. When 1, no bus address errors are detected or\r
766 corrected.\r
767\r
768**/\r
769#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61\r
770\r
771\r
772/**\r
773\r
774 When 0, bus protocol errors (BINIT#) are signaled by the\r
775 processor on the bus. When 1, bus protocol errors (BINIT#) are\r
776 not signaled on the bus. If Disable Bus Initialization Event\r
777 Checking is 1, this bit is ignored.\r
778\r
779**/\r
780#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60\r
781\r
782\r
783/**\r
784\r
785 When 0, bus protocol errors (BINIT#) are detected and sampled\r
786 and an MCA is generated internally to the processor. When 1,\r
787 the processor will ignore bus protocol error conditions\r
788 (BINIT#).\r
789\r
790**/\r
791#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59\r
792\r
793\r
794\r
795/**\r
796\r
797 When 0, BERR# is signalled if a bus error is detected. When 1,\r
798 bus errors are not signalled on the bus.\r
799\r
800**/\r
801#define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58\r
802\r
803\r
804\r
805\r
806/**\r
807\r
808 When 0, BERR# is signalled when internal processor requestor\r
809 initiated bus errors are detected. When 1, internal requester\r
810 bus errors are not signalled on the bus.\r
811\r
812**/\r
813#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57\r
814\r
815\r
816/**\r
817\r
818 When 0, the processor takes an MCA if BERR# is asserted. When\r
819 1, the processor ignores the BERR# signal.\r
820\r
821**/\r
822#define PAL_BUS_DISABLE_ERROR_CHECK BIT56\r
823\r
824\r
825/**\r
826\r
827 When 0, the processor asserts BINIT# if it detects a parity\r
828 error on the signals which identify the transactions to which\r
829 this is a response. When 1, the processor ignores parity on\r
830 these signals.\r
831\r
832**/\r
833#define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55\r
834\r
835\r
836/**\r
837\r
838 When 0, the in-order transaction queue is limited only by the\r
839 number of hardware entries. When 1, the processor's in-order\r
840 transactions queue is limited to one entry.\r
841\r
842**/\r
843#define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54\r
844\r
845/**\r
846\r
847 Enable a bus cache line replacement transaction when a cache\r
848 line in the exclusive state is replaced from the highest level\r
849 processor cache and is not present in the lower level processor\r
850 caches. When 0, no bus cache line replacement transaction will\r
851 be seen on the bus. When 1, bus cache line replacement\r
852 transactions will be seen on the bus when the above condition is\r
853 detected.\r
854\r
855**/\r
856#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53\r
857\r
858\r
859/**\r
860\r
861 Enable a bus cache line replacement transaction when a cache\r
862 line in the shared or exclusive state is replaced from the\r
863 highest level processor cache and is not present in the lower\r
864 level processor caches.\r
865 When 0, no bus cache line replacement transaction will be seen\r
866 on the bus. When 1, bus cache line replacement transactions\r
867 will be seen on the bus when the above condition is detected.\r
868\r
869**/\r
870#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52\r
871\r
872\r
873\r
874/**\r
875\r
876 When 0, the data bus is configured at the 2x data transfer\r
877 rate.When 1, the data bus is configured at the 1x data\r
878 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the\r
879 processor executes locked transactions atomically. When 1, the\r
880 processor masks the bus lock signal and executes locked\r
881 transactions as a non-atomic series of transactions.\r
882\r
883**/\r
884#define PAL_BUS_ENABLE_HALF_TRANSFER BIT30\r
885\r
886/**\r
887\r
888 When 0, the processor will deassert bus request when finished\r
889 with each transaction. When 1, the processor will continue to\r
890 assert bus request after it has finished, if it was the last\r
891 agent to own the bus and if there are no other pending\r
892 requests.\r
893\r
894**/\r
895#define PAL_BUS_REQUEST_BUS_PARKING BIT29\r
896\r
897\r
898/**\r
899 PAL Procedure - PAL_BUS_GET_FEATURES.\r
900\r
901 Return configurable processor bus interface features and their\r
902 current settings. It is required by IPF. The PAL procedure\r
903 supports the Stacked Register calling convention. It could be\r
904 called at physical mode.\r
905\r
906 @param Index Index of PAL_BUS_GET_FEATURES within the list\r
907 of PAL procedures.\r
908\r
909 @retval 0 Call completed without error\r
910 @retval -2 Invalid argument\r
911 @retval -3 Call completed with error.\r
912\r
913 @return R9 64-bit vector of features implemented.\r
914 (1=implemented, 0=not implemented)\r
915 @return R10 64-bit vector of current feature settings.\r
916 @return R11 64-bit vector of features controllable by\r
917 software. (1=controllable, 0= not controllable)\r
918\r
919**/\r
920#define PAL_BUS_GET_FEATURES 9\r
921\r
922/**\r
923 PAL Procedure - PAL_BUS_SET_FEATURES.\r
924\r
925 Enable or disable configurable features in processor bus\r
926 interface. It is required by IPF. It is required by IPF. The PAL procedure\r
927 supports the Static Registers calling convention. It could be\r
928 called at physical mode.\r
929\r
930 @param Index Index of PAL_BUS_SET_FEATURES within the list\r
931 of PAL procedures.\r
932 @param FeatureSelect 64-bit vector denoting desired state of\r
933 each feature (1=select, 0=non-select).\r
934\r
935 @retval 0 Call completed without error\r
936 @retval -2 Invalid argument\r
937 @retval -3 Call completed with error.\r
938\r
939**/\r
940#define PAL_BUS_SET_FEATURES 10\r
941\r
942\r
943/**\r
944 PAL Procedure - PAL_DEBUG_INFO.\r
945\r
946 Return the number of instruction and data breakpoint\r
947 registers. It is required by IPF. It is required by IPF. The\r
948 PAL procedure supports the Static Registers calling\r
949 convention. It could be called at physical mode and virtual\r
950 mode.\r
951\r
952 @param Index Index of PAL_DEBUG_INFO within the list of PAL\r
953 procedures.\r
954\r
955 @retval 0 Call completed without error\r
956 @retval -2 Invalid argument\r
957 @retval -3 Call completed with error.\r
958\r
959 @return R9 Unsigned 64-bit integer denoting the number of\r
960 pairs of instruction debug registers implemented\r
961 by the processor.\r
962 @return R10 Unsigned 64-bit integer denoting the number of\r
963 pairs of data debug registers implemented by the\r
964 processor.\r
965\r
966**/\r
967#define PAL_DEBUG_INFO 11\r
968\r
969/**\r
970 PAL Procedure - PAL_FIXED_ADDR.\r
971\r
972 Return the fixed component of a processor's directed address.\r
973 It is required by IPF. It is required by IPF. The PAL\r
974 procedure supports the Static Registers calling convention. It\r
975 could be called at physical mode and virtual mode.\r
976\r
977 @param Index Index of PAL_FIXED_ADDR within the list of PAL\r
978 procedures.\r
979\r
980 @retval 0 Call completed without error\r
981 @retval -2 Invalid argument\r
982 @retval -3 Call completed with error.\r
983\r
984 @return R9 Fixed geographical address of this processor.\r
985\r
986**/\r
987#define PAL_FIXED_ADDR 12\r
988\r
989/**\r
990 PAL Procedure - PAL_FREQ_BASE.\r
991\r
992 Return the frequency of the output clock for use by the\r
993 platform, if generated by the processor. It is optinal. The\r
994 PAL procedure supports the Static Registers calling\r
995 convention. It could be called at physical mode and virtual\r
996 mode.\r
997\r
998 @param Index Index of PAL_FREQ_BASE within the list of PAL\r
999 procedures.\r
1000\r
1001 @retval 0 Call completed without error\r
1002 @retval -1 Unimplemented procedure\r
1003 @retval -2 Invalid argument\r
1004 @retval -3 Call completed with error.\r
1005\r
1006 @return R9 Base frequency of the platform if generated by the\r
1007 processor chip.\r
1008\r
1009**/\r
1010#define PAL_FREQ_BASE 13\r
1011\r
1012\r
1013/**\r
1014 PAL Procedure - PAL_FREQ_RATIOS.\r
1015\r
1016 Return ratio of processor, bus, and interval time counter to\r
1017 processor input clock or output clock for platform use, if\r
1018 generated by the processor. It is required by IPF. The PAL\r
1019 procedure supports the Static Registers calling convention. It\r
1020 could be called at physical mode and virtual mode.\r
1021\r
1022 @param Index Index of PAL_FREQ_RATIOS within the list of PAL\r
1023 procedures.\r
1024\r
1025 @retval 0 Call completed without error\r
1026 @retval -2 Invalid argument\r
1027 @retval -3 Call completed with error.\r
1028\r
1029 @return R9 Ratio of the processor frequency to the input\r
1030 clock of the processor, if the platform clock is\r
1031 generated externally or to the output clock to the\r
1032 platform, if the platform clock is generated by\r
1033 the processor.\r
1034 @return R10 Ratio of the bus frequency to the input clock of\r
1035 the processor, if the platform clock is generated\r
1036 externally or to the output clock to the platform,\r
1037 if the platform clock is generated by the\r
1038 processor.\r
1039 @return R11 Ratio of the interval timer counter rate to input\r
1040 clock of the processor, if the platform clock is\r
1041 generated externally or to the output clock to the\r
1042 platform, if the platform clock is generated by\r
1043 the processor.\r
1044\r
1045**/\r
1046#define PAL_FREQ_RATIOS 14\r
1047\r
1048/**\r
1049\r
1050 @param NumberOfLogicalProcessors Total number of logical\r
1051 processors on this physical\r
1052 processor package that are\r
1053 enabled.\r
1054\r
1055 @param ThreadsPerCore Number of threads per core.\r
1056\r
1057 @param CoresPerProcessor Total number of cores on this\r
1058 physical processor package.\r
1059\r
1060 @param PhysicalProcessorPackageId Physical processor package\r
1061 identifier which was\r
1062 assigned at reset by the\r
1063 platform or bus\r
1064 controller. This value may\r
1065 or may not be unique\r
1066 across the entire platform\r
1067 since it depends on the\r
1068 platform vendor's policy.\r
1069**/\r
1070typedef struct {\r
1071 UINT64 NumberOfLogicalProcessors:16;\r
1072 UINT64 ThreadsPerCore:8;\r
1073 UINT64 Reserved1:8;\r
1074 UINT64 CoresPerProcessor;\r
1075 UINT64 Reserved2:8;\r
1076 UINT64 PhysicalProcessorPackageId:8;\r
1077 UINT64 Reserved3:8;\r
1078} PAL_LOGICAL_PROCESSPR_OVERVIEW;\r
1079\r
1080/**\r
1081\r
1082 @param ThreadId The thread identifier of the logical\r
1083 processor for which information is being\r
1084 returned. This value will be unique on a per\r
1085 core basis.\r
1086\r
1087 @param CoreId The core identifier of the logical processor\r
1088 for which information is being returned.\r
1089 This value will be unique on a per physical\r
1090 processor package basis.\r
1091\r
1092**/\r
1093typedef struct {\r
1094 UINT64 ThreadId:16;\r
1095 UINT64 Reserved1:16;\r
1096 UINT64 CoreId:16;\r
1097 UINT64 Reserved2:16;\r
1098} PAL_LOGICAL_PROCESSORN_INFO1;\r
1099\r
1100\r
1101/**\r
1102\r
1103 @param LogicalAddress Geographical address of the logical\r
1104 processor for which information is being\r
1105 returned. This is the same value that is\r
1106 returned by the PAL_FIXED_ADDR procedure\r
1107 when it is called on the logical\r
1108 processor.\r
1109\r
1110\r
1111**/\r
1112typedef struct {\r
1113 UINT64 LogicalAddress:16;\r
1114 UINT64 Reserved:48;\r
1115} PAL_LOGICAL_PROCESSORN_INFO2;\r
1116\r
1117/**\r
1118 PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.\r
1119\r
1120 Return information on which logical processors map to a\r
1121 physical processor die. It is optinal. The PAL procedure\r
1122 supports the Static Registers calling convention. It could be\r
1123 called at physical mode and virtual mode.\r
1124\r
1125 @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL\r
1126 procedures.\r
1127 @param ProcessorNumber Signed 64-bit integer that specifies\r
1128 for which logical processor\r
1129 information is being requested. When\r
1130 this input argument is -1, information\r
1131 is returned about the logical\r
1132 processor on which the procedure call\r
1133 is made. This input argument must be\r
1134 in the range of 1 up to one less than\r
1135 the number of logical processors\r
1136 returned by num_log in the\r
1137 log_overview return value.\r
1138\r
1139 @retval 0 Call completed without error\r
1140 @retval -1 Unimplemented procedure\r
1141 @retval -2 Invalid argument\r
1142 @retval -3 Call completed with error.\r
1143\r
1144 @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.\r
1145 @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.\r
1146 @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.\r
1147\r
1148**/\r
1149#define PAL_LOGICAL_TO_PHYSICAL 42\r
1150\r
1151\r
1152/**\r
1153\r
1154 @param NumberOfPmcPairs Unsigned 8-bit number defining the\r
1155 number of generic PMC/PMD pairs.\r
1156\r
1157 @param WidthOfCounter Unsigned 8-bit number in the range\r
1158 0:60 defining the number of\r
1159 implemented counter bits.\r
1160\r
1161 @param TypeOfCycleCounting Unsigned 8-bit number defining the\r
1162 event type for counting processor\r
1163 cycles.\r
1164\r
1165\r
1166 @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit\r
1167 number defining the\r
1168 event type for retired\r
1169 instruction bundles.\r
1170\r
1171**/\r
1172typedef struct {\r
1173 UINT64 NumberOfPmcPairs:8;\r
1174 UINT64 WidthOfCounter:8;\r
1175 UINT64 TypeOfCycleCounting:8;\r
1176 UINT64 TypeOfRetiredInstructionBundle:8;\r
1177 UINT64 Reserved:32;\r
1178} PAL_PERFORMANCE_INFO;\r
1179\r
1180/**\r
1181 PAL Procedure - PAL_PERF_MON_INFO.\r
1182\r
1183 Return the number and type of performance monitors. It is\r
1184 required by IPF. The PAL procedure supports the Static\r
1185 Registers calling convention. It could be called at physical\r
1186 mode and virtual mode.\r
1187\r
1188 @param Index Index of PAL_PERF_MON_INFO within the list of\r
1189 PAL procedures.\r
1190 @param PerformanceBuffer An address to an 8-byte aligned\r
1191 128-byte memory buffer.\r
1192\r
1193 @retval 0 Call completed without error\r
1194 @retval -2 Invalid argument\r
1195 @retval -3 Call completed with error.\r
1196\r
1197 @return R9 Information about the performance monitors\r
1198 implemented. See PAL_PERFORMANCE_INFO;\r
1199\r
1200**/\r
1201#define PAL_PERF_MON_INFO 15\r
1202\r
1203#define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0\r
1204#define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1\r
1205\r
1206/**\r
1207 PAL Procedure - PAL_PLATFORM_ADDR.\r
1208\r
1209 Specify processor interrupt block address and I/O port space\r
1210 address. It is required by IPF. The PAL procedure supports the\r
1211 Static Registers calling convention. It could be called at\r
1212 physical mode and virtual mode.\r
1213\r
1214 @param Index Index of PAL_PLATFORM_ADDR within the list of\r
1215 PAL procedures.\r
1216 @param Type Unsigned 64-bit integer specifying the type of\r
1217 block. 0 indicates that the processor interrupt\r
1218 block pointer should be initialized. 1 indicates\r
1219 that the processor I/O block pointer should be\r
1220 initialized.\r
1221 @param Address Unsigned 64-bit integer specifying the address\r
1222 to which the processor I/O block or interrupt\r
1223 block shall be set. The address must specify\r
1224 an implemented physical address on the\r
1225 processor model, bit 63 is ignored.\r
1226\r
1227 @retval 0 Call completed without error\r
1228 @retval -1 Unimplemented procedure.\r
1229 @retval -2 Invalid argument\r
1230 @retval -3 Call completed with error.\r
1231\r
1232**/\r
1233#define PAL_PLATFORM_ADDR 16\r
1234\r
1235\r
1236/**\r
1237\r
1238 @param EnableBerrPromotion Bit63. Enable BERR promotion. When\r
1239 1, the Bus Error (BERR) signal is\r
1240 promoted to the Bus Initialization\r
1241 (BINIT) signal, and the BINIT pin\r
1242 is asserted on the occurrence of\r
1243 each Bus Error. Setting this bit\r
1244 has no effect if BINIT signalling\r
1245 is disabled. (See\r
1246 PAL_BUS_GET/SET_FEATURES)\r
1247\r
1248 @param EnableMcaPromotion Bit62, Enable MCA promotion. When\r
1249 1, machine check aborts (MCAs) are\r
1250 promoted to the Bus Error signal,\r
1251 and the BERR pin is assert on each\r
1252 occurrence of an MCA. Setting this\r
1253 bit has no effect if BERR\r
1254 signalling is disabled. (See\r
1255 PAL_BUS_GET/SET_FEATURES)\r
1256\r
1257 @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT\r
1258 promotion. When 1, machine\r
1259 check aborts (MCAs) are\r
1260 promoted to the Bus\r
1261 Initialization signal, and\r
1262 the BINIT pin is assert on\r
1263 each occurrence of an MCA.\r
1264 Setting this bit has no\r
1265 effect if BINIT signalling\r
1266 is disabled. (See\r
1267 PAL_BUS_GET/SET_FEATURES)\r
1268\r
1269 @param EnableCmciPromotion Bit60, Enable CMCI promotion When\r
1270 1, Corrected Machine Check\r
1271 Interrupts (CMCI) are promoted to\r
1272 MCAs. They are also further\r
1273 promoted to BERR if bit 39, Enable\r
1274 MCA promotion, is also set and\r
1275 they are promoted to BINIT if bit\r
1276 38, Enable MCA to BINIT promotion,\r
1277 is also set. This bit has no\r
1278 effect if MCA signalling is\r
1279 disabled (see\r
1280 PAL_BUS_GET/SET_FEATURES)\r
1281\r
1282 @param DisableCache Bit59, Disable Cache. When 0, the\r
1283 processor performs cast outs on\r
1284 cacheable pages and issues and responds\r
1285 to coherency requests normally. When 1,\r
1286 the processor performs a memory access\r
1287 for each reference regardless of cache\r
1288 contents and issues no coherence\r
1289 requests and responds as if the line\r
1290 were not present. Cache contents cannot\r
1291 be relied upon when the cache is\r
1292 disabled. WARNING: Semaphore\r
1293 instructions may not be atomic or may\r
1294 cause Unsupported Data Reference faults\r
1295 if caches are disabled.\r
1296\r
1297 @param DisableCoherency Bit58, Disable Coherency. When 0,\r
1298 the processor uses normal coherency\r
1299 requests and responses. When 1, the\r
1300 processor answers all requests as if\r
1301 the line were not present.\r
1302\r
1303 @param DisableDPM Bit57, Disable Dynamic Power Management\r
1304 (DPM). When 0, the hardware may reduce\r
1305 power consumption by removing the clock\r
1306 input from idle functional units. When 1,\r
1307 all functional units will receive clock\r
1308 input, even when idle.\r
1309\r
1310 @param DisableBinitWithTimeout Bit56, Disable a BINIT on\r
1311 internal processor time-out.\r
1312 When 0, the processor may\r
1313 generate a BINIT on an\r
1314 internal processor time-out.\r
1315 When 1, the processor will not\r
1316 generate a BINIT on an\r
1317 internal processor time-out.\r
1318 The event is silently ignored.\r
1319\r
1320\r
1321 @param EnableEnvNotification Bit55, Enable external\r
1322 notification when the processor\r
1323 detects hardware errors caused\r
1324 by environmental factors that\r
1325 could cause loss of\r
1326 deterministic behavior of the\r
1327 processor. When 1, this bit will\r
1328 enable external notification,\r
1329 when 0 external notification is\r
1330 not provided. The type of\r
1331 external notification of these\r
1332 errors is processor-dependent. A\r
1333 loss of processor deterministic\r
1334 behavior is considered to have\r
1335 occurred if these\r
1336 environmentally induced errors\r
1337 cause the processor to deviate\r
1338 from its normal execution and\r
1339 eventually causes different\r
1340 behavior which can be observed\r
1341 at the processor bus pins.\r
1342 Processor errors that do not\r
1343 have this effects (i.e.,\r
1344 software induced machine checks)\r
1345 may or may not be promoted\r
1346 depending on the processor\r
1347 implementation.\r
1348\r
1349 @param EnableVmsw Bit54, Enable the use of the vmsw\r
1350 instruction. When 0, the vmsw instruction\r
1351 causes a Virtualization fault when\r
1352 executed at the most privileged level.\r
1353 When 1, this bit will enable normal\r
1354 operation of the vmsw instruction.\r
1355\r
1356 @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling\r
1357 on data-poisoning event\r
1358 detection. When 0, a CMCI\r
1359 will be signaled on error\r
1360 detection. When 1, an MCA\r
1361 will be signaled on error\r
1362 detection. If this feature\r
1363 is not supported, then the\r
1364 corresponding argument is\r
1365 ignored when calling\r
1366 PAL_PROC_SET_FEATURES. Note\r
1367 that the functionality of\r
1368 this bit is independent of\r
1369 the setting in bit 60\r
1370 (Enable CMCI promotion), and\r
1371 that the bit 60 setting does\r
1372 not affect CMCI signaling\r
1373 for data-poisoning related\r
1374 events. Volume 2: Processor\r
1375 Abstraction Layer 2:431\r
1376 PAL_PROC_GET_FEATURES\r
1377\r
1378 @param DisablePState Bit52, Disable P-states. When 1, the PAL\r
1379 P-state procedures (PAL_PSTATE_INFO,\r
1380 PAL_SET_PSTATE, PAL_GET_PSTATE) will\r
1381 return with a status of -1\r
1382 (Unimplemented procedure).\r
1383\r
1384 @param DisableBranchPrediction Bit47, Disable Dynamic branch\r
1385 prediction. When 0, the\r
1386 processor may predict branch\r
1387 targets and speculatively\r
1388 execute, but may not commit\r
1389 results. When 1, the processor\r
1390 must wait until branch targets\r
1391 are known to execute.\r
1392\r
1393 @param DisableDynamicInsCachePrefetch Bit46, Disable\r
1394 DynamicInstruction Cache\r
1395 Prefetch. When 0, the\r
1396 processor may prefetch\r
1397 into the caches any\r
1398 instruction which has\r
1399 not been executed, but\r
1400 whose execution is\r
1401 likely. When 1,\r
1402 instructions may not be\r
1403 fetched until needed or\r
1404 hinted for execution.\r
1405 (Prefetch for a hinted\r
1406 branch is allowed even\r
1407 when dynamic instruction\r
1408 cache prefetch is\r
1409 disabled.)\r
1410\r
1411 @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic\r
1412 Data Cache Prefetch.\r
1413 When 0, the processor\r
1414 may prefetch into the\r
1415 caches any data which\r
1416 has not been accessed\r
1417 by instruction\r
1418 execution, but which\r
1419 is likely to be\r
1420 accessed. When 1, no\r
1421 data may be fetched\r
1422 until it is needed for\r
1423 instruction execution\r
1424 or is fetched by an\r
1425 lfetch instruction.\r
1426\r
1427 @param DisableSpontaneousDeferral Bit44, Disable Spontaneous\r
1428 Deferral. When 1, the\r
1429 processor may optionally\r
1430 defer speculative loads\r
1431 that do not encounter any\r
1432 exception conditions, but\r
1433 that trigger other\r
1434 implementation-dependent\r
1435 conditions (e.g., cache\r
1436 miss). When 0, spontaneous\r
1437 deferral is disabled.\r
1438\r
1439 @param DisableDynamicPrediction Bit43, Disable Dynamic\r
1440 Predicate Prediction. When\r
1441 0, the processor may predict\r
1442 predicate results and\r
1443 execute speculatively, but\r
1444 may not commit results until\r
1445 the actual predicates are\r
1446 known. When 1, the processor\r
1447 shall not execute predicated\r
1448 instructions until the\r
1449 actual predicates are known.\r
1450\r
1451 @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.\r
1452 Denotes whether XR1 XR3 are\r
1453 implemented for machine check\r
1454 recovery. This feature may only be\r
1455 interrogated by PAL_PROC_GET_FEATURES.\r
1456 It may not be enabled or disabled by\r
1457 PAL_PROC_SET_FEATURES. The\r
1458 corresponding argument is ignored.\r
1459\r
1460 @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS\r
1461 implemented. Denotes whether XIP, XPSR,\r
1462 and XFS are implemented for machine\r
1463 check recovery. This feature may only be\r
1464 interrogated by PAL_PROC_GET_FEATURES.\r
1465 It may not be enabled or disabled by\r
1466 PAL_PROC_SET_FEATURES. The corresponding\r
1467 argument is ignored.\r
1468\r
1469 @param NoVM Bit40, No Virtual Machine features implemented.\r
1470 Denotes whether PSR.vm is implemented. This\r
1471 feature may only be interrogated by\r
1472 PAL_PROC_GET_FEATURES. It may not be enabled or\r
1473 disabled by PAL_PROC_SET_FEATURES. The\r
1474 corresponding argument is ignored.\r
1475\r
1476 @param NoVariablePState Bit39, No Variable P-state\r
1477 performance: A value of 1, indicates\r
1478 that a processor implements\r
1479 techniques to optimize performance\r
1480 for the given P-state power budget\r
1481 by dynamically varying the\r
1482 frequency, such that maximum\r
1483 performance is achieved for the\r
1484 power budget. A value of 0,\r
1485 indicates that P-states have no\r
1486 frequency variation or very small\r
1487 frequency variations for their given\r
1488 power budget. This feature may only\r
1489 be interrogated by\r
1490 PAL_PROC_GET_FEATURES. it may not be\r
1491 enabled or disabled by\r
1492 PAL_PROC_SET_FEATURES. The\r
1493 corresponding argument is ignored.\r
1494\r
1495\r
1496 @param NoSimpleImpInUndefinedIns Bit38, No Simple\r
1497 implementation of\r
1498 unimplemented instruction\r
1499 addresses. Denotes how an\r
1500 unimplemented instruction\r
1501 address is recorded in IIP\r
1502 on an Unimplemented\r
1503 Instruction Address trap or\r
1504 fault. When 1, the full\r
1505 unimplemented address is\r
1506 recorded in IIP; when 0, the\r
1507 address is sign extended\r
1508 (virtual addresses) or zero\r
1509 extended (physical\r
1510 addresses). This feature may\r
1511 only be interrogated by\r
1512 PAL_PROC_GET_FEATURES. It\r
1513 may not be enabled or\r
1514 disabled by\r
1515 PAL_PROC_SET_FEATURES. The\r
1516 corresponding argument is\r
1517 ignored.\r
1518\r
1519 @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins\r
1520 present. Denotes the absence of INIT,\r
1521 PMI, LINT0 and LINT1 pins on the\r
1522 processor. When 1, the pins are absent.\r
1523 When 0, the pins are present. This\r
1524 feature may only be interrogated by\r
1525 PAL_PROC_GET_FEATURES. It may not be\r
1526 enabled or disabled by\r
1527 PAL_PROC_SET_FEATURES. The corresponding\r
1528 argument is ignored.\r
1529\r
1530 @param FaultInUndefinedIns Bit36, No Unimplemented\r
1531 instruction address reported as\r
1532 fault. Denotes how the processor\r
1533 reports the detection of\r
1534 unimplemented instruction\r
1535 addresses. When 1, the processor\r
1536 reports an Unimplemented\r
1537 Instruction Address fault on the\r
1538 unimplemented address; when 0, it\r
1539 reports an Unimplemented\r
1540 Instruction Address trap on the\r
1541 previous instruction in program\r
1542 order. This feature may only be\r
1543 interrogated by\r
1544 PAL_PROC_GET_FEATURES. It may not\r
1545 be enabled or disabled by\r
1546 PAL_PROC_SET_FEATURES. The\r
1547 corresponding argument is\r
1548 ignored.\r
1549\r
1550**/\r
1551typedef struct {\r
1552 UINT64 Reserved1:36;\r
1553 UINT64 FaultInUndefinedIns:1;\r
1554 UINT64 NoPresentPmi:1;\r
1555 UINT64 NoSimpleImpInUndefinedIns:1;\r
1556 UINT64 NoVariablePState:1;\r
1557 UINT64 NoVM:1;\r
1558 UINT64 NoXipXpsrXfs:1;\r
1559 UINT64 NoXr1ThroughXr3:1;\r
1560 UINT64 DisableDynamicPrediction:1;\r
1561 UINT64 DisableSpontaneousDeferral:1;\r
1562 UINT64 DisableDynamicDataCachePrefetch:1;\r
1563 UINT64 DisableDynamicInsCachePrefetch:1;\r
1564 UINT64 DisableBranchPrediction:1;\r
1565 UINT64 Reserved2:4;\r
1566 UINT64 DisablePState:1;\r
1567 UINT64 EnableMcaOnDataPoisoning:1;\r
1568 UINT64 EnableVmsw:1;\r
1569 UINT64 EnableEnvNotification:1;\r
1570 UINT64 DisableBinitWithTimeout:1;\r
1571 UINT64 DisableDPM:1;\r
1572 UINT64 DisableCoherency:1;\r
1573 UINT64 DisableCache:1;\r
1574 UINT64 EnableCmciPromotion:1;\r
1575 UINT64 EnableMcaToBinitPromotion:1;\r
1576 UINT64 EnableMcaPromotion:1;\r
1577 UINT64 EnableBerrPromotion:1;\r
1578} PAL_PROCESSOR_FEATURES;\r
1579\r
1580/**\r
1581 PAL Procedure - PAL_PROC_GET_FEATURES.\r
1582\r
1583 Return configurable processor features and their current\r
1584 setting. It is required by IPF. The PAL procedure supports the\r
1585 Static Registers calling convention. It could be called at\r
1586 physical mode and virtual mode.\r
1587\r
1588 @param Index Index of PAL_PROC_GET_FEATURES within the list of\r
1589 PAL procedures.\r
1590 @param Reserved Reserved parameter.\r
1591 @param FeatureSet Feature set information is being requested\r
1592 for.\r
1593\r
1594 @retval 1 Call completed without error; The\r
1595 feature_set passed is not supported but a\r
1596 feature_set of a larger value is supported.\r
1597 @retval 0 Call completed without error\r
1598 @retval -2 Invalid argument\r
1599 @retval -3 Call completed with error.\r
1600 @retval -8 feature_set passed is beyond the maximum\r
1601 feature_set supported\r
1602\r
1603 @return R9 64-bit vector of features implemented. See\r
1604 PAL_PROCESSOR_FEATURES.\r
1605 @return R10 64-bit vector of current feature settings. See\r
1606 PAL_PROCESSOR_FEATURES.\r
1607 @return R11 64-bit vector of features controllable by\r
1608 software.\r
1609\r
1610**/\r
1611#define PAL_PROC_GET_FEATURES 17\r
1612\r
1613\r
1614/**\r
1615 PAL Procedure - PAL_PROC_SET_FEATURES.\r
1616\r
1617 Enable or disable configurable processor features. It is\r
1618 required by IPF. The PAL procedure supports the Static\r
1619 Registers calling convention. It could be called at physical\r
1620 mode.\r
1621\r
1622 @param Index Index of PAL_PROC_SET_FEATURES within the list of\r
1623 PAL procedures.\r
1624 @param FeatureSelect 64-bit vector denoting desired state of\r
1625 each feature (1=select, 0=non-select).\r
1626 @param FeatureSet Feature set to apply changes to. See\r
1627 PAL_PROC_GET_FEATURES for more information\r
1628 on feature sets.\r
1629\r
1630 @retval 1 Call completed without error; The\r
1631 feature_set passed is not supported but a\r
1632 feature_set of a larger value is supported\r
1633 @retval 0 Call completed without error\r
1634 @retval -2 Invalid argument\r
1635 @retval -3 Call completed with error.\r
1636 @retval -8 feature_set passed is beyond the maximum\r
1637 feature_set supported\r
1638\r
1639**/\r
1640#define PAL_PROC_SET_FEATURES 18\r
1641\r
1642\r
1643//\r
1644// Value of PAL_REGISTER_INFO.InfoRequest.\r
1645//\r
1646#define PAL_APPLICATION_REGISTER_IMPLEMENTED 0\r
1647#define PAL_APPLICATION_REGISTER_READABLE 1\r
1648#define PAL_CONTROL_REGISTER_IMPLEMENTED 2\r
1649#define PAL_CONTROL_REGISTER_READABLE 3\r
1650\r
1651\r
1652/**\r
1653 PAL Procedure - PAL_REGISTER_INFO.\r
1654\r
1655 Return AR and CR register information. It is required by IPF.\r
1656 The PAL procedure supports the Static Registers calling\r
1657 convention. It could be called at physical mode and virtual\r
1658 mode.\r
1659\r
1660 @param Index Index of PAL_REGISTER_INFO within the list of\r
1661 PAL procedures.\r
1662 @param InfoRequest Unsigned 64-bit integer denoting what\r
1663 register information is requested. See\r
1664 PAL_REGISTER_INFO.InfoRequest above.\r
1665\r
1666 @retval 0 Call completed without error\r
1667 @retval -2 Invalid argument\r
1668 @retval -3 Call completed with error.\r
1669\r
1670 @return R9 64-bit vector denoting information for registers\r
1671 0-63. Bit 0 is register 0, bit 63 is register 63.\r
1672 @return R10 64-bit vector denoting information for registers\r
1673 64-127. Bit 0 is register 64, bit 63 is register\r
1674 127.\r
1675\r
1676**/\r
1677#define PAL_REGISTER_INFO 39\r
1678\r
1679/**\r
1680 PAL Procedure - PAL_RSE_INFO.\r
1681\r
1682 Return RSE information. It is required by IPF. The PAL\r
1683 procedure supports the Static Registers calling convention. It\r
1684 could be called at physical mode and virtual mode.\r
1685\r
1686 @param Index Index of PAL_RSE_INFO within the list of\r
1687 PAL procedures.\r
1688 @param InfoRequest Unsigned 64-bit integer denoting what\r
1689 register information is requested. See\r
1690 PAL_REGISTER_INFO.InfoRequest above.\r
1691\r
1692 @retval 0 Call completed without error\r
1693 @retval -2 Invalid argument\r
1694 @retval -3 Call completed with error.\r
1695\r
1696 @return R9 Number of physical stacked general registers.\r
1697 @return R10 RSE hints supported by processor.\r
1698\r
1699**/\r
1700#define PAL_RSE_INFO 19\r
1701\r
1702/**\r
1703\r
1704 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)\r
1705 number that provides identification\r
1706 information about the PAL_B firmware.\r
1707\r
1708 @param PalVendor Is an unsigned 8-bit integer indicating the\r
1709 vendor of the PAL code.\r
1710\r
1711 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)\r
1712 number that provides identification\r
1713 information about the PAL_A firmware. In\r
1714 the split PAL_A model, this return value\r
1715 is the version number of the\r
1716 processor-specific PAL_A. The generic\r
1717 PAL_A version is not returned by this\r
1718 procedure in the split PAL_A model.\r
1719\r
1720**/\r
1721typedef struct {\r
1722 UINT64 VersionOfPalB:16;\r
1723 UINT64 Reserved1:8;\r
1724 UINT64 PalVendor:8;\r
1725 UINT64 VersionOfPalA:16;\r
1726 UINT64 Reserved2:16;\r
1727} PAL_VERSION_INFO;\r
1728\r
1729/**\r
1730 PAL Procedure - PAL_VERSION.\r
1731\r
1732 Return version of PAL code. It is required by IPF. The PAL\r
1733 procedure supports the Static Registers calling convention. It\r
1734 could be called at physical mode and virtual mode.\r
1735\r
1736 @param Index Index of PAL_VERSION within the list of\r
1737 PAL procedures.\r
1738 @param InfoRequest Unsigned 64-bit integer denoting what\r
1739 register information is requested. See\r
1740 PAL_REGISTER_INFO.InfoRequest above.\r
1741\r
1742 @retval 0 Call completed without error\r
1743 @retval -2 Invalid argument\r
1744 @retval -3 Call completed with error.\r
1745\r
1746 @return R9 8-byte formatted value returning the minimum PAL\r
1747 version needed for proper operation of the\r
1748 processor. See PAL_VERSION_INFO above.\r
1749 @return R10 8-byte formatted value returning the current PAL\r
1750 version running on the processor. See\r
1751 PAL_VERSION_INFO above.\r
1752\r
1753**/\r
1754#define PAL_VERSION 20\r
1755\r
1756\r
1757\r
1758//\r
1759// Vectors of PAL_MC_CLEAR_LOG.pending\r
1760//\r
1761#define PAL_MC_PENDING BIT0\r
1762#define PAL_INIT_PENDING BIT1\r
1763\r
1764/**\r
1765 PAL Procedure - PAL_MC_CLEAR_LOG.\r
1766\r
1767 Clear all error information from processor error logging\r
1768 registers. It is required by IPF. The PAL procedure supports\r
1769 the Static Registers calling convention. It could be called at\r
1770 physical mode and virtual mode.\r
1771\r
1772 @param Index Index of PAL_MC_CLEAR_LOG within the list of\r
1773 PAL procedures.\r
1774\r
1775 @retval 0 Call completed without error\r
1776 @retval -2 Invalid argument\r
1777 @retval -3 Call completed with error.\r
1778\r
1779 @return R9 64-bit vector denoting whether an event is\r
1780 pending. See PAL_MC_CLEAR_LOG.pending above.\r
1781\r
1782**/\r
1783#define PAL_MC_CLEAR_LOG 21\r
1784\r
1785/**\r
1786 PAL Procedure - PAL_MC_DRAIN.\r
1787\r
1788 Ensure that all operations that could cause an MCA have\r
1789 completed. It is required by IPF. The PAL procedure supports\r
1790 the Static Registers calling convention. It could be called at\r
1791 physical mode and virtual mode.\r
1792\r
1793 @param Index Index of PAL_MC_DRAIN within the list of PAL\r
1794 procedures.\r
1795\r
1796 @retval 0 Call completed without error\r
1797 @retval -2 Invalid argument\r
1798 @retval -3 Call completed with error.\r
1799\r
1800**/\r
1801#define PAL_MC_DRAIN 22\r
1802\r
1803\r
1804/**\r
1805 PAL Procedure - PAL_MC_DYNAMIC_STATE.\r
1806\r
1807 Return Processor Dynamic State for logging by SAL. It is\r
1808 optional. The PAL procedure supports the Static Registers\r
1809 calling convention. It could be called at physical mode.\r
1810\r
1811 @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL\r
1812 procedures.\r
1813 @param Offset Offset of the next 8 bytes of Dynamic Processor\r
1814 State to return. (multiple of 8).\r
1815\r
1816 @retval 0 Call completed without error\r
1817 @retval -1 Unimplemented procedure.\r
1818 @retval -2 Invalid argument\r
1819 @retval -3 Call completed with error.\r
1820\r
1821 @return R9 Unsigned 64-bit integer denoting bytes of Dynamic\r
1822 Processor State returned.\r
1823 @return R10 Next 8 bytes of Dynamic Processor State.\r
1824\r
1825**/\r
1826#define PAL_MC_DYNAMIC_STATE 24\r
1827\r
1828\r
1829\r
1830//\r
1831// Values of PAL_MC_ERROR_INFO.InfoIndex.\r
1832//\r
1833#define PAL_PROCESSOR_ERROR_MAP 0\r
1834#define PAL_PROCESSOR_STATE_PARAM 1\r
1835#define PAL_STRUCTURE_SPECIFIC_ERROR 2\r
1836\r
1837/**\r
1838\r
1839 @param CoreId Bit3:0, Processor core ID (default is 0 for\r
1840 processors with a single core)\r
1841\r
1842 @param ThreadId Bit7:4, Logical thread ID (default is 0 for\r
1843 processors that execute a single thread)\r
1844\r
1845 @param InfoOfInsCache Bit11:8, Error information is\r
1846 available for 1st, 2nd, 3rd, and 4th\r
1847 level instruction caches.\r
1848\r
1849 @param InfoOfDataCache Bit15:12, Error information is\r
1850 available for 1st, 2nd, 3rd, and 4th\r
1851 level data/unified caches.\r
1852\r
1853 @param InfoOfInsTlb Bit19:16 Error information is available\r
1854 for 1st, 2nd, 3rd, and 4th level\r
1855 instruction TLB.\r
1856\r
1857 @param InfoOfDataTlb Bit23:20, Error information is available\r
1858 for 1st, 2nd, 3rd, and 4th level\r
1859 data/unified TLB\r
1860\r
1861 @param InfoOfProcessorBus Bit27:24 Error information is\r
1862 available for the 1st, 2nd, 3rd,\r
1863 and 4th level processor bus\r
1864 hierarchy.\r
1865\r
1866 @param InfoOfRegisterFile Bit31:28 Error information is\r
1867 available on register file\r
1868 structures.\r
1869\r
1870 @param InfoOfMicroArch Bit47:32, Error information is\r
1871 available on micro-architectural\r
1872 structures.\r
1873\r
1874**/\r
1875typedef struct {\r
1876 UINT64 CoreId:4;\r
1877 UINT64 ThreadId:4;\r
1878 UINT64 InfoOfInsCache:4;\r
1879 UINT64 InfoOfDataCache:4;\r
1880 UINT64 InfoOfInsTlb:4;\r
1881 UINT64 InfoOfDataTlb:4;\r
1882 UINT64 InfoOfProcessorBus:4;\r
1883 UINT64 InfoOfRegisterFile:4;\r
1884 UINT64 InfoOfMicroArch:4;\r
1885 UINT64 Reserved:16;\r
1886} PAL_MC_ERROR_INFO_LEVEL_INDEX;\r
1887\r
1888//\r
1889// Value of PAL_MC_ERROR_INFO.ErrorTypeIndex\r
1890//\r
1891#define PAL_ERR_INFO_BY_LEVEL_INDEX 0\r
1892#define PAL_ERR_INFO_TARGET_ADDRESS 1\r
1893#define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2\r
1894#define PAL_ERR_INFO_REPONSER_INDENTIFIER 3\r
1895#define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4\r
1896\r
1897/**\r
1898\r
1899 @param Operation Bit3:0, Type of cache operation that caused\r
1900 the machine check: 0 - unknown or internal\r
1901 error 1 - load 2 - store 3 - instruction\r
1902 fetch or instruction prefetch 4 - data\r
1903 prefetch (both hardware and software) 5 -\r
1904 snoop (coherency check) 6 - cast out\r
1905 (explicit or implicit write-back of a cache\r
1906 line) 7 - move in (cache line fill)\r
1907\r
1908 @param FailedCacheLevel Bit5:4 Level of cache where the\r
1909 error occurred. A value of 0\r
1910 indicates the first level of cache.\r
1911\r
1912 @param FailedInDataPart Bit8, Failure located in the data\r
1913 part of the cache line.\r
1914\r
1915 @param FailedInTagPart Bit9, Failure located in the tag part\r
1916 of the cache line.\r
1917\r
1918 @param FailedInDataCache Bit10, Failure located in the data\r
1919 cache\r
1920\r
1921 @param FailedInInsCache Bit11, Failure located in the\r
1922 instruction cache.\r
1923\r
1924\r
1925 @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache\r
1926 line is held shared. 2 - cache line is held\r
1927 exclusive. 3 - cache line is modified. All other\r
1928 values are reserved.\r
1929\r
1930 @param MesiIsValid Bit15, The mesi field in the cache_check\r
1931 parameter is valid.\r
1932\r
1933 @param FailedWay Bit20:16, Failure located in the way of\r
1934 the cache indicated by this value.\r
1935\r
1936 @param WayIndexIsValid Bit21, The way and index field in the\r
1937 cache_check parameter is valid.\r
1938\r
1939 @param MultipleBitsError Bit23, A multiple-bit error was\r
1940 detected, and data was poisoned for\r
1941 the corresponding cache line during\r
1942 castout.\r
1943\r
1944 @param IndexOfCacheLineError Bit51:32, Index of the cache\r
1945 line where the error occurred.\r
1946\r
1947 @param InstructionSet Bit54, Instruction set. If this value\r
1948 is set to zero, the instruction that\r
1949 generated the machine check was an\r
1950 Intel Itanium instruction. If this bit\r
1951 is set to one, the instruction that\r
1952 generated the machine check was IA-32\r
1953 instruction.\r
1954\r
1955 @param InstructionSetIsValid Bit55, The is field in the\r
1956 cache_check parameter is valid.\r
1957\r
1958 @param PrivilegeLevel Bit57:56, Privilege level. The\r
1959 privilege level of the instruction\r
1960 bundle responsible for generating the\r
1961 machine check.\r
1962\r
1963 @param PrivilegeLevelIsValide Bit58, The pl field of the\r
1964 cache_check parameter is\r
1965 valid.\r
1966\r
1967 @param McCorrected Bit59, Machine check corrected: This bit\r
1968 is set to one to indicate that the machine\r
1969 check has been corrected.\r
1970\r
1971 @param TargetAddressIsValid Bit60, Target address is valid:\r
1972 This bit is set to one to\r
1973 indicate that a valid target\r
1974 address has been logged.\r
1975\r
1976 @param RequesterIdentifier Bit61, Requester identifier: This\r
1977 bit is set to one to indicate that\r
1978 a valid requester identifier has\r
1979 been logged.\r
1980\r
1981 @param ResponserIdentifier Bit62, Responder identifier: This\r
1982 bit is set to one to indicate that\r
1983 a valid responder identifier has\r
1984 been logged.\r
1985\r
1986 @param PreciseInsPointer Bit63, Precise instruction pointer.\r
1987 This bit is set to one to indicate\r
1988 that a valid precise instruction\r
1989 pointer has been logged.\r
1990\r
1991**/\r
1992typedef struct {\r
1993 UINT64 Operation:4;\r
1994 UINT64 FailedCacheLevel:2;\r
1995 UINT64 Reserved1:2;\r
1996 UINT64 FailedInDataPart:1;\r
1997 UINT64 FailedInTagPart:1;\r
1998 UINT64 FailedInDataCache:1;\r
1999 UINT64 FailedInInsCache:1;\r
2000 UINT64 Mesi:3;\r
2001 UINT64 MesiIsValid:1;\r
2002 UINT64 FailedWay:5;\r
2003 UINT64 WayIndexIsValid:1;\r
2004\r
2005 UINT64 Reserved2:1;\r
2006 UINT64 MultipleBitsError:1;\r
2007 UINT64 Reserved3:8;\r
2008 UINT64 IndexOfCacheLineError:20;\r
2009 UINT64 Reserved4:2;\r
2010 UINT64 InstructionSet:1;\r
2011 UINT64 InstructionSetIsValid:1;\r
2012\r
2013 UINT64 PrivilegeLevel:2;\r
2014 UINT64 PrivilegeLevelIsValide:1;\r
2015\r
2016 UINT64 McCorrected:1;\r
2017\r
2018 UINT64 TargetAddressIsValid:1;\r
2019 UINT64 RequesterIdentifier:1;\r
2020 UINT64 ResponserIdentifier:1;\r
2021 UINT64 PreciseInsPointer:1;\r
2022\r
2023} PAL_CACHE_CHECK_INFO;\r
2024\r
2025/**\r
2026\r
2027 @param FailedSlot Bit7:0, Slot number of the translation\r
2028 register where the failure occurred.\r
2029\r
2030 @param FailedSlotIsValid Bit8, The tr_slot field in the\r
2031 TLB_check parameter is valid.\r
2032\r
2033 @param TlbLevel Bit11:10, The level of the TLB where the\r
2034 error occurred. A value of 0 indicates the\r
2035 first level of TLB\r
2036\r
2037 @param FailedInDataTr Bit16, Error occurred in the data\r
2038 translation registers.\r
2039\r
2040 @param FailedInInsTr Bit17, Error occurred in the instruction\r
2041 translation registers\r
2042\r
2043 @param FailedInDataTc Bit18, Error occurred in data\r
2044 translation cache.\r
2045\r
2046 @param FailedInInsTc Bit19, Error occurred in the instruction\r
2047 translation cache.\r
2048\r
2049 @param FailedOperation Bit23:20, Type of cache operation that\r
2050 caused the machine check: 0 - unknown\r
2051 1 - TLB access due to load instruction\r
2052 2 - TLB access due to store\r
2053 instruction 3 - TLB access due to\r
2054 instruction fetch or instruction\r
2055 prefetch 4 - TLB access due to data\r
2056 prefetch (both hardware and software)\r
2057 5 - TLB shoot down access 6 - TLB\r
2058 probe instruction (probe, tpa) 7 -\r
2059 move in (VHPT fill) 8 - purge (insert\r
2060 operation that purges entries or a TLB\r
2061 purge instruction) All other values\r
2062 are reserved.\r
2063\r
2064 @param InstructionSet Bit54, Instruction set. If this value\r
2065 is set to zero, the instruction that\r
2066 generated the machine check was an\r
2067 Intel Itanium instruction. If this bit\r
2068 is set to one, the instruction that\r
2069 generated the machine check was IA-32\r
2070 instruction.\r
2071\r
2072 @param InstructionSetIsValid Bit55, The is field in the\r
2073 TLB_check parameter is valid.\r
2074\r
2075 @param PrivelegeLevel Bit57:56, Privilege level. The\r
2076 privilege level of the instruction\r
2077 bundle responsible for generating the\r
2078 machine check.\r
2079\r
2080 @param PrivelegeLevelIsValid Bit58, The pl field of the\r
2081 TLB_check parameter is valid.\r
2082\r
2083 @param McCorrected Bit59, Machine check corrected: This bit\r
2084 is set to one to indicate that the machine\r
2085 check has been corrected.\r
2086\r
2087 @param TargetAddressIsValid Bit60, Target address is valid:\r
2088 This bit is set to one to\r
2089 indicate that a valid target\r
2090 address has been logged.\r
2091\r
2092 @param RequesterIdentifier Bit61 Requester identifier: This\r
2093 bit is set to one to indicate that\r
2094 a valid requester identifier has\r
2095 been logged.\r
2096\r
2097 @param ResponserIdentifier Bit62, Responder identifier: This\r
2098 bit is set to one to indicate that\r
2099 a valid responder identifier has\r
2100 been logged.\r
2101\r
2102 @param PreciseInsPointer Bit63 Precise instruction pointer.\r
2103 This bit is set to one to indicate\r
2104 that a valid precise instruction\r
2105 pointer has been logged.\r
2106**/\r
2107typedef struct {\r
2108 UINT64 FailedSlot:8;\r
2109 UINT64 FailedSlotIsValid:1;\r
2110 UINT64 Reserved1 :1;\r
2111 UINT64 TlbLevel:2;\r
2112 UINT64 Reserved2 :4;\r
2113 UINT64 FailedInDataTr:1;\r
2114 UINT64 FailedInInsTr:1;\r
2115 UINT64 FailedInDataTc:1;\r
2116 UINT64 FailedInInsTc:1;\r
2117 UINT64 FailedOperation:4;\r
2118 UINT64 Reserved3:30;\r
2119 UINT64 InstructionSet:1;\r
2120 UINT64 InstructionSetIsValid:1;\r
2121 UINT64 PrivelegeLevel:2;\r
2122 UINT64 PrivelegeLevelIsValid:1;\r
2123 UINT64 McCorrected:1;\r
2124 UINT64 TargetAddressIsValid:1;\r
2125 UINT64 RequesterIdentifier:1;\r
2126 UINT64 ResponserIdentifier:1;\r
2127 UINT64 PreciseInsPointer:1;\r
2128} PAL_TLB_CHECK_INFO;\r
2129\r
2130/**\r
2131 PAL Procedure - PAL_MC_ERROR_INFO.\r
2132\r
2133 Return Processor Machine Check Information and Processor\r
2134 Static State for logging by SAL. It is required by IPF. The\r
2135 PAL procedure supports the Static Registers calling\r
2136 convention. It could be called at physical and virtual mode.\r
2137\r
2138 @param Index Index of PAL_MC_ERROR_INFO within the list of PAL\r
2139 procedures.\r
2140 @param InfoIndex Unsigned 64-bit integer identifying the\r
2141 error information that is being requested.\r
2142 See PAL_MC_ERROR_INFO.InfoIndex.\r
2143 @param LevelIndex 8-byte formatted value identifying the\r
2144 structure to return error information\r
2145 on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.\r
2146 @param ErrorTypeIndex Unsigned 64-bit integer denoting the\r
2147 type of error information that is\r
2148 being requested for the structure\r
2149 identified in LevelIndex.\r
2150\r
2151 @retval 0 Call completed without error\r
2152 @retval -2 Invalid argument\r
2153 @retval -3 Call completed with error.\r
2154 @retval -6 Argument was valid, but no error\r
2155 information was available\r
2156\r
2157 @return R9 Error information returned. The format of this\r
2158 value is dependant on the input values passed.\r
2159 @return R10 If this value is zero, all the error information\r
2160 specified by err_type_index has been returned. If\r
2161 this value is one, more structure-specific error\r
2162 information is available and the caller needs to\r
2163 make this procedure call again with level_index\r
2164 unchanged and err_type_index, incremented.\r
2165\r
2166**/\r
2167#define PAL_MC_ERROR_INFO 25\r
2168\r
2169/**\r
2170 PAL Procedure - PAL_MC_EXPECTED.\r
2171\r
2172 Set/Reset Expected Machine Check Indicator. It is required by\r
2173 IPF. The PAL procedure supports the Static Registers calling\r
2174 convention. It could be called at physical mode.\r
2175\r
2176 @param Index Index of PAL_MC_EXPECTED within the list of PAL\r
2177 procedures.\r
2178 @param Expected Unsigned integer with a value of 0 or 1 to\r
2179 set or reset the hardware resource\r
2180 PALE_CHECK examines for expected machine\r
2181 checks.\r
2182\r
2183 @retval 0 Call completed without error\r
2184 @retval -2 Invalid argument\r
2185 @retval -3 Call completed with error.\r
2186\r
2187 @return R9 Unsigned integer denoting whether a machine check\r
2188 was previously expected.\r
2189\r
2190**/\r
2191#define PAL_MC_EXPECTED 23\r
2192\r
2193/**\r
2194 PAL Procedure - PAL_MC_REGISTER_MEM.\r
2195\r
2196 Register min-state save area with PAL for machine checks and\r
2197 inits. It is required by IPF. The PAL procedure supports the\r
2198 Static Registers calling convention. It could be called at\r
2199 physical mode.\r
2200\r
2201 @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL\r
2202 procedures.\r
2203 @param Address Physical address of the buffer to be\r
2204 registered with PAL.\r
2205\r
2206 @retval 0 Call completed without error\r
2207 @retval -2 Invalid argument\r
2208 @retval -3 Call completed with error.\r
2209\r
2210**/\r
2211#define PAL_MC_REGISTER_MEM 27\r
2212\r
2213/**\r
2214 PAL Procedure - PAL_MC_RESUME.\r
2215\r
2216 Restore minimal architected state and return to interrupted\r
2217 process. It is required by IPF. The PAL procedure supports the\r
2218 Static Registers calling convention. It could be called at\r
2219 physical mode.\r
2220\r
2221 @param Index Index of PAL_MC_RESUME within the list of PAL\r
2222 procedures.\r
2223 @param SetCmci Unsigned 64 bit integer denoting whether to\r
2224 set the CMC interrupt. A value of 0 indicates\r
2225 not to set the interrupt, a value of 1\r
2226 indicated to set the interrupt, and all other\r
2227 values are reserved.\r
2228 @param SavePtr Physical address of min-state save area used\r
2229 to used to restore processor state.\r
2230 @param NewContext Unsigned 64-bit integer denoting whether\r
2231 the caller is returning to a new context.\r
2232 A value of 0 indicates the caller is\r
2233 returning to the interrupted context, a\r
2234 value of 1 indicates that the caller is\r
2235 returning to a new context.\r
2236\r
2237 @retval -2 Invalid argument\r
2238 @retval -3 Call completed with error.\r
2239\r
2240**/\r
2241#define PAL_MC_RESUME 26\r
2242\r
2243/**\r
2244 PAL Procedure - PAL_HALT.\r
2245\r
2246 Enter the low-power HALT state or an implementation-dependent\r
2247 low-power state. It is optinal. The PAL procedure supports the\r
2248 Static Registers calling convention. It could be called at\r
2249 physical mode.\r
2250\r
2251 @param Index Index of PAL_HALT within the list of PAL\r
2252 procedures.\r
2253 @param HaltState Unsigned 64-bit integer denoting low power\r
2254 state requested.\r
2255 @param IoDetailPtr 8-byte aligned physical address pointer to\r
2256 information on the type of I/O\r
2257 (load/store) requested.\r
2258\r
2259 @retval 0 Call completed without error\r
2260 @retval -1 Unimplemented procedure\r
2261 @retval -2 Invalid argument\r
2262 @retval -3 Call completed with error.\r
2263\r
2264 @return R9 Value returned if a load instruction is requested\r
2265 in the io_detail_ptr\r
2266\r
2267**/\r
2268#define PAL_HALT 28\r
2269\r
2270\r
2271/**\r
2272 PAL Procedure - PAL_HALT_INFO.\r
2273\r
2274 Return the low power capabilities of the processor. It is\r
2275 required by IPF. The PAL procedure supports the\r
2276 Stacked Registers calling convention. It could be called at\r
2277 physical and virtual mode.\r
2278\r
2279 @param Index Index of PAL_HALT_INFO within the list of PAL\r
2280 procedures.\r
2281 @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned\r
2282 on an 8-byte boundary.\r
2283\r
2284 @retval 0 Call completed without error\r
2285 @retval -2 Invalid argument\r
2286 @retval -3 Call completed with error.\r
2287\r
2288**/\r
2289#define PAL_HALT_INFO 257\r
2290\r
2291\r
2292/**\r
2293 PAL Procedure - PAL_HALT_LIGHT.\r
2294\r
2295 Enter the low power LIGHT HALT state. It is required by\r
2296 IPF. The PAL procedure supports the Static Registers calling\r
2297 convention. It could be called at physical and virtual mode.\r
2298\r
2299 @param Index Index of PAL_HALT_LIGHT within the list of PAL\r
2300 procedures.\r
2301\r
2302 @retval 0 Call completed without error\r
2303 @retval -2 Invalid argument\r
2304 @retval -3 Call completed with error.\r
2305\r
2306**/\r
2307#define PAL_HALT_LIGHT 29\r
2308\r
2309/**\r
2310 PAL Procedure - PAL_CACHE_LINE_INIT.\r
2311\r
2312 Initialize tags and data of a cache line for processor\r
2313 testing. It is required by IPF. The PAL procedure supports the\r
2314 Static Registers calling convention. It could be called at\r
2315 physical and virtual mode.\r
2316\r
2317 @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL\r
2318 procedures.\r
2319 @param Address Unsigned 64-bit integer value denoting the\r
2320 physical address from which the physical page\r
2321 number is to be generated. The address must be\r
2322 an implemented physical address, bit 63 must\r
2323 be zero.\r
2324 @param DataValue 64-bit data value which is used to\r
2325 initialize the cache line.\r
2326\r
2327 @retval 0 Call completed without error\r
2328 @retval -2 Invalid argument\r
2329 @retval -3 Call completed with error.\r
2330\r
2331**/\r
2332#define PAL_CACHE_LINE_INIT 31\r
2333\r
2334/**\r
2335 PAL Procedure - PAL_CACHE_READ.\r
2336\r
2337 Read tag and data of a cache line for diagnostic testing. It\r
2338 is optional. The PAL procedure supports the\r
2339 Satcked Registers calling convention. It could be called at\r
2340 physical mode.\r
2341\r
2342 @param Index Index of PAL_CACHE_READ within the list of PAL\r
2343 procedures.\r
2344 @param LineId 8-byte formatted value describing where in the\r
2345 cache to read the data.\r
2346 @param Address 64-bit 8-byte aligned physical address from\r
2347 which to read the data. The address must be an\r
2348 implemented physical address on the processor\r
2349 model with bit 63 set to zero.\r
2350\r
2351 @retval 1 The word at address was found in the\r
2352 cache, but the line was invalid.\r
2353 @retval 0 Call completed without error\r
2354 @retval -2 Invalid argument\r
2355 @retval -3 Call completed with error.\r
2356 @retval -5 The word at address was not found in the\r
2357 cache.\r
2358 @retval -7 The operation requested is not supported\r
2359 for this cache_type and level.\r
2360\r
2361 @return R9 Right-justified value returned from the cache\r
2362 line.\r
2363 @return R10 The number of bits returned in data.\r
2364 @return R11 The status of the cache line.\r
2365\r
2366**/\r
2367#define PAL_CACHE_READ 259\r
2368\r
2369\r
2370/**\r
2371 PAL Procedure - PAL_CACHE_WRITE.\r
2372\r
2373 Write tag and data of a cache for diagnostic testing. It is\r
2374 optional. The PAL procedure supports the Satcked Registers\r
2375 calling convention. It could be called at physical mode.\r
2376\r
2377 @param Index Index of PAL_CACHE_WRITE within the list of PAL\r
2378 procedures.\r
2379 @param LineId 8-byte formatted value describing where in the\r
2380 cache to write the data.\r
2381 @param Address 64-bit 8-byte aligned physical address at\r
2382 which the data should be written. The address\r
2383 must be an implemented physical address on the\r
2384 processor model with bit 63 set to 0.\r
2385 @param Data Unsigned 64-bit integer value to write into\r
2386 the specified part of the cache.\r
2387\r
2388 @retval 0 Call completed without error\r
2389 @retval -2 Invalid argument\r
2390 @retval -3 Call completed with error.\r
2391 @retval -7 The operation requested is not supported\r
2392 for this cache_type and level.\r
2393\r
2394**/\r
2395#define PAL_CACHE_WRITE 260\r
2396\r
2397/**\r
2398 PAL Procedure - PAL_TEST_INFO.\r
2399\r
2400 Returns alignment and size requirements needed for the memory\r
2401 buffer passed to the PAL_TEST_PROC procedure as well as\r
2402 information on self-test control words for the processor self\r
2403 tests. It is required by IPF. The PAL procedure supports the\r
2404 Static Registers calling convention. It could be called at\r
2405 physical mode.\r
2406\r
2407 @param Index Index of PAL_TEST_INFO within the list of PAL\r
2408 procedures.\r
2409 @param TestPhase Unsigned integer that specifies which phase\r
2410 of the processor self-test information is\r
2411 being requested on. A value of 0 indicates\r
2412 the phase two of the processor self-test and\r
2413 a value of 1 indicates phase one of the\r
2414 processor self-test. All other values are\r
2415 reserved.\r
2416\r
2417 @retval 0 Call completed without error\r
2418 @retval -2 Invalid argument\r
2419 @retval -3 Call completed with error.\r
2420\r
2421 @return R9 Unsigned 64-bit integer denoting the number of\r
2422 bytes of main memory needed to perform the second\r
2423 phase of processor self-test.\r
2424 @return R10 Unsigned 64-bit integer denoting the alignment\r
2425 required for the memory buffer.\r
2426 @return R11 48-bit wide bit-field indicating if control of\r
2427 the processor self-tests is supported and which\r
2428 bits of the test_control field are defined for\r
2429 use.\r
2430\r
2431**/\r
2432#define PAL_TEST_INFO 37\r
2433\r
2434/**\r
2435\r
2436 @param BufferSize Indicates the size in bytes of the memory\r
2437 buffer that is passed to this procedure.\r
2438 BufferSize must be greater than or equal in\r
2439 size to the bytes_needed return value from\r
2440 PAL_TEST_INFO, otherwise this procedure will\r
2441 return with an invalid argument return\r
2442 value.\r
2443\r
2444 @param TestPhase Defines which phase of the processor\r
2445 self-tests are requested to be run. A value\r
2446 of zero indicates to run phase two of the\r
2447 processor self-tests. Phase two of the\r
2448 processor self-tests are ones that require\r
2449 external memory to execute correctly. A\r
2450 value of one indicates to run phase one of\r
2451 the processor self-tests. Phase one of the\r
2452 processor self-tests are tests run during\r
2453 PALE_RESET and do not depend on external\r
2454 memory to run correctly. When the caller\r
2455 requests to have phase one of the processor\r
2456 self-test run via this procedure call, a\r
2457 memory buffer may be needed to save and\r
2458 restore state as required by the PAL calling\r
2459 conventions. The procedure PAL_TEST_INFO\r
2460 informs the caller about the requirements of\r
2461 the memory buffer.\r
2462\r
2463**/\r
2464typedef struct {\r
2465 UINT64 BufferSize:56;\r
2466 UINT64 TestPhase:8;\r
2467} PAL_TEST_INFO_INFO;\r
2468\r
2469/**\r
2470\r
2471 @param TestControl This is an ordered implementation-specific\r
2472 control word that allows the user control\r
2473 over the length and runtime of the\r
2474 processor self-tests. This control word is\r
2475 ordered from the longest running tests up\r
2476 to the shortest running tests with bit 0\r
2477 controlling the longest running test. PAL\r
2478 may not implement all 47-bits of the\r
2479 test_control word. PAL communicates if a\r
2480 bit provides control by placing a zero in\r
2481 that bit. If a bit provides no control,\r
2482 PAL will place a one in it. PAL will have\r
2483 two sets of test_control bits for the two\r
2484 phases of the processor self-test. PAL\r
2485 provides information about implemented\r
2486 test_control bits at the hand-off from PAL\r
2487 to SAL for the firmware recovery check.\r
2488 These test_control bits provide control\r
2489 for phase one of processor self-test. It\r
2490 also provides this information via the PAL\r
2491 procedure call PAL_TEST_INFO for both the\r
2492 phase one and phase two processor tests\r
2493 depending on which information the caller\r
2494 is requesting. PAL interprets these bits\r
2495 as input parameters on two occasions. The\r
2496 first time is when SAL passes control back\r
2497 to PAL after the firmware recovery check.\r
2498 The second time is when a call to\r
2499 PAL_TEST_PROC is made. When PAL interprets\r
2500 these bits it will only interpret\r
2501 implemented test_control bits and will\r
2502 ignore the values located in the\r
2503 unimplemented test_control bits. PAL\r
2504 interprets the implemented bits such that\r
2505 if a bit contains a zero, this indicates\r
2506 to run the test. If a bit contains a one,\r
2507 this indicates to PAL to skip the test. If\r
2508 the cs bit indicates that control is not\r
2509 available, the test_control bits will be\r
2510 ignored or generate an illegal argument in\r
2511 procedure calls if the caller sets these\r
2512 bits.\r
2513\r
2514 @param ControlSupport This bit defines if an implementation\r
2515 supports control of the PAL self-tests\r
2516 via the self-test control word. If\r
2517 this bit is 0, the implementation does\r
2518 not support control of the processor\r
2519 self-tests via the self-test control\r
2520 word. If this bit is 1, the\r
2521 implementation does support control of\r
2522 the processor self-tests via the\r
2523 self-test control word. If control is\r
2524 not supported, GR37 will be ignored at\r
2525 the hand-off between SAL and PAL after\r
2526 the firmware recovery check and the\r
2527 PAL procedures related to the\r
2528 processor self-tests may return\r
2529 illegal arguments if a user tries to\r
2530 use the self-test control features.\r
2531\r
2532**/\r
2533typedef struct {\r
2534 UINT64 TestControl:47;\r
2535 UINT64 ControlSupport:1;\r
2536 UINT64 Reserved:16;\r
2537} PAL_SELF_TEST_CONTROL;\r
2538\r
2539/**\r
2540\r
2541 @param Attributes Specifies the memory attributes that are\r
2542 allowed to be used with the memory buffer\r
2543 passed to this procedure. The attributes\r
2544 parameter is a vector where each bit\r
2545 represents one of the virtual memory\r
2546 attributes defined by the architecture.See\r
2547 MEMORY_AATRIBUTES. The caller is required\r
2548 to support the cacheable attribute for the\r
2549 memory buffer, otherwise an invalid\r
2550 argument will be returned.\r
2551\r
2552\r
2553 @param TestControl Is the self-test control word\r
2554 corresponding to the test_phase passed.\r
2555 This test_control directs the coverage and\r
2556 runtime of the processor self-tests\r
2557 specified by the test_phase input\r
2558 argument. Information on if this\r
2559 feature is implemented and the number of\r
2560 bits supported can be obtained by the\r
2561 PAL_TEST_INFO procedure call. If this\r
2562 feature is implemented by the processor,\r
2563 the caller can selectively skip parts of\r
2564 the processor self-test by setting\r
2565 test_control bits to a one. If a bit has a\r
2566 zero, this test will be run. The values in\r
2567 the unimplemented bits are ignored. If\r
2568 PAL_TEST_INFO indicated that the self-test\r
2569 control word is not implemented, this\r
2570 procedure will return with an invalid\r
2571 argument status if the caller sets any of\r
2572 the test_control bits. See\r
2573 PAL_SELF_TEST_CONTROL.\r
2574**/\r
2575typedef struct {\r
2576 UINT64 Attributes:8;\r
2577 UINT64 Reserved:8;\r
2578 UINT64 TestControl:48;\r
2579} PAL_TEST_CONTROL;\r
2580\r
2581/**\r
2582 PAL Procedure - PAL_TEST_PROC.\r
2583\r
2584 Perform late processor self test. It is required by IPF. The\r
2585 PAL procedure supports the Static Registers calling\r
2586 convention. It could be called at physical mode.\r
2587\r
2588 @param Index Index of PAL_TEST_PROC within the list of PAL\r
2589 procedures.\r
2590 @param TestAddress 64-bit physical address of main memory\r
2591 area to be used by processor self-test.\r
2592 The memory region passed must be\r
2593 cacheable, bit 63 must be zero.\r
2594 @param TestInfo Input argument specifying the size of the\r
2595 memory buffer passed and the phase of the\r
2596 processor self-test that should be run. See\r
2597 PAL_TEST_INFO.\r
2598 @param TestParam Input argument specifying the self-test\r
2599 control word and the allowable memory\r
2600 attributes that can be used with the memory\r
2601 buffer. See PAL_TEST_CONTROL.\r
2602\r
2603 @retval 1 Call completed without error, but hardware\r
2604 failures occurred during self-test.\r
2605 @retval 0 Call completed without error\r
2606 @retval -2 Invalid argument\r
2607 @retval -3 Call completed with error.\r
2608\r
2609 @return R9 Formatted 8-byte value denoting the state of the\r
2610 processor after self-test\r
2611\r
2612**/\r
2613#define PAL_TEST_PROC 258\r
2614\r
2615/**\r
2616\r
2617 @param NumberOfInterruptControllers Number of interrupt\r
2618 controllers currently\r
2619 enabled on the system.\r
2620\r
2621 @param NumberOfProcessors Number of processors currently\r
2622 enabled on the system.\r
2623\r
2624**/\r
2625typedef struct {\r
2626 UINT32 NumberOfInterruptControllers;\r
2627 UINT32 NumberOfProcessors;\r
2628} PAL_PLATFORM_INFO;\r
2629\r
2630/**\r
2631 PAL Procedure - PAL_COPY_INFO.\r
2632\r
2633 Return information needed to relocate PAL procedures and PAL\r
2634 PMI code to memory. It is required by IPF. The PAL procedure\r
2635 supports the Static Registers calling convention. It could be\r
2636 called at physical mode.\r
2637\r
2638 @param Index Index of PAL_COPY_INFO within the list of PAL\r
2639 procedures.\r
2640 @param CopyType Unsigned integer denoting type of procedures\r
2641 for which copy information is requested.\r
2642 @param PlatformInfo 8-byte formatted value describing the\r
2643 number of processors and the number of\r
2644 interrupt controllers currently enabled\r
2645 on the system. See PAL_PLATFORM_INFO.\r
2646 @param McaProcStateInfo Unsigned integer denoting the number\r
2647 of bytes that SAL needs for the\r
2648 min-state save area for each\r
2649 processor.\r
2650\r
2651 @retval 0 Call completed without error\r
2652 @retval -2 Invalid argument\r
2653 @retval -3 Call completed with error.\r
2654\r
2655 @return R9 Unsigned integer denoting the number of bytes of\r
2656 PAL information that must be copied to main\r
2657 memory.\r
2658 @return R10 Unsigned integer denoting the starting alignment\r
2659 of the data to be copied.\r
2660\r
2661**/\r
2662#define PAL_COPY_INFO 30\r
2663\r
2664/**\r
2665 PAL Procedure - PAL_COPY_PAL.\r
2666\r
2667 Relocate PAL procedures and PAL PMI code to memory. It is\r
2668 required by IPF. The PAL procedure supports the Stacked\r
2669 Registers calling convention. It could be called at physical\r
2670 mode.\r
2671\r
2672 @param Index Index of PAL_COPY_PAL within the list of PAL\r
2673 procedures.\r
2674 @param TargetAddress Physical address of a memory buffer to\r
2675 copy relocatable PAL procedures and PAL\r
2676 PMI code.\r
2677 @param AllocSize Unsigned integer denoting the size of the\r
2678 buffer passed by SAL for the copy operation.\r
2679 @param CopyOption Unsigned integer indicating whether\r
2680 relocatable PAL code and PAL PMI code\r
2681 should be copied from firmware address\r
2682 space to main memory.\r
2683\r
2684 @retval 0 Call completed without error\r
2685 @retval -2 Invalid argument\r
2686 @retval -3 Call completed with error.\r
2687\r
2688 @return R9 Unsigned integer denoting the offset of PAL_PROC\r
2689 in the relocatable segment copied.\r
2690\r
2691**/\r
2692#define PAL_COPY_PAL 256\r
2693\r
2694/**\r
2695 PAL Procedure - PAL_ENTER_IA_32_ENV.\r
2696\r
2697 Enter IA-32 System environment. It is optional. The PAL\r
2698 procedure supports the Static Registers calling convention.\r
2699 It could be called at physical mode.\r
2700\r
2701 Note: Since this is a special call, it does not follow the PAL\r
2702 static register calling convention. GR28 contains the index of\r
2703 PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other\r
2704 input arguments including GR29-GR31 are setup by SAL to values\r
2705 as required by the IA-32 operating system defined in Table\r
2706 11-67. The registers that are designated as preserved, scratch,\r
2707 input arguments and procedure return values by the static\r
2708 procedure calling convention are not followed by this call. For\r
2709 instance, GR5 and GR6 need not be preserved since these are\r
2710 regarded as scratch by the IA-32 operating system. Note: In an\r
2711 MP system, this call must be COMPLETED on the first CPU to enter\r
2712 the IA-32 System Environment (may or may not be the BSP) prior\r
2713 to being called on the remaining processors in the MP system.\r
2714\r
2715 @param Index GR28 contains the index of the\r
2716 PAL_ENTER_IA_32_ENV call within the list of PAL\r
2717 procedures.\r
2718\r
2719\r
2720 @retval The status is returned in GR4.\r
2721 -1 - Un-implemented procedure 0 JMPE detected\r
2722 at privilege level\r
2723\r
2724 0 - 1 SAL allocated buffer for IA-32 System\r
2725 Environment operation is too small\r
2726\r
2727 2 - IA-32 Firmware Checksum Error\r
2728\r
2729 3 - SAL allocated buffer for IA-32 System\r
2730 Environment operation is not properly aligned\r
2731\r
2732 4 - Error in SAL MP Info Table\r
2733\r
2734 5 - Error in SAL Memory Descriptor Table\r
2735\r
2736 6 - Error in SAL System Table\r
2737\r
2738 7 - Inconsistent IA-32 state\r
2739\r
2740 8 - IA-32 Firmware Internal Error\r
2741\r
2742 9 - IA-32 Soft Reset (Note: remaining register\r
2743 state is undefined for this termination\r
2744 reason)\r
2745\r
2746 10 - Machine Check Error\r
2747\r
2748 11 - Error in SAL I/O Intercept Table\r
2749\r
2750 12 - Processor exit due to other processor in\r
2751 MP system terminating the IA32 system\r
2752 environment. (Note: remaining register state\r
2753 is undefined for this termination reason.)\r
2754\r
2755 13 - Itanium architecture-based state\r
2756 corruption by either SAL PMI handler or I/O\r
2757 Intercept callback function.\r
2758\r
2759\r
2760**/\r
2761#define PAL_ENTER_IA_32_ENV 33\r
2762\r
2763/**\r
2764 PAL Procedure - PAL_PMI_ENTRYPOINT.\r
2765\r
2766 Register PMI memory entrypoints with processor. It is required\r
2767 by IPF. The PAL procedure supports the Stacked Registers\r
2768 calling convention. It could be called at physical mode.\r
2769\r
2770 @param Index Index of PAL_PMI_ENTRYPOINT within the list of\r
2771 PAL procedures.\r
2772 @param SalPmiEntry 256-byte aligned physical address of SAL\r
2773 PMI entrypoint in memory.\r
2774\r
2775 @retval 0 Call completed without error\r
2776 @retval -2 Invalid argument\r
2777 @retval -3 Call completed with error.\r
2778\r
2779**/\r
2780#define PAL_PMI_ENTRYPOINT 32\r
2781\r
2782\r
2783/**\r
2784\r
2785 The ASCII brand identification string will be copied to the\r
2786 address specified in the address input argument. The processor\r
2787 brand identification string is defined to be a maximum of 128\r
2788 characters long; 127 bytes will contain characters and the 128th\r
2789 byte is defined to be NULL (0). A processor may return less than\r
2790 the 127 ASCII characters as long as the string is null\r
2791 terminated. The string length will be placed in the brand_info\r
2792 return argument.\r
2793\r
2794**/\r
2795#define PAL_BRAND_INFO_ID_REQUEST 0\r
2796\r
2797/**\r
2798 PAL Procedure - PAL_BRAND_INFO.\r
2799\r
2800 Provides processor branding information. It is optional by\r
2801 IPF. The PAL procedure supports the Stacked Registers calling\r
2802 convention. It could be called at physical and Virtual mode.\r
2803\r
2804 @param Index Index of PAL_BRAND_INFO within the list of PAL\r
2805 procedures.\r
2806 @param InfoRequest Unsigned 64-bit integer specifying the\r
2807 information that is being requested. (See\r
2808 PAL_BRAND_INFO_ID_REQUEST)\r
2809 @param Address Unsigned 64-bit integer specifying the\r
2810 address of the 128-byte block to which the\r
2811 processor brand string shall be written.\r
2812\r
2813 @retval 0 Call completed without error\r
2814 @retval -1 Unimplemented procedure\r
2815 @retval -2 Invalid argument\r
2816 @retval -3 Call completed with error.\r
2817 @retval -6 Input argument is not implemented.\r
2818\r
2819 @return R9 Brand information returned. The format of this\r
2820 value is dependent on the input values passed.\r
2821\r
2822**/\r
2823#define PAL_BRAND_INFO 274\r
2824\r
2825/**\r
2826 PAL Procedure - PAL_GET_HW_POLICY.\r
2827\r
2828 Returns the current hardware resource sharing policy of the\r
2829 processor. It is optional by IPF. The PAL procedure supports\r
2830 the Static Registers calling convention. It could be called at\r
2831 physical and Virtual mode.\r
2832\r
2833\r
2834 @param Index Index of PAL_GET_HW_POLICY within the list of PAL\r
2835 procedures.\r
2836 @param ProcessorNumber Unsigned 64-bit integer that specifies\r
2837 for which logical processor\r
2838 information is being requested. This\r
2839 input argument must be zero for the\r
2840 first call to this procedure and can\r
2841 be a maximum value of one less than\r
2842 the number of logical processors\r
2843 impacted by the hardware resource\r
2844 sharing policy, which is returned by\r
2845 the R10 return value.\r
2846\r
2847 @retval 0 Call completed without error\r
2848 @retval -1 Unimplemented procedure\r
2849 @retval -2 Invalid argument\r
2850 @retval -3 Call completed with error.\r
2851 @retval -9 Call requires PAL memory buffer.\r
2852\r
2853 @return R9 Unsigned 64-bit integer representing the current\r
2854 hardware resource sharing policy.\r
2855 @return R10 Unsigned 64-bit integer that returns the number\r
2856 of logical processors impacted by the policy\r
2857 input argument.\r
2858 @return R11 Unsigned 64-bit integer containing the logical\r
2859 address of one of the logical processors\r
2860 impacted by policy modification.\r
2861\r
2862**/\r
2863#define PAL_GET_HW_POLICY 48\r
2864\r
2865\r
2866//\r
2867// Value of PAL_SET_HW_POLICY.Policy\r
2868//\r
2869#define PAL_SET_HW_POLICY_PERFORMANCE 0\r
2870#define PAL_SET_HW_POLICY_FAIRNESS 1\r
2871#define PAL_SET_HW_POLICY_HIGH_PRIORITY 2\r
2872#define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3\r
2873\r
2874/**\r
2875 PAL Procedure - PAL_SET_HW_POLICY.\r
2876\r
2877 Sets the current hardware resource sharing policy of the\r
2878 processor. It is optional by IPF. The PAL procedure supports\r
2879 the Static Registers calling convention. It could be called at\r
2880 physical and Virtual mode.\r
2881\r
2882 @param Index Index of PAL_SET_HW_POLICY within the list of PAL\r
2883 procedures.\r
2884 @param Policy Unsigned 64-bit integer specifying the hardware\r
2885 resource sharing policy the caller is setting.\r
2886 See Value of PAL_SET_HW_POLICY.Policy above.\r
2887\r
2888 @retval 1 Call completed successfully but could not\r
2889 change the hardware policy since a\r
2890 competing logical processor is set in\r
2891 exclusive high priority.\r
2892 @retval 0 Call completed without error\r
2893 @retval -1 Unimplemented procedure\r
2894 @retval -2 Invalid argument\r
2895 @retval -3 Call completed with error.\r
2896 @retval -9 Call requires PAL memory buffer.\r
2897\r
2898**/\r
2899#define PAL_SET_HW_POLICY 49\r
2900\r
2901\r
2902/**\r
2903\r
2904 @param Mode Bit2:0, Indicates the mode of operation for this\r
2905 procedure: 0 - Query mode 1 - Error inject mode\r
2906 (err_inj should also be specified) 2 - Cancel\r
2907 outstanding trigger. All other fields in\r
2908 PAL_MC_ERROR_TYPE_INFO,\r
2909 PAL_MC_ERROR_STRUCTURE_INFO and\r
2910 PAL_MC_ERROR_DATA_BUFFER are ignored. All other\r
2911 values are reserved.\r
2912\r
2913 @param ErrorInjection Bit5:3, indicates the mode of error\r
2914 injection: 0 - Error inject only (no\r
2915 error consumption) 1 - Error inject\r
2916 and consume All other values are\r
2917 reserved.\r
2918\r
2919\r
2920 @param ErrorSeverity Bit7:6, indicates the severity desired\r
2921 for error injection/query. Definitions\r
2922 of the different error severity types\r
2923 0 - Corrected error 1 - Recoverable\r
2924 error 2 - Fatal error 3 - Reserved\r
2925\r
2926\r
2927 @param ErrorStructure Bit12:8, Indicates the structure\r
2928 identification for error\r
2929 injection/query: 0 - Any structure\r
2930 (cannot be used during query mode).\r
2931 When selected, the structure type used\r
2932 for error injection is determined by\r
2933 PAL. 1 - Cache 2 - TLB 3 - Register\r
2934 file 4 - Bus/System interconnect 5-15\r
2935 - Reserved 16-31 - Processor\r
2936 specific error injection\r
2937 capabilities.ErrorDataBuffer is used\r
2938 to specify error types. Please refer\r
2939 to the processor specific\r
2940 documentation for additional details.\r
2941\r
2942 @param StructureHierarchy Bit15:13, Indicates the structure\r
2943 hierarchy for error\r
2944 injection/query: 0 - Any level of\r
2945 hierarchy (cannot be used during\r
2946 query mode). When selected, the\r
2947 structure hierarchy used for error\r
2948 injection is determined by PAL. 1\r
2949 - Error structure hierarchy\r
2950 level-1 2 - Error structure\r
2951 hierarchy level-2 3 - Error\r
2952 structure hierarchy level-3 4 -\r
2953 Error structure hierarchy level-4\r
2954 All other values are reserved.\r
2955 Reserved 63:16 Reserved\r
2956\r
2957**/\r
2958typedef struct {\r
2959 UINT64 Mode:3;\r
2960 UINT64 ErrorInjection:3;\r
2961 UINT64 ErrorSeverity:2;\r
2962 UINT64 ErrorStructure:5;\r
2963 UINT64 StructureHierarchy:3;\r
2964 UINT64 Reserved:48;\r
2965} PAL_MC_ERROR_TYPE_INFO;\r
2966\r
2967/**\r
2968\r
2969 @param StructInfoIsValid Bit0 When 1, indicates that the\r
2970 structure information fields\r
2971 (c_t,cl_p,cl_id) are valid and\r
2972 should be used for error injection.\r
2973 When 0, the structure information\r
2974 fields are ignored, and the values\r
2975 of these fields used for error\r
2976 injection are\r
2977 implementation-specific.\r
2978\r
2979 @param CacheType Bit2:1 Indicates which cache should be used\r
2980 for error injection: 0 - Reserved 1 -\r
2981 Instruction cache 2 - Data or unified cache\r
2982 3 - Reserved\r
2983\r
2984\r
2985 @param PortionOfCacheLine Bit5:3 Indicates the portion of the\r
2986 cache line where the error should\r
2987 be injected: 0 - Reserved 1 - Tag\r
2988 2 - Data 3 - mesi All other\r
2989 values are reserved.\r
2990\r
2991 @param Mechanism Bit8:6 Indicates which mechanism is used to\r
2992 identify the cache line to be used for error\r
2993 injection: 0 - Reserved 1 - Virtual address\r
2994 provided in the inj_addr field of the buffer\r
2995 pointed to by err_data_buffer should be used\r
2996 to identify the cache line for error\r
2997 injection. 2 - Physical address provided in\r
2998 the inj_addr field of the buffer pointed to\r
2999 by err_data_buffershould be used to identify\r
3000 the cache line for error injection. 3 - way\r
3001 and index fields provided in err_data_buffer\r
3002 should be used to identify the cache line\r
3003 for error injection. All other values are\r
3004 reserved.\r
3005\r
3006 @param DataPoisonOfCacheLine Bit9 When 1, indicates that a\r
3007 multiple bit, non-correctable\r
3008 error should be injected in the\r
3009 cache line specified by cl_id.\r
3010 If this injected error is not\r
3011 consumed, it may eventually\r
3012 cause a data-poisoning event\r
3013 resulting in a corrected error\r
3014 signal, when the associated\r
3015 cache line is cast out (implicit\r
3016 or explicit write-back of the\r
3017 cache line). The error severity\r
3018 specified by err_sev in\r
3019 err_type_info must be set to 0\r
3020 (corrected error) when this bit\r
3021 is set.\r
3022\r
3023\r
3024 @param TrigerInfoIsValid Bit32 When 1, indicates that the\r
3025 trigger information fields (trigger,\r
3026 trigger_pl) are valid and should be\r
3027 used for error injection. When 0,\r
3028 the trigger information fields are\r
3029 ignored and error injection is\r
3030 performed immediately.\r
3031\r
3032 @param Triger Bit36:33 Indicates the operation type to be\r
3033 used as the error trigger condition. The\r
3034 address corresponding to the trigger is\r
3035 specified in the trigger_addr field of the\r
3036 buffer pointed to by err_data_buffer: 0 -\r
3037 Instruction memory access. The trigger match\r
3038 conditions for this operation type are similar\r
3039 to the IBR address breakpoint match conditions\r
3040 1 - Data memory access. The trigger match\r
3041 conditions for this operation type are similar\r
3042 to the DBR address breakpoint match conditions\r
3043 All other values are reserved.\r
3044\r
3045 @param PrivilegeOfTriger Bit39:37 Indicates the privilege\r
3046 level of the context during which\r
3047 the error should be injected: 0 -\r
3048 privilege level 0 1 - privilege\r
3049 level 1 2 - privilege level 2 3 -\r
3050 privilege level 3 All other values\r
3051 are reserved. If the implementation\r
3052 does not support privilege level\r
3053 qualifier for triggers (i.e. if\r
3054 trigger_pl is 0 in the capabilities\r
3055 vector), this field is ignored and\r
3056 triggers can be taken at any\r
3057 privilege level.\r
3058\r
3059**/\r
3060typedef struct {\r
3061 UINT64 StructInfoIsValid:1;\r
3062 UINT64 CacheType:2;\r
3063 UINT64 PortionOfCacheLine:3;\r
3064 UINT64 Mechanism:3;\r
3065 UINT64 DataPoisonOfCacheLine:1;\r
3066 UINT64 Reserved1:22;\r
3067 UINT64 TrigerInfoIsValid:1;\r
3068 UINT64 Triger:4;\r
3069 UINT64 PrivilegeOfTriger:3;\r
3070 UINT64 Reserved2:24;\r
3071} PAL_MC_ERROR_STRUCT_INFO;\r
3072\r
3073/**\r
3074\r
3075 Buffer Pointed to by err_data_buffer - TLB\r
3076\r
3077**/\r
3078typedef struct {\r
3079 UINT64 TrigerAddress;\r
3080 UINT64 VirtualPageNumber:52;\r
3081 UINT64 Reserved1:8;\r
3082 UINT64 RegionId:24;\r
3083 UINT64 Reserved2:40;\r
3084} PAL_MC_ERROR_DATA_BUFFER_TLB;\r
3085\r
3086/**\r
3087 PAL Procedure - PAL_MC_ERROR_INJECT.\r
3088\r
3089 Injects the requested processor error or returns information\r
3090 on the supported injection capabilities for this particular\r
3091 processor implementation. It is optional by IPF. The PAL\r
3092 procedure supports the Stacked Registers calling convention.\r
3093 It could be called at physical and Virtual mode.\r
3094\r
3095 @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL\r
3096 procedures.\r
3097 @param ErrorTypeInfo Unsigned 64-bit integer specifying the\r
3098 first level error information which\r
3099 identifies the error structure and\r
3100 corresponding structure hierarchy, and\r
3101 the error severity.\r
3102 @param ErrorStructInfo Unsigned 64-bit integer identifying\r
3103 the optional structure specific\r
3104 information that provides the second\r
3105 level details for the requested error.\r
3106 @param ErrorDataBuffer 64-bit physical address of a buffer\r
3107 providing additional parameters for\r
3108 the requested error. The address of\r
3109 this buffer must be 8-byte aligned.\r
3110\r
3111 @retval 0 Call completed without error\r
3112 @retval -1 Unimplemented procedure\r
3113 @retval -2 Invalid argument\r
3114 @retval -3 Call completed with error.\r
3115 @retval -4 Call completed with error; the requested\r
3116 error could not be injected due to failure in\r
3117 locating the target location in the specified\r
3118 structure.\r
3119 @retval -5 Argument was valid, but requested error\r
3120 injection capability is not supported.\r
3121 @retval -9 Call requires PAL memory buffer.\r
3122\r
3123 @return R9 64-bit vector specifying the supported error\r
3124 injection capabilities for the input argument\r
3125 combination of struct_hier, err_struct and\r
3126 err_sev fields in ErrorTypeInfo.\r
3127 @return R10 64-bit vector specifying the architectural\r
3128 resources that are used by the procedure.\r
3129\r
3130**/\r
3131#define PAL_MC_ERROR_INJECT 276\r
3132\r
3133\r
3134//\r
3135// Types of PAL_GET_PSTATE.Type\r
3136//\r
3137#define PAL_GET_PSTATE_RECENT 0\r
3138#define PAL_GET_PSTATE_AVERAGE_NEW_START 1\r
3139#define PAL_GET_PSTATE_AVERAGE 2\r
3140#define PAL_GET_PSTATE_NOW 3\r
3141\r
3142/**\r
3143 PAL Procedure - PAL_GET_PSTATE.\r
3144\r
3145 Returns the performance index of the processor. It is optional\r
3146 by IPF. The PAL procedure supports the Stacked Registers\r
3147 calling convention. It could be called at physical and Virtual\r
3148 mode.\r
3149\r
3150 @param Index Index of PAL_GET_PSTATE within the list of PAL\r
3151 procedures.\r
3152 @param Type Type of performance_index value to be returned\r
3153 by this procedure.See PAL_GET_PSTATE.Type above.\r
3154\r
3155 @retval 1 Call completed without error, but accuracy\r
3156 of performance index has been impacted by a\r
3157 thermal throttling event, or a\r
3158 hardware-initiated event.\r
3159 @retval 0 Call completed without error\r
3160 @retval -1 Unimplemented procedure\r
3161 @retval -2 Invalid argument\r
3162 @retval -3 Call completed with error.\r
3163 @retval -9 Call requires PAL memory buffer.\r
3164\r
3165 @return R9 Unsigned integer denoting the processor\r
3166 performance for the time duration since the last\r
3167 PAL_GET_PSTATE procedure call was made. The\r
3168 value returned is between 0 and 100, and is\r
3169 relative to the performance index of the highest\r
3170 available P-state.\r
3171\r
3172**/\r
3173#define PAL_GET_PSTATE 262\r
3174\r
3175/**\r
3176\r
3177 Layout of PAL_PSTATE_INFO.PStateBuffer\r
3178\r
3179**/\r
3180typedef struct {\r
3181 UINT32 PerformanceIndex:7;\r
3182 UINT32 Reserved1:5;\r
3183 UINT32 TypicalPowerDissipation:20;\r
3184 UINT32 TransitionLatency1;\r
3185 UINT32 TransitionLatency2;\r
3186 UINT32 Reserved2;\r
3187} PAL_PSTATE_INFO_BUFFER;\r
3188\r
3189\r
3190/**\r
3191 PAL Procedure - PAL_PSTATE_INFO.\r
3192\r
3193 Returns information about the P-states supported by the\r
3194 processor. It is optional by IPF. The PAL procedure supports\r
3195 the Static Registers calling convention. It could be called\r
3196 at physical and Virtual mode.\r
3197\r
3198 @param Index Index of PAL_PSTATE_INFO within the list of PAL\r
3199 procedures.\r
3200 @param PStateBuffer 64-bit pointer to a 256-byte buffer\r
3201 aligned on an 8-byte boundary. See\r
3202 PAL_PSTATE_INFO_BUFFER above.\r
3203\r
3204 @retval 0 Call completed without error\r
3205 @retval -1 Unimplemented procedure\r
3206 @retval -2 Invalid argument\r
3207 @retval -3 Call completed with error.\r
3208\r
3209 @return R9 Unsigned integer denoting the number of P-states\r
3210 supported. The maximum value of this field is 16.\r
3211 @return R10 Dependency domain information\r
3212\r
3213**/\r
3214#define PAL_PSTATE_INFO 44\r
3215\r
3216\r
3217/**\r
3218 PAL Procedure - PAL_SET_PSTATE.\r
3219\r
3220 To request a processor transition to a given P-state. It is\r
3221 optional by IPF. The PAL procedure supports the Stacked\r
3222 Registers calling convention. It could be called at physical\r
3223 and Virtual mode.\r
3224\r
3225 @param Index Index of PAL_SET_PSTATE within the list of PAL\r
3226 procedures.\r
3227 @param PState Unsigned integer denoting the processor\r
3228 P-state being requested.\r
3229 @param ForcePState Unsigned integer denoting whether the\r
3230 P-state change should be forced for the\r
3231 logical processor.\r
3232\r
3233 @retval 1 Call completed without error, but\r
3234 transition request was not accepted\r
3235 @retval 0 Call completed without error\r
3236 @retval -1 Unimplemented procedure\r
3237 @retval -2 Invalid argument\r
3238 @retval -3 Call completed with error.\r
3239 @retval -9 Call requires PAL memory buffer.\r
3240\r
3241**/\r
3242#define PAL_SET_PSTATE 263\r
3243\r
3244/**\r
3245 PAL Procedure - PAL_SHUTDOWN.\r
3246\r
3247 Put the logical processor into a low power state which can be\r
3248 exited only by a reset event. It is optional by IPF. The PAL\r
3249 procedure supports the Static Registers calling convention. It\r
3250 could be called at physical mode.\r
3251\r
3252 @param Index Index of PAL_SHUTDOWN within the list of PAL\r
3253 procedures.\r
3254 @param NotifyPlatform 8-byte aligned physical address\r
3255 pointer providing details on how to\r
3256 optionally notify the platform that\r
3257 the processor is entering a shutdown\r
3258 state.\r
3259\r
3260 @retval -1 Unimplemented procedure\r
3261 @retval -2 Invalid argument\r
3262 @retval -3 Call completed with error.\r
3263 @retval -9 Call requires PAL memory buffer.\r
3264\r
3265**/\r
3266#define PAL_SHUTDOWN 45\r
3267\r
3268/**\r
3269\r
3270 Layout of PAL_MEMORY_BUFFER.ControlWord\r
3271\r
3272**/\r
3273typedef struct {\r
3274 UINT64 Registration:1;\r
3275 UINT64 ProbeInterrupt:1;\r
3276 UINT64 Reserved:62;\r
3277} PAL_MEMORY_CONTROL_WORD;\r
3278\r
3279/**\r
3280 PAL Procedure - PAL_MEMORY_BUFFER.\r
3281\r
3282 Provides cacheable memory to PAL for exclusive use during\r
3283 runtime. It is optional by IPF. The PAL procedure supports the\r
3284 Static Registers calling convention. It could be called at\r
3285 physical mode.\r
3286\r
3287 @param Index Index of PAL_MEMORY_BUFFER within the list of PAL\r
3288 procedures.\r
3289 @param BaseAddress Physical address of the memory buffer\r
3290 allocated for PAL use.\r
3291 @param AllocSize Unsigned integer denoting the size of the\r
3292 memory buffer.\r
3293 @param ControlWord Formatted bit vector that provides control\r
3294 options for this procedure. See\r
3295 PAL_MEMORY_CONTROL_WORD above.\r
3296\r
3297 @retval 1 Call has not completed a buffer relocation\r
3298 due to a pending interrupt\r
3299 @retval 0 Call completed without error\r
3300 @retval -1 Unimplemented procedure\r
3301 @retval -2 Invalid argument\r
3302 @retval -3 Call completed with error.\r
3303 @retval -9 Call requires PAL memory buffer.\r
3304\r
3305 @return R9 Returns the minimum size of the memory buffer\r
3306 required if the alloc_size input argument was\r
3307 not large enough.\r
3308\r
3309**/\r
3310#define PAL_MEMORY_BUFFER 277\r
3311\r
3312\r
3313/**\r
3314 PAL Procedure - PAL_VP_CREATE.\r
3315\r
3316 Initializes a new vpd for the operation of a new virtual\r
3317 processor in the virtual environment. It is optional by IPF.\r
3318 The PAL procedure supports the Stacked Registers calling\r
3319 convention. It could be called at Virtual mode.\r
3320\r
3321 @param Index Index of PAL_VP_CREATE within the list of PAL\r
3322 procedures.\r
3323 @param Vpd 64-bit host virtual pointer to the Virtual\r
3324 Processor Descriptor (VPD).\r
3325 @param HostIva 64-bit host virtual pointer to the host IVT\r
3326 for the virtual processor\r
3327 @param OptionalHandler 64-bit non-zero host-virtual pointer\r
3328 to an optional handler for\r
3329 virtualization intercepts.\r
3330\r
3331 @retval 0 Call completed without error\r
3332 @retval -1 Unimplemented procedure\r
3333 @retval -2 Invalid argument\r
3334 @retval -3 Call completed with error.\r
3335 @retval -9 Call requires PAL memory buffer.\r
3336\r
3337**/\r
3338#define PAL_VP_CREATE 265\r
3339\r
3340/**\r
3341\r
3342 Virtual Environment Information Parameter\r
3343\r
3344**/\r
3345typedef struct {\r
3346 UINT64 Reserved1:8;\r
3347 UINT64 Opcode:1;\r
3348 UINT64 Reserved:53;\r
3349} PAL_VP_ENV_INFO_RETURN;\r
3350\r
3351/**\r
3352 PAL Procedure - PAL_VP_ENV_INFO.\r
3353\r
3354 Returns the parameters needed to enter a virtual environment.\r
3355 It is optional by IPF. The PAL procedure supports the Stacked\r
3356 Registers calling convention. It could be called at Virtual\r
3357 mode.\r
3358\r
3359 @param Index Index of PAL_VP_ENV_INFO within the list of PAL\r
3360 procedures.\r
3361 @param Vpd 64-bit host virtual pointer to the Virtual\r
3362 Processor Descriptor (VPD).\r
3363 @param HostIva 64-bit host virtual pointer to the host IVT\r
3364 for the virtual processor\r
3365 @param OptionalHandler 64-bit non-zero host-virtual pointer\r
3366 to an optional handler for\r
3367 virtualization intercepts.\r
3368\r
3369 @retval 0 Call completed without error\r
3370 @retval -1 Unimplemented procedure\r
3371 @retval -2 Invalid argument\r
3372 @retval -3 Call completed with error.\r
3373 @retval -9 Call requires PAL memory buffer.\r
3374\r
3375 @return R9 Unsigned integer denoting the number of bytes\r
3376 required by the PAL virtual environment buffer\r
3377 during PAL_VP_INIT_ENV\r
3378 @return R10 64-bit vector of virtual environment\r
3379 information. See PAL_VP_ENV_INFO_RETURN.\r
3380\r
3381\r
3382**/\r
3383#define PAL_VP_ENV_INFO 266\r
3384\r
3385/**\r
3386 PAL Procedure - PAL_VP_EXIT_ENV.\r
3387\r
3388 Allows a logical processor to exit a virtual environment.\r
3389 It is optional by IPF. The PAL procedure supports the Stacked\r
3390 Registers calling convention. It could be called at Virtual\r
3391 mode.\r
3392\r
3393 @param Index Index of PAL_VP_EXIT_ENV within the list of PAL\r
3394 procedures.\r
3395 @param Iva Optional 64-bit host virtual pointer to the IVT\r
3396 when this procedure is done\r
3397\r
3398 @retval 0 Call completed without error\r
3399 @retval -1 Unimplemented procedure\r
3400 @retval -2 Invalid argument\r
3401 @retval -3 Call completed with error.\r
3402 @retval -9 Call requires PAL memory buffer.\r
3403\r
3404**/\r
3405#define PAL_VP_EXIT_ENV 267\r
3406\r
3407\r
3408\r
3409/**\r
3410 PAL Procedure - PAL_VP_INIT_ENV.\r
3411\r
3412 Allows a logical processor to enter a virtual environment. It\r
3413 is optional by IPF. The PAL procedure supports the Stacked\r
3414 Registers calling convention. It could be called at Virtual\r
3415 mode.\r
3416\r
3417 @param Index Index of PAL_VP_INIT_ENV within the list of PAL\r
3418 procedures.\r
3419 @param ConfigOptions 64-bit vector of global configuration\r
3420 settings.\r
3421 @param PhysicalBase Host physical base address of a block of\r
3422 contiguous physical memory for the PAL\r
3423 virtual environment buffer 1) This\r
3424 memory area must be allocated by the VMM\r
3425 and be 4K aligned. The first logical\r
3426 processor to enter the environment will\r
3427 initialize the physical block for\r
3428 virtualization operations.\r
3429 @param VirtualBase Host virtual base address of the\r
3430 corresponding physical memory block for\r
3431 the PAL virtual environment buffer : The\r
3432 VMM must maintain the host virtual to host\r
3433 physical data and instruction translations\r
3434 in TRs for addresses within the allocated\r
3435 address space. Logical processors in this\r
3436 virtual environment will use this address\r
3437 when transitioning to virtual mode\r
3438 operations.\r
3439\r
3440 @retval 0 Call completed without error\r
3441 @retval -1 Unimplemented procedure\r
3442 @retval -2 Invalid argument\r
3443 @retval -3 Call completed with error.\r
3444 @retval -9 Call requires PAL memory buffer.\r
3445\r
3446 @return R9 Virtualization Service Address - VSA specifies\r
3447 the virtual base address of the PAL\r
3448 virtualization services in this virtual\r
3449 environment.\r
3450\r
3451\r
3452**/\r
3453#define PAL_VP_INIT_ENV 268\r
3454\r
3455\r
3456/**\r
3457 PAL Procedure - PAL_VP_REGISTER.\r
3458\r
3459 Register a different host IVT and/or a different optional\r
3460 virtualization intercept handler for the virtual processor\r
3461 specified by vpd. It is optional by IPF. The PAL procedure\r
3462 supports the Stacked Registers calling convention. It could be\r
3463 called at Virtual mode.\r
3464\r
3465 @param Index Index of PAL_VP_REGISTER within the list of PAL\r
3466 procedures.\r
3467 @param Vpd 64-bit host virtual pointer to the Virtual\r
3468 Processor Descriptor (VPD) host_iva 64-bit host\r
3469 virtual pointer to the host IVT for the virtual\r
3470 processor\r
3471 @param OptionalHandler 64-bit non-zero host-virtual pointer\r
3472 to an optional handler for\r
3473 virtualization intercepts.\r
3474\r
3475 @retval 0 Call completed without error\r
3476 @retval -1 Unimplemented procedure\r
3477 @retval -2 Invalid argument\r
3478 @retval -3 Call completed with error.\r
3479 @retval -9 Call requires PAL memory buffer.\r
3480\r
3481**/\r
3482#define PAL_VP_REGISTER 269\r
3483\r
3484\r
3485/**\r
3486 PAL Procedure - PAL_VP_RESTORE.\r
3487\r
3488 Restores virtual processor state for the specified vpd on the\r
3489 logical processor. It is optional by IPF. The PAL procedure\r
3490 supports the Stacked Registers calling convention. It could be\r
3491 called at Virtual mode.\r
3492\r
3493 @param Index Index of PAL_VP_RESTORE within the list of PAL\r
3494 procedures.\r
3495 @param Vpd 64-bit host virtual pointer to the Virtual\r
3496 Processor Descriptor (VPD) host_iva 64-bit host\r
3497 virtual pointer to the host IVT for the virtual\r
3498 processor\r
3499 @param PalVector Vector specifies PAL procedure\r
3500 implementation-specific state to be\r
3501 restored.\r
3502\r
3503 @retval 0 Call completed without error\r
3504 @retval -1 Unimplemented procedure\r
3505 @retval -2 Invalid argument\r
3506 @retval -3 Call completed with error.\r
3507 @retval -9 Call requires PAL memory buffer.\r
3508\r
3509**/\r
3510#define PAL_VP_RESTORE 270\r
3511\r
3512/**\r
3513 PAL Procedure - PAL_VP_SAVE.\r
3514\r
3515 Saves virtual processor state for the specified vpd on the\r
3516 logical processor. It is optional by IPF. The PAL procedure\r
3517 supports the Stacked Registers calling convention. It could be\r
3518 called at Virtual mode.\r
3519\r
3520 @param Index Index of PAL_VP_SAVE within the list of PAL\r
3521 procedures.\r
3522 @param Vpd 64-bit host virtual pointer to the Virtual\r
3523 Processor Descriptor (VPD) host_iva 64-bit host\r
3524 virtual pointer to the host IVT for the virtual\r
3525 processor\r
3526 @param PalVector Vector specifies PAL procedure\r
3527 implementation-specific state to be\r
3528 restored.\r
3529\r
3530 @retval 0 Call completed without error\r
3531 @retval -1 Unimplemented procedure\r
3532 @retval -2 Invalid argument\r
3533 @retval -3 Call completed with error.\r
3534 @retval -9 Call requires PAL memory buffer.\r
3535\r
3536**/\r
3537#define PAL_VP_SAVE 271\r
3538\r
3539\r
3540/**\r
3541 PAL Procedure - PAL_VP_TERMINATE.\r
3542\r
3543 Terminates operation for the specified virtual processor. It\r
3544 is optional by IPF. The PAL procedure supports the Stacked\r
3545 Registers calling convention. It could be called at Virtual\r
3546 mode.\r
3547\r
3548 @param Index Index of PAL_VP_TERMINATE within the list of PAL\r
3549 procedures.\r
3550 @param Vpd 64-bit host virtual pointer to the Virtual\r
3551 Processor Descriptor (VPD)\r
3552 @param Iva Optional 64-bit host virtual pointer to the IVT\r
3553 when this procedure is done.\r
3554\r
3555 @retval 0 Call completed without error\r
3556 @retval -1 Unimplemented procedure\r
3557 @retval -2 Invalid argument\r
3558 @retval -3 Call completed with error.\r
3559 @retval -9 Call requires PAL memory buffer.\r
3560\r
3561**/\r
3562#define PAL_VP_TERMINATE 272\r
3563\r
3564\r
3565/**\r
3566 Makes a PAL procedure call.\r
3567\r
3568 This is a wrapper function to make a PAL procedure call. Based on the Index value,\r
3569 this API will make static or stacked PAL call. Architected procedures may be designated\r
3570 as required or optional. If a PAL procedure is specified as optional, a unique return\r
3571 code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.\r
3572 This indicates that the procedure is not present in this PAL implementation. It is the\r
3573 caller's responsibility to check for this return code after calling any optional PAL\r
3574 procedure. No parameter checking is performed on the 4 input parameters, but there are\r
3575 some common rules that the caller should follow when making a PAL call. Any address\r
3576 passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses\r
3577 may cause undefined results. For those parameters defined as reserved or some fields\r
3578 defined as reserved must be zero filled or the invalid argument return value may be\r
3579 returned or undefined result may occur during the execution of the procedure.\r
3580 This function is only available on IPF.\r
3581\r
3582 @param Index The PAL procedure Index number.\r
3583 @param Arg2 The 2nd parameter for PAL procedure calls.\r
3584 @param Arg3 The 3rd parameter for PAL procedure calls.\r
3585 @param Arg4 The 4th parameter for PAL procedure calls.\r
3586\r
3587 @return structure returned from the PAL Call procedure, including the status and return value.\r
3588\r
3589**/\r
3590PAL_CALL_RETURN\r
3591EFIAPI\r
3592PalCall (\r
3593 IN UINT64 Index,\r
3594 IN UINT64 Arg2,\r
3595 IN UINT64 Arg3,\r
3596 IN UINT64 Arg4\r
3597 );\r
3598\r
3599#endif\r
3600\r
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