| | 1 | /** @file\r |
| | 2 | Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.\r |
| | 3 | \r |
| | 4 | This library is identical to the PCI Library, except the access method for performing PCI\r |
| | 5 | configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows\r |
| | 6 | access to PCI Segment #0.\r |
| | 7 | \r |
| | 8 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| | 9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| | 10 | \r |
| | 11 | **/\r |
| | 12 | \r |
| | 13 | #ifndef __PCI_CF8_LIB_H__\r |
| | 14 | #define __PCI_CF8_LIB_H__\r |
| | 15 | \r |
| | 16 | /**\r |
| | 17 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r |
| | 18 | address that can be passed to the PCI Library functions.\r |
| | 19 | \r |
| | 20 | Computes an address that is compatible with the PCI Library functions. The\r |
| | 21 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r |
| | 22 | the generation of the address.\r |
| | 23 | \r |
| | 24 | @param Bus PCI Bus number. Range 0..255.\r |
| | 25 | @param Device PCI Device number. Range 0..31.\r |
| | 26 | @param Function PCI Function number. Range 0..7.\r |
| | 27 | @param Register PCI Register number. Range 0..255.\r |
| | 28 | \r |
| | 29 | @return The encode PCI address.\r |
| | 30 | \r |
| | 31 | **/\r |
| | 32 | #define PCI_CF8_LIB_ADDRESS(Bus, Device, Function, Offset) \\r |
| | 33 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r |
| | 34 | \r |
| | 35 | /**\r |
| | 36 | Registers a PCI device so PCI configuration registers may be accessed after\r |
| | 37 | SetVirtualAddressMap().\r |
| | 38 | \r |
| | 39 | Registers the PCI device specified by Address so all the PCI configuration registers\r |
| | 40 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r |
| | 41 | \r |
| | 42 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 43 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 44 | \r |
| | 45 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 46 | Register.\r |
| | 47 | \r |
| | 48 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
| | 49 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
| | 50 | after ExitBootServices().\r |
| | 51 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r |
| | 52 | at runtime could not be mapped.\r |
| | 53 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r |
| | 54 | complete the registration.\r |
| | 55 | \r |
| | 56 | **/\r |
| | 57 | RETURN_STATUS\r |
| | 58 | EFIAPI\r |
| | 59 | PciCf8RegisterForRuntimeAccess (\r |
| | 60 | IN UINTN Address\r |
| | 61 | );\r |
| | 62 | \r |
| | 63 | /**\r |
| | 64 | Reads an 8-bit PCI configuration register.\r |
| | 65 | \r |
| | 66 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| | 67 | This function must guarantee that all PCI read and write operations are\r |
| | 68 | serialized.\r |
| | 69 | \r |
| | 70 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 71 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 72 | \r |
| | 73 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 74 | Register.\r |
| | 75 | \r |
| | 76 | @return The read value from the PCI configuration register.\r |
| | 77 | \r |
| | 78 | **/\r |
| | 79 | UINT8\r |
| | 80 | EFIAPI\r |
| | 81 | PciCf8Read8 (\r |
| | 82 | IN UINTN Address\r |
| | 83 | );\r |
| | 84 | \r |
| | 85 | /**\r |
| | 86 | Writes an 8-bit PCI configuration register.\r |
| | 87 | \r |
| | 88 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| | 89 | value specified by Value. Value is returned. This function must guarantee\r |
| | 90 | that all PCI read and write operations are serialized.\r |
| | 91 | \r |
| | 92 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 93 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 94 | \r |
| | 95 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 96 | Register.\r |
| | 97 | @param Value The value to write.\r |
| | 98 | \r |
| | 99 | @return The value written to the PCI configuration register.\r |
| | 100 | \r |
| | 101 | **/\r |
| | 102 | UINT8\r |
| | 103 | EFIAPI\r |
| | 104 | PciCf8Write8 (\r |
| | 105 | IN UINTN Address,\r |
| | 106 | IN UINT8 Value\r |
| | 107 | );\r |
| | 108 | \r |
| | 109 | /**\r |
| | 110 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
| | 111 | an 8-bit value.\r |
| | 112 | \r |
| | 113 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| | 114 | bitwise OR between the read result and the value specified by\r |
| | 115 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| | 116 | specified by Address. The value written to the PCI configuration register is\r |
| | 117 | returned. This function must guarantee that all PCI read and write operations\r |
| | 118 | are serialized.\r |
| | 119 | \r |
| | 120 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 121 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 122 | \r |
| | 123 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 124 | Register.\r |
| | 125 | @param OrData The value to OR with the PCI configuration register.\r |
| | 126 | \r |
| | 127 | @return The value written back to the PCI configuration register.\r |
| | 128 | \r |
| | 129 | **/\r |
| | 130 | UINT8\r |
| | 131 | EFIAPI\r |
| | 132 | PciCf8Or8 (\r |
| | 133 | IN UINTN Address,\r |
| | 134 | IN UINT8 OrData\r |
| | 135 | );\r |
| | 136 | \r |
| | 137 | /**\r |
| | 138 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| | 139 | value.\r |
| | 140 | \r |
| | 141 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| | 142 | bitwise AND between the read result and the value specified by AndData, and\r |
| | 143 | writes the result to the 8-bit PCI configuration register specified by\r |
| | 144 | Address. The value written to the PCI configuration register is returned.\r |
| | 145 | This function must guarantee that all PCI read and write operations are\r |
| | 146 | serialized.\r |
| | 147 | \r |
| | 148 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 149 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 150 | \r |
| | 151 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 152 | Register.\r |
| | 153 | @param AndData The value to AND with the PCI configuration register.\r |
| | 154 | \r |
| | 155 | @return The value written back to the PCI configuration register.\r |
| | 156 | \r |
| | 157 | **/\r |
| | 158 | UINT8\r |
| | 159 | EFIAPI\r |
| | 160 | PciCf8And8 (\r |
| | 161 | IN UINTN Address,\r |
| | 162 | IN UINT8 AndData\r |
| | 163 | );\r |
| | 164 | \r |
| | 165 | /**\r |
| | 166 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| | 167 | value, followed a bitwise OR with another 8-bit value.\r |
| | 168 | \r |
| | 169 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| | 170 | bitwise AND between the read result and the value specified by AndData,\r |
| | 171 | performs a bitwise OR between the result of the AND operation and\r |
| | 172 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| | 173 | configuration register specified by Address. The value written to the PCI\r |
| | 174 | configuration register is returned. This function must guarantee that all PCI\r |
| | 175 | read and write operations are serialized.\r |
| | 176 | \r |
| | 177 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 178 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 179 | \r |
| | 180 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 181 | Register.\r |
| | 182 | @param AndData The value to AND with the PCI configuration register.\r |
| | 183 | @param OrData The value to OR with the result of the AND operation.\r |
| | 184 | \r |
| | 185 | @return The value written back to the PCI configuration register.\r |
| | 186 | \r |
| | 187 | **/\r |
| | 188 | UINT8\r |
| | 189 | EFIAPI\r |
| | 190 | PciCf8AndThenOr8 (\r |
| | 191 | IN UINTN Address,\r |
| | 192 | IN UINT8 AndData,\r |
| | 193 | IN UINT8 OrData\r |
| | 194 | );\r |
| | 195 | \r |
| | 196 | /**\r |
| | 197 | Reads a bit field of a PCI configuration register.\r |
| | 198 | \r |
| | 199 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| | 200 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| | 201 | returned.\r |
| | 202 | \r |
| | 203 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 204 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 205 | If StartBit is greater than 7, then ASSERT().\r |
| | 206 | If EndBit is greater than 7, then ASSERT().\r |
| | 207 | If EndBit is less than StartBit, then ASSERT().\r |
| | 208 | \r |
| | 209 | @param Address PCI configuration register to read.\r |
| | 210 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 211 | Range 0..7.\r |
| | 212 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 213 | Range 0..7.\r |
| | 214 | \r |
| | 215 | @return The value of the bit field read from the PCI configuration register.\r |
| | 216 | \r |
| | 217 | **/\r |
| | 218 | UINT8\r |
| | 219 | EFIAPI\r |
| | 220 | PciCf8BitFieldRead8 (\r |
| | 221 | IN UINTN Address,\r |
| | 222 | IN UINTN StartBit,\r |
| | 223 | IN UINTN EndBit\r |
| | 224 | );\r |
| | 225 | \r |
| | 226 | /**\r |
| | 227 | Writes a bit field to a PCI configuration register.\r |
| | 228 | \r |
| | 229 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| | 230 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| | 231 | destination PCI configuration register are preserved. The new value of the\r |
| | 232 | 8-bit register is returned.\r |
| | 233 | \r |
| | 234 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 235 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 236 | If StartBit is greater than 7, then ASSERT().\r |
| | 237 | If EndBit is greater than 7, then ASSERT().\r |
| | 238 | If EndBit is less than StartBit, then ASSERT().\r |
| | 239 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 240 | \r |
| | 241 | @param Address PCI configuration register to write.\r |
| | 242 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 243 | Range 0..7.\r |
| | 244 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 245 | Range 0..7.\r |
| | 246 | @param Value New value of the bit field.\r |
| | 247 | \r |
| | 248 | @return The value written back to the PCI configuration register.\r |
| | 249 | \r |
| | 250 | **/\r |
| | 251 | UINT8\r |
| | 252 | EFIAPI\r |
| | 253 | PciCf8BitFieldWrite8 (\r |
| | 254 | IN UINTN Address,\r |
| | 255 | IN UINTN StartBit,\r |
| | 256 | IN UINTN EndBit,\r |
| | 257 | IN UINT8 Value\r |
| | 258 | );\r |
| | 259 | \r |
| | 260 | /**\r |
| | 261 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| | 262 | writes the result back to the bit field in the 8-bit port.\r |
| | 263 | \r |
| | 264 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| | 265 | bitwise OR between the read result and the value specified by\r |
| | 266 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| | 267 | specified by Address. The value written to the PCI configuration register is\r |
| | 268 | returned. This function must guarantee that all PCI read and write operations\r |
| | 269 | are serialized. Extra left bits in OrData are stripped.\r |
| | 270 | \r |
| | 271 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 272 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 273 | If StartBit is greater than 7, then ASSERT().\r |
| | 274 | If EndBit is greater than 7, then ASSERT().\r |
| | 275 | If EndBit is less than StartBit, then ASSERT().\r |
| | 276 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 277 | \r |
| | 278 | @param Address PCI configuration register to write.\r |
| | 279 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 280 | Range 0..7.\r |
| | 281 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 282 | Range 0..7.\r |
| | 283 | @param OrData The value to OR with the PCI configuration register.\r |
| | 284 | \r |
| | 285 | @return The value written back to the PCI configuration register.\r |
| | 286 | \r |
| | 287 | **/\r |
| | 288 | UINT8\r |
| | 289 | EFIAPI\r |
| | 290 | PciCf8BitFieldOr8 (\r |
| | 291 | IN UINTN Address,\r |
| | 292 | IN UINTN StartBit,\r |
| | 293 | IN UINTN EndBit,\r |
| | 294 | IN UINT8 OrData\r |
| | 295 | );\r |
| | 296 | \r |
| | 297 | /**\r |
| | 298 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| | 299 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| | 300 | \r |
| | 301 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| | 302 | bitwise AND between the read result and the value specified by AndData, and\r |
| | 303 | writes the result to the 8-bit PCI configuration register specified by\r |
| | 304 | Address. The value written to the PCI configuration register is returned.\r |
| | 305 | This function must guarantee that all PCI read and write operations are\r |
| | 306 | serialized. Extra left bits in AndData are stripped.\r |
| | 307 | \r |
| | 308 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 309 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 310 | If StartBit is greater than 7, then ASSERT().\r |
| | 311 | If EndBit is greater than 7, then ASSERT().\r |
| | 312 | If EndBit is less than StartBit, then ASSERT().\r |
| | 313 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 314 | \r |
| | 315 | @param Address PCI configuration register to write.\r |
| | 316 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 317 | Range 0..7.\r |
| | 318 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 319 | Range 0..7.\r |
| | 320 | @param AndData The value to AND with the PCI configuration register.\r |
| | 321 | \r |
| | 322 | @return The value written back to the PCI configuration register.\r |
| | 323 | \r |
| | 324 | **/\r |
| | 325 | UINT8\r |
| | 326 | EFIAPI\r |
| | 327 | PciCf8BitFieldAnd8 (\r |
| | 328 | IN UINTN Address,\r |
| | 329 | IN UINTN StartBit,\r |
| | 330 | IN UINTN EndBit,\r |
| | 331 | IN UINT8 AndData\r |
| | 332 | );\r |
| | 333 | \r |
| | 334 | /**\r |
| | 335 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| | 336 | bitwise OR, and writes the result back to the bit field in the\r |
| | 337 | 8-bit port.\r |
| | 338 | \r |
| | 339 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| | 340 | bitwise AND followed by a bitwise OR between the read result and\r |
| | 341 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| | 342 | configuration register specified by Address. The value written to the PCI\r |
| | 343 | configuration register is returned. This function must guarantee that all PCI\r |
| | 344 | read and write operations are serialized. Extra left bits in both AndData and\r |
| | 345 | OrData are stripped.\r |
| | 346 | \r |
| | 347 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 348 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 349 | If StartBit is greater than 7, then ASSERT().\r |
| | 350 | If EndBit is greater than 7, then ASSERT().\r |
| | 351 | If EndBit is less than StartBit, then ASSERT().\r |
| | 352 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 353 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 354 | \r |
| | 355 | @param Address PCI configuration register to write.\r |
| | 356 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 357 | Range 0..7.\r |
| | 358 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 359 | Range 0..7.\r |
| | 360 | @param AndData The value to AND with the PCI configuration register.\r |
| | 361 | @param OrData The value to OR with the result of the AND operation.\r |
| | 362 | \r |
| | 363 | @return The value written back to the PCI configuration register.\r |
| | 364 | \r |
| | 365 | **/\r |
| | 366 | UINT8\r |
| | 367 | EFIAPI\r |
| | 368 | PciCf8BitFieldAndThenOr8 (\r |
| | 369 | IN UINTN Address,\r |
| | 370 | IN UINTN StartBit,\r |
| | 371 | IN UINTN EndBit,\r |
| | 372 | IN UINT8 AndData,\r |
| | 373 | IN UINT8 OrData\r |
| | 374 | );\r |
| | 375 | \r |
| | 376 | /**\r |
| | 377 | Reads a 16-bit PCI configuration register.\r |
| | 378 | \r |
| | 379 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| | 380 | This function must guarantee that all PCI read and write operations are\r |
| | 381 | serialized.\r |
| | 382 | \r |
| | 383 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 384 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 385 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 386 | \r |
| | 387 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 388 | Register.\r |
| | 389 | \r |
| | 390 | @return The read value from the PCI configuration register.\r |
| | 391 | \r |
| | 392 | **/\r |
| | 393 | UINT16\r |
| | 394 | EFIAPI\r |
| | 395 | PciCf8Read16 (\r |
| | 396 | IN UINTN Address\r |
| | 397 | );\r |
| | 398 | \r |
| | 399 | /**\r |
| | 400 | Writes a 16-bit PCI configuration register.\r |
| | 401 | \r |
| | 402 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| | 403 | value specified by Value. Value is returned. This function must guarantee\r |
| | 404 | that all PCI read and write operations are serialized.\r |
| | 405 | \r |
| | 406 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 407 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 408 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 409 | \r |
| | 410 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 411 | Register.\r |
| | 412 | @param Value The value to write.\r |
| | 413 | \r |
| | 414 | @return The value written to the PCI configuration register.\r |
| | 415 | \r |
| | 416 | **/\r |
| | 417 | UINT16\r |
| | 418 | EFIAPI\r |
| | 419 | PciCf8Write16 (\r |
| | 420 | IN UINTN Address,\r |
| | 421 | IN UINT16 Value\r |
| | 422 | );\r |
| | 423 | \r |
| | 424 | /**\r |
| | 425 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
| | 426 | a 16-bit value.\r |
| | 427 | \r |
| | 428 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| | 429 | bitwise OR between the read result and the value specified by\r |
| | 430 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| | 431 | specified by Address. The value written to the PCI configuration register is\r |
| | 432 | returned. This function must guarantee that all PCI read and write operations\r |
| | 433 | are serialized.\r |
| | 434 | \r |
| | 435 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 436 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 437 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 438 | \r |
| | 439 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 440 | Register.\r |
| | 441 | @param OrData The value to OR with the PCI configuration register.\r |
| | 442 | \r |
| | 443 | @return The value written back to the PCI configuration register.\r |
| | 444 | \r |
| | 445 | **/\r |
| | 446 | UINT16\r |
| | 447 | EFIAPI\r |
| | 448 | PciCf8Or16 (\r |
| | 449 | IN UINTN Address,\r |
| | 450 | IN UINT16 OrData\r |
| | 451 | );\r |
| | 452 | \r |
| | 453 | /**\r |
| | 454 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| | 455 | value.\r |
| | 456 | \r |
| | 457 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| | 458 | bitwise AND between the read result and the value specified by AndData, and\r |
| | 459 | writes the result to the 16-bit PCI configuration register specified by\r |
| | 460 | Address. The value written to the PCI configuration register is returned.\r |
| | 461 | This function must guarantee that all PCI read and write operations are\r |
| | 462 | serialized.\r |
| | 463 | \r |
| | 464 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 465 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 466 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 467 | \r |
| | 468 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 469 | Register.\r |
| | 470 | @param AndData The value to AND with the PCI configuration register.\r |
| | 471 | \r |
| | 472 | @return The value written back to the PCI configuration register.\r |
| | 473 | \r |
| | 474 | **/\r |
| | 475 | UINT16\r |
| | 476 | EFIAPI\r |
| | 477 | PciCf8And16 (\r |
| | 478 | IN UINTN Address,\r |
| | 479 | IN UINT16 AndData\r |
| | 480 | );\r |
| | 481 | \r |
| | 482 | /**\r |
| | 483 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| | 484 | value, followed a bitwise OR with another 16-bit value.\r |
| | 485 | \r |
| | 486 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| | 487 | bitwise AND between the read result and the value specified by AndData,\r |
| | 488 | performs a bitwise OR between the result of the AND operation and\r |
| | 489 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| | 490 | configuration register specified by Address. The value written to the PCI\r |
| | 491 | configuration register is returned. This function must guarantee that all PCI\r |
| | 492 | read and write operations are serialized.\r |
| | 493 | \r |
| | 494 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 495 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 496 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 497 | \r |
| | 498 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 499 | Register.\r |
| | 500 | @param AndData The value to AND with the PCI configuration register.\r |
| | 501 | @param OrData The value to OR with the result of the AND operation.\r |
| | 502 | \r |
| | 503 | @return The value written back to the PCI configuration register.\r |
| | 504 | \r |
| | 505 | **/\r |
| | 506 | UINT16\r |
| | 507 | EFIAPI\r |
| | 508 | PciCf8AndThenOr16 (\r |
| | 509 | IN UINTN Address,\r |
| | 510 | IN UINT16 AndData,\r |
| | 511 | IN UINT16 OrData\r |
| | 512 | );\r |
| | 513 | \r |
| | 514 | /**\r |
| | 515 | Reads a bit field of a PCI configuration register.\r |
| | 516 | \r |
| | 517 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| | 518 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| | 519 | returned.\r |
| | 520 | \r |
| | 521 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 522 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 523 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 524 | If StartBit is greater than 15, then ASSERT().\r |
| | 525 | If EndBit is greater than 15, then ASSERT().\r |
| | 526 | If EndBit is less than StartBit, then ASSERT().\r |
| | 527 | \r |
| | 528 | @param Address PCI configuration register to read.\r |
| | 529 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 530 | Range 0..15.\r |
| | 531 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 532 | Range 0..15.\r |
| | 533 | \r |
| | 534 | @return The value of the bit field read from the PCI configuration register.\r |
| | 535 | \r |
| | 536 | **/\r |
| | 537 | UINT16\r |
| | 538 | EFIAPI\r |
| | 539 | PciCf8BitFieldRead16 (\r |
| | 540 | IN UINTN Address,\r |
| | 541 | IN UINTN StartBit,\r |
| | 542 | IN UINTN EndBit\r |
| | 543 | );\r |
| | 544 | \r |
| | 545 | /**\r |
| | 546 | Writes a bit field to a PCI configuration register.\r |
| | 547 | \r |
| | 548 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| | 549 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| | 550 | destination PCI configuration register are preserved. The new value of the\r |
| | 551 | 16-bit register is returned.\r |
| | 552 | \r |
| | 553 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 554 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 555 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 556 | If StartBit is greater than 15, then ASSERT().\r |
| | 557 | If EndBit is greater than 15, then ASSERT().\r |
| | 558 | If EndBit is less than StartBit, then ASSERT().\r |
| | 559 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 560 | \r |
| | 561 | @param Address PCI configuration register to write.\r |
| | 562 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 563 | Range 0..15.\r |
| | 564 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 565 | Range 0..15.\r |
| | 566 | @param Value New value of the bit field.\r |
| | 567 | \r |
| | 568 | @return The value written back to the PCI configuration register.\r |
| | 569 | \r |
| | 570 | **/\r |
| | 571 | UINT16\r |
| | 572 | EFIAPI\r |
| | 573 | PciCf8BitFieldWrite16 (\r |
| | 574 | IN UINTN Address,\r |
| | 575 | IN UINTN StartBit,\r |
| | 576 | IN UINTN EndBit,\r |
| | 577 | IN UINT16 Value\r |
| | 578 | );\r |
| | 579 | \r |
| | 580 | /**\r |
| | 581 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| | 582 | writes the result back to the bit field in the 16-bit port.\r |
| | 583 | \r |
| | 584 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| | 585 | bitwise OR between the read result and the value specified by\r |
| | 586 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| | 587 | specified by Address. The value written to the PCI configuration register is\r |
| | 588 | returned. This function must guarantee that all PCI read and write operations\r |
| | 589 | are serialized. Extra left bits in OrData are stripped.\r |
| | 590 | \r |
| | 591 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 592 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 593 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 594 | If StartBit is greater than 15, then ASSERT().\r |
| | 595 | If EndBit is greater than 15, then ASSERT().\r |
| | 596 | If EndBit is less than StartBit, then ASSERT().\r |
| | 597 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 598 | \r |
| | 599 | @param Address PCI configuration register to write.\r |
| | 600 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 601 | Range 0..15.\r |
| | 602 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 603 | Range 0..15.\r |
| | 604 | @param OrData The value to OR with the PCI configuration register.\r |
| | 605 | \r |
| | 606 | @return The value written back to the PCI configuration register.\r |
| | 607 | \r |
| | 608 | **/\r |
| | 609 | UINT16\r |
| | 610 | EFIAPI\r |
| | 611 | PciCf8BitFieldOr16 (\r |
| | 612 | IN UINTN Address,\r |
| | 613 | IN UINTN StartBit,\r |
| | 614 | IN UINTN EndBit,\r |
| | 615 | IN UINT16 OrData\r |
| | 616 | );\r |
| | 617 | \r |
| | 618 | /**\r |
| | 619 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| | 620 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| | 621 | \r |
| | 622 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| | 623 | bitwise AND between the read result and the value specified by AndData, and\r |
| | 624 | writes the result to the 16-bit PCI configuration register specified by\r |
| | 625 | Address. The value written to the PCI configuration register is returned.\r |
| | 626 | This function must guarantee that all PCI read and write operations are\r |
| | 627 | serialized. Extra left bits in AndData are stripped.\r |
| | 628 | \r |
| | 629 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 630 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 631 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 632 | If StartBit is greater than 15, then ASSERT().\r |
| | 633 | If EndBit is greater than 15, then ASSERT().\r |
| | 634 | If EndBit is less than StartBit, then ASSERT().\r |
| | 635 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 636 | \r |
| | 637 | @param Address PCI configuration register to write.\r |
| | 638 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 639 | Range 0..15.\r |
| | 640 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 641 | Range 0..15.\r |
| | 642 | @param AndData The value to AND with the PCI configuration register.\r |
| | 643 | \r |
| | 644 | @return The value written back to the PCI configuration register.\r |
| | 645 | \r |
| | 646 | **/\r |
| | 647 | UINT16\r |
| | 648 | EFIAPI\r |
| | 649 | PciCf8BitFieldAnd16 (\r |
| | 650 | IN UINTN Address,\r |
| | 651 | IN UINTN StartBit,\r |
| | 652 | IN UINTN EndBit,\r |
| | 653 | IN UINT16 AndData\r |
| | 654 | );\r |
| | 655 | \r |
| | 656 | /**\r |
| | 657 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| | 658 | bitwise OR, and writes the result back to the bit field in the\r |
| | 659 | 16-bit port.\r |
| | 660 | \r |
| | 661 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| | 662 | bitwise AND followed by a bitwise OR between the read result and\r |
| | 663 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| | 664 | configuration register specified by Address. The value written to the PCI\r |
| | 665 | configuration register is returned. This function must guarantee that all PCI\r |
| | 666 | read and write operations are serialized. Extra left bits in both AndData and\r |
| | 667 | OrData are stripped.\r |
| | 668 | \r |
| | 669 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 670 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 671 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 672 | If StartBit is greater than 15, then ASSERT().\r |
| | 673 | If EndBit is greater than 15, then ASSERT().\r |
| | 674 | If EndBit is less than StartBit, then ASSERT().\r |
| | 675 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 676 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 677 | \r |
| | 678 | @param Address PCI configuration register to write.\r |
| | 679 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 680 | Range 0..15.\r |
| | 681 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 682 | Range 0..15.\r |
| | 683 | @param AndData The value to AND with the PCI configuration register.\r |
| | 684 | @param OrData The value to OR with the result of the AND operation.\r |
| | 685 | \r |
| | 686 | @return The value written back to the PCI configuration register.\r |
| | 687 | \r |
| | 688 | **/\r |
| | 689 | UINT16\r |
| | 690 | EFIAPI\r |
| | 691 | PciCf8BitFieldAndThenOr16 (\r |
| | 692 | IN UINTN Address,\r |
| | 693 | IN UINTN StartBit,\r |
| | 694 | IN UINTN EndBit,\r |
| | 695 | IN UINT16 AndData,\r |
| | 696 | IN UINT16 OrData\r |
| | 697 | );\r |
| | 698 | \r |
| | 699 | /**\r |
| | 700 | Reads a 32-bit PCI configuration register.\r |
| | 701 | \r |
| | 702 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| | 703 | This function must guarantee that all PCI read and write operations are\r |
| | 704 | serialized.\r |
| | 705 | \r |
| | 706 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 707 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 708 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 709 | \r |
| | 710 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 711 | Register.\r |
| | 712 | \r |
| | 713 | @return The read value from the PCI configuration register.\r |
| | 714 | \r |
| | 715 | **/\r |
| | 716 | UINT32\r |
| | 717 | EFIAPI\r |
| | 718 | PciCf8Read32 (\r |
| | 719 | IN UINTN Address\r |
| | 720 | );\r |
| | 721 | \r |
| | 722 | /**\r |
| | 723 | Writes a 32-bit PCI configuration register.\r |
| | 724 | \r |
| | 725 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| | 726 | value specified by Value. Value is returned. This function must guarantee\r |
| | 727 | that all PCI read and write operations are serialized.\r |
| | 728 | \r |
| | 729 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 730 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 731 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 732 | \r |
| | 733 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 734 | Register.\r |
| | 735 | @param Value The value to write.\r |
| | 736 | \r |
| | 737 | @return The value written to the PCI configuration register.\r |
| | 738 | \r |
| | 739 | **/\r |
| | 740 | UINT32\r |
| | 741 | EFIAPI\r |
| | 742 | PciCf8Write32 (\r |
| | 743 | IN UINTN Address,\r |
| | 744 | IN UINT32 Value\r |
| | 745 | );\r |
| | 746 | \r |
| | 747 | /**\r |
| | 748 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
| | 749 | a 32-bit value.\r |
| | 750 | \r |
| | 751 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| | 752 | bitwise OR between the read result and the value specified by\r |
| | 753 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| | 754 | specified by Address. The value written to the PCI configuration register is\r |
| | 755 | returned. This function must guarantee that all PCI read and write operations\r |
| | 756 | are serialized.\r |
| | 757 | \r |
| | 758 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 759 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 760 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 761 | \r |
| | 762 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 763 | Register.\r |
| | 764 | @param OrData The value to OR with the PCI configuration register.\r |
| | 765 | \r |
| | 766 | @return The value written back to the PCI configuration register.\r |
| | 767 | \r |
| | 768 | **/\r |
| | 769 | UINT32\r |
| | 770 | EFIAPI\r |
| | 771 | PciCf8Or32 (\r |
| | 772 | IN UINTN Address,\r |
| | 773 | IN UINT32 OrData\r |
| | 774 | );\r |
| | 775 | \r |
| | 776 | /**\r |
| | 777 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| | 778 | value.\r |
| | 779 | \r |
| | 780 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| | 781 | bitwise AND between the read result and the value specified by AndData, and\r |
| | 782 | writes the result to the 32-bit PCI configuration register specified by\r |
| | 783 | Address. The value written to the PCI configuration register is returned.\r |
| | 784 | This function must guarantee that all PCI read and write operations are\r |
| | 785 | serialized.\r |
| | 786 | \r |
| | 787 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 788 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 789 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 790 | \r |
| | 791 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 792 | Register.\r |
| | 793 | @param AndData The value to AND with the PCI configuration register.\r |
| | 794 | \r |
| | 795 | @return The value written back to the PCI configuration register.\r |
| | 796 | \r |
| | 797 | **/\r |
| | 798 | UINT32\r |
| | 799 | EFIAPI\r |
| | 800 | PciCf8And32 (\r |
| | 801 | IN UINTN Address,\r |
| | 802 | IN UINT32 AndData\r |
| | 803 | );\r |
| | 804 | \r |
| | 805 | /**\r |
| | 806 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| | 807 | value, followed a bitwise OR with another 32-bit value.\r |
| | 808 | \r |
| | 809 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| | 810 | bitwise AND between the read result and the value specified by AndData,\r |
| | 811 | performs a bitwise OR between the result of the AND operation and\r |
| | 812 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| | 813 | configuration register specified by Address. The value written to the PCI\r |
| | 814 | configuration register is returned. This function must guarantee that all PCI\r |
| | 815 | read and write operations are serialized.\r |
| | 816 | \r |
| | 817 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 818 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 819 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 820 | \r |
| | 821 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 822 | Register.\r |
| | 823 | @param AndData The value to AND with the PCI configuration register.\r |
| | 824 | @param OrData The value to OR with the result of the AND operation.\r |
| | 825 | \r |
| | 826 | @return The value written back to the PCI configuration register.\r |
| | 827 | \r |
| | 828 | **/\r |
| | 829 | UINT32\r |
| | 830 | EFIAPI\r |
| | 831 | PciCf8AndThenOr32 (\r |
| | 832 | IN UINTN Address,\r |
| | 833 | IN UINT32 AndData,\r |
| | 834 | IN UINT32 OrData\r |
| | 835 | );\r |
| | 836 | \r |
| | 837 | /**\r |
| | 838 | Reads a bit field of a PCI configuration register.\r |
| | 839 | \r |
| | 840 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| | 841 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| | 842 | returned.\r |
| | 843 | \r |
| | 844 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 845 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 846 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 847 | If StartBit is greater than 31, then ASSERT().\r |
| | 848 | If EndBit is greater than 31, then ASSERT().\r |
| | 849 | If EndBit is less than StartBit, then ASSERT().\r |
| | 850 | \r |
| | 851 | @param Address PCI configuration register to read.\r |
| | 852 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 853 | Range 0..31.\r |
| | 854 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 855 | Range 0..31.\r |
| | 856 | \r |
| | 857 | @return The value of the bit field read from the PCI configuration register.\r |
| | 858 | \r |
| | 859 | **/\r |
| | 860 | UINT32\r |
| | 861 | EFIAPI\r |
| | 862 | PciCf8BitFieldRead32 (\r |
| | 863 | IN UINTN Address,\r |
| | 864 | IN UINTN StartBit,\r |
| | 865 | IN UINTN EndBit\r |
| | 866 | );\r |
| | 867 | \r |
| | 868 | /**\r |
| | 869 | Writes a bit field to a PCI configuration register.\r |
| | 870 | \r |
| | 871 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| | 872 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| | 873 | destination PCI configuration register are preserved. The new value of the\r |
| | 874 | 32-bit register is returned.\r |
| | 875 | \r |
| | 876 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 877 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 878 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 879 | If StartBit is greater than 31, then ASSERT().\r |
| | 880 | If EndBit is greater than 31, then ASSERT().\r |
| | 881 | If EndBit is less than StartBit, then ASSERT().\r |
| | 882 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 883 | \r |
| | 884 | @param Address PCI configuration register to write.\r |
| | 885 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 886 | Range 0..31.\r |
| | 887 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 888 | Range 0..31.\r |
| | 889 | @param Value New value of the bit field.\r |
| | 890 | \r |
| | 891 | @return The value written back to the PCI configuration register.\r |
| | 892 | \r |
| | 893 | **/\r |
| | 894 | UINT32\r |
| | 895 | EFIAPI\r |
| | 896 | PciCf8BitFieldWrite32 (\r |
| | 897 | IN UINTN Address,\r |
| | 898 | IN UINTN StartBit,\r |
| | 899 | IN UINTN EndBit,\r |
| | 900 | IN UINT32 Value\r |
| | 901 | );\r |
| | 902 | \r |
| | 903 | /**\r |
| | 904 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| | 905 | writes the result back to the bit field in the 32-bit port.\r |
| | 906 | \r |
| | 907 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| | 908 | bitwise OR between the read result and the value specified by\r |
| | 909 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| | 910 | specified by Address. The value written to the PCI configuration register is\r |
| | 911 | returned. This function must guarantee that all PCI read and write operations\r |
| | 912 | are serialized. Extra left bits in OrData are stripped.\r |
| | 913 | \r |
| | 914 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 915 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 916 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 917 | If StartBit is greater than 31, then ASSERT().\r |
| | 918 | If EndBit is greater than 31, then ASSERT().\r |
| | 919 | If EndBit is less than StartBit, then ASSERT().\r |
| | 920 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 921 | \r |
| | 922 | @param Address PCI configuration register to write.\r |
| | 923 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 924 | Range 0..31.\r |
| | 925 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 926 | Range 0..31.\r |
| | 927 | @param OrData The value to OR with the PCI configuration register.\r |
| | 928 | \r |
| | 929 | @return The value written back to the PCI configuration register.\r |
| | 930 | \r |
| | 931 | **/\r |
| | 932 | UINT32\r |
| | 933 | EFIAPI\r |
| | 934 | PciCf8BitFieldOr32 (\r |
| | 935 | IN UINTN Address,\r |
| | 936 | IN UINTN StartBit,\r |
| | 937 | IN UINTN EndBit,\r |
| | 938 | IN UINT32 OrData\r |
| | 939 | );\r |
| | 940 | \r |
| | 941 | /**\r |
| | 942 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| | 943 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| | 944 | \r |
| | 945 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| | 946 | bitwise AND between the read result and the value specified by AndData, and\r |
| | 947 | writes the result to the 32-bit PCI configuration register specified by\r |
| | 948 | Address. The value written to the PCI configuration register is returned.\r |
| | 949 | This function must guarantee that all PCI read and write operations are\r |
| | 950 | serialized. Extra left bits in AndData are stripped.\r |
| | 951 | \r |
| | 952 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 953 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 954 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 955 | If StartBit is greater than 31, then ASSERT().\r |
| | 956 | If EndBit is greater than 31, then ASSERT().\r |
| | 957 | If EndBit is less than StartBit, then ASSERT().\r |
| | 958 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 959 | \r |
| | 960 | @param Address PCI configuration register to write.\r |
| | 961 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 962 | Range 0..31.\r |
| | 963 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 964 | Range 0..31.\r |
| | 965 | @param AndData The value to AND with the PCI configuration register.\r |
| | 966 | \r |
| | 967 | @return The value written back to the PCI configuration register.\r |
| | 968 | \r |
| | 969 | **/\r |
| | 970 | UINT32\r |
| | 971 | EFIAPI\r |
| | 972 | PciCf8BitFieldAnd32 (\r |
| | 973 | IN UINTN Address,\r |
| | 974 | IN UINTN StartBit,\r |
| | 975 | IN UINTN EndBit,\r |
| | 976 | IN UINT32 AndData\r |
| | 977 | );\r |
| | 978 | \r |
| | 979 | /**\r |
| | 980 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| | 981 | bitwise OR, and writes the result back to the bit field in the\r |
| | 982 | 32-bit port.\r |
| | 983 | \r |
| | 984 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| | 985 | bitwise AND followed by a bitwise OR between the read result and\r |
| | 986 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| | 987 | configuration register specified by Address. The value written to the PCI\r |
| | 988 | configuration register is returned. This function must guarantee that all PCI\r |
| | 989 | read and write operations are serialized. Extra left bits in both AndData and\r |
| | 990 | OrData are stripped.\r |
| | 991 | \r |
| | 992 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| | 993 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 994 | If the register specified by Address >= 0x100, then ASSERT().\r |
| | 995 | If StartBit is greater than 31, then ASSERT().\r |
| | 996 | If EndBit is greater than 31, then ASSERT().\r |
| | 997 | If EndBit is less than StartBit, then ASSERT().\r |
| | 998 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 999 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 1000 | \r |
| | 1001 | @param Address PCI configuration register to write.\r |
| | 1002 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 1003 | Range 0..31.\r |
| | 1004 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 1005 | Range 0..31.\r |
| | 1006 | @param AndData The value to AND with the PCI configuration register.\r |
| | 1007 | @param OrData The value to OR with the result of the AND operation.\r |
| | 1008 | \r |
| | 1009 | @return The value written back to the PCI configuration register.\r |
| | 1010 | \r |
| | 1011 | **/\r |
| | 1012 | UINT32\r |
| | 1013 | EFIAPI\r |
| | 1014 | PciCf8BitFieldAndThenOr32 (\r |
| | 1015 | IN UINTN Address,\r |
| | 1016 | IN UINTN StartBit,\r |
| | 1017 | IN UINTN EndBit,\r |
| | 1018 | IN UINT32 AndData,\r |
| | 1019 | IN UINT32 OrData\r |
| | 1020 | );\r |
| | 1021 | \r |
| | 1022 | /**\r |
| | 1023 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| | 1024 | \r |
| | 1025 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| | 1026 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| | 1027 | configuration registers from a single PCI function to be read. Size is\r |
| | 1028 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| | 1029 | from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| | 1030 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| | 1031 | end of the range.\r |
| | 1032 | \r |
| | 1033 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| | 1034 | If the register specified by StartAddress >= 0x100, then ASSERT().\r |
| | 1035 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r |
| | 1036 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| | 1037 | \r |
| | 1038 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| | 1039 | Function and Register.\r |
| | 1040 | @param Size Size in bytes of the transfer.\r |
| | 1041 | @param Buffer Pointer to a buffer receiving the data read.\r |
| | 1042 | \r |
| | 1043 | @return Size read from StartAddress.\r |
| | 1044 | \r |
| | 1045 | **/\r |
| | 1046 | UINTN\r |
| | 1047 | EFIAPI\r |
| | 1048 | PciCf8ReadBuffer (\r |
| | 1049 | IN UINTN StartAddress,\r |
| | 1050 | IN UINTN Size,\r |
| | 1051 | OUT VOID *Buffer\r |
| | 1052 | );\r |
| | 1053 | \r |
| | 1054 | /**\r |
| | 1055 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| | 1056 | configuration space.\r |
| | 1057 | \r |
| | 1058 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| | 1059 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| | 1060 | configuration registers from a single PCI function to be written. Size is\r |
| | 1061 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| | 1062 | write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r |
| | 1063 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| | 1064 | and the end of the range.\r |
| | 1065 | \r |
| | 1066 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| | 1067 | If the register specified by StartAddress >= 0x100, then ASSERT().\r |
| | 1068 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r |
| | 1069 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| | 1070 | \r |
| | 1071 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| | 1072 | Function and Register.\r |
| | 1073 | @param Size Size in bytes of the transfer.\r |
| | 1074 | @param Buffer Pointer to a buffer containing the data to write.\r |
| | 1075 | \r |
| | 1076 | @return Size written to StartAddress.\r |
| | 1077 | \r |
| | 1078 | **/\r |
| | 1079 | UINTN\r |
| | 1080 | EFIAPI\r |
| | 1081 | PciCf8WriteBuffer (\r |
| | 1082 | IN UINTN StartAddress,\r |
| | 1083 | IN UINTN Size,\r |
| | 1084 | IN VOID *Buffer\r |
| | 1085 | );\r |
| | 1086 | \r |
| | 1087 | #endif\r |
projects / mirror_edk2.git / blame_incremental