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1 | /** @file\r | |
2 | Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r | |
3 | \r | |
4 | The PCI Segment Library function provide services to read, write, and modify the PCI configuration\r | |
5 | registers on PCI root bridges on any supported PCI segment. These library services take a single\r | |
6 | address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.\r | |
7 | The layout of this address parameter is as follows:\r | |
8 | \r | |
9 | PCI Register: Bits 0..11\r | |
10 | PCI Function Bits 12..14\r | |
11 | PCI Device Bits 15..19\r | |
12 | PCI Bus Bits 20..27\r | |
13 | Reserved Bits 28..31. Must be 0.\r | |
14 | PCI Segment Bits 32..47\r | |
15 | Reserved Bits 48..63. Must be 0.\r | |
16 | \r | |
17 | | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r | |
18 | 63 48 47 32 31 28 27 20 19 15 14 12 11 0\r | |
19 | \r | |
20 | These functions perform PCI configuration cycles using the default PCI configuration access\r | |
21 | method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it\r | |
22 | may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate\r | |
23 | access method. Modules will typically use the PCI Segment Library for its PCI configuration\r | |
24 | accesses when PCI Segments other than Segment #0 must be accessed.\r | |
25 | \r | |
26 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
27 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
28 | \r | |
29 | **/\r | |
30 | \r | |
31 | #ifndef __PCI_SEGMENT_LIB__\r | |
32 | #define __PCI_SEGMENT_LIB__\r | |
33 | \r | |
34 | /**\r | |
35 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r | |
36 | and PCI Register to an address that can be passed to the PCI Segment Library functions.\r | |
37 | \r | |
38 | Computes an address that is compatible with the PCI Segment Library functions.\r | |
39 | The unused upper bits of Segment, Bus, Device, Function,\r | |
40 | and Register are stripped prior to the generation of the address.\r | |
41 | \r | |
42 | @param Segment PCI Segment number. Range 0..65535.\r | |
43 | @param Bus PCI Bus number. Range 0..255.\r | |
44 | @param Device PCI Device number. Range 0..31.\r | |
45 | @param Function PCI Function number. Range 0..7.\r | |
46 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r | |
47 | \r | |
48 | @return The address that is compatible with the PCI Segment Library functions.\r | |
49 | \r | |
50 | **/\r | |
51 | #define PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, Register) \\r | |
52 | ((Segment != 0) ? \\r | |
53 | ( ((Register) & 0xfff) | \\r | |
54 | (((Function) & 0x07) << 12) | \\r | |
55 | (((Device) & 0x1f) << 15) | \\r | |
56 | (((Bus) & 0xff) << 20) | \\r | |
57 | (LShiftU64 ((Segment) & 0xffff, 32)) \\r | |
58 | ) : \\r | |
59 | ( ((Register) & 0xfff) | \\r | |
60 | (((Function) & 0x07) << 12) | \\r | |
61 | (((Device) & 0x1f) << 15) | \\r | |
62 | (((Bus) & 0xff) << 20) \\r | |
63 | ) \\r | |
64 | )\r | |
65 | \r | |
66 | /**\r | |
67 | Register a PCI device so PCI configuration registers may be accessed after\r | |
68 | SetVirtualAddressMap().\r | |
69 | \r | |
70 | If any reserved bits in Address are set, then ASSERT().\r | |
71 | \r | |
72 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
73 | Register.\r | |
74 | \r | |
75 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
76 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r | |
77 | after ExitBootServices().\r | |
78 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
79 | at runtime could not be mapped.\r | |
80 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
81 | complete the registration.\r | |
82 | \r | |
83 | **/\r | |
84 | RETURN_STATUS\r | |
85 | EFIAPI\r | |
86 | PciSegmentRegisterForRuntimeAccess (\r | |
87 | IN UINTN Address\r | |
88 | );\r | |
89 | \r | |
90 | /**\r | |
91 | Reads an 8-bit PCI configuration register.\r | |
92 | \r | |
93 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
94 | This function must guarantee that all PCI read and write operations are serialized.\r | |
95 | \r | |
96 | If any reserved bits in Address are set, then ASSERT().\r | |
97 | \r | |
98 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
99 | \r | |
100 | @return The 8-bit PCI configuration register specified by Address.\r | |
101 | \r | |
102 | **/\r | |
103 | UINT8\r | |
104 | EFIAPI\r | |
105 | PciSegmentRead8 (\r | |
106 | IN UINT64 Address\r | |
107 | );\r | |
108 | \r | |
109 | /**\r | |
110 | Writes an 8-bit PCI configuration register.\r | |
111 | \r | |
112 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r | |
113 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
114 | \r | |
115 | If any reserved bits in Address are set, then ASSERT().\r | |
116 | \r | |
117 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
118 | @param Value The value to write.\r | |
119 | \r | |
120 | @return The value written to the PCI configuration register.\r | |
121 | \r | |
122 | **/\r | |
123 | UINT8\r | |
124 | EFIAPI\r | |
125 | PciSegmentWrite8 (\r | |
126 | IN UINT64 Address,\r | |
127 | IN UINT8 Value\r | |
128 | );\r | |
129 | \r | |
130 | /**\r | |
131 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r | |
132 | \r | |
133 | Reads the 8-bit PCI configuration register specified by Address,\r | |
134 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
135 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
136 | The value written to the PCI configuration register is returned.\r | |
137 | This function must guarantee that all PCI read and write operations are serialized.\r | |
138 | \r | |
139 | If any reserved bits in Address are set, then ASSERT().\r | |
140 | \r | |
141 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
142 | @param OrData The value to OR with the PCI configuration register.\r | |
143 | \r | |
144 | @return The value written to the PCI configuration register.\r | |
145 | \r | |
146 | **/\r | |
147 | UINT8\r | |
148 | EFIAPI\r | |
149 | PciSegmentOr8 (\r | |
150 | IN UINT64 Address,\r | |
151 | IN UINT8 OrData\r | |
152 | );\r | |
153 | \r | |
154 | /**\r | |
155 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r | |
156 | \r | |
157 | Reads the 8-bit PCI configuration register specified by Address,\r | |
158 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
159 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
160 | The value written to the PCI configuration register is returned.\r | |
161 | This function must guarantee that all PCI read and write operations are serialized.\r | |
162 | If any reserved bits in Address are set, then ASSERT().\r | |
163 | \r | |
164 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
165 | @param AndData The value to AND with the PCI configuration register.\r | |
166 | \r | |
167 | @return The value written to the PCI configuration register.\r | |
168 | \r | |
169 | **/\r | |
170 | UINT8\r | |
171 | EFIAPI\r | |
172 | PciSegmentAnd8 (\r | |
173 | IN UINT64 Address,\r | |
174 | IN UINT8 AndData\r | |
175 | );\r | |
176 | \r | |
177 | /**\r | |
178 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r | |
179 | followed a bitwise OR with another 8-bit value.\r | |
180 | \r | |
181 | Reads the 8-bit PCI configuration register specified by Address,\r | |
182 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
183 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
184 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
185 | The value written to the PCI configuration register is returned.\r | |
186 | This function must guarantee that all PCI read and write operations are serialized.\r | |
187 | \r | |
188 | If any reserved bits in Address are set, then ASSERT().\r | |
189 | \r | |
190 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
191 | @param AndData The value to AND with the PCI configuration register.\r | |
192 | @param OrData The value to OR with the PCI configuration register.\r | |
193 | \r | |
194 | @return The value written to the PCI configuration register.\r | |
195 | \r | |
196 | **/\r | |
197 | UINT8\r | |
198 | EFIAPI\r | |
199 | PciSegmentAndThenOr8 (\r | |
200 | IN UINT64 Address,\r | |
201 | IN UINT8 AndData,\r | |
202 | IN UINT8 OrData\r | |
203 | );\r | |
204 | \r | |
205 | /**\r | |
206 | Reads a bit field of a PCI configuration register.\r | |
207 | \r | |
208 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
209 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
210 | returned.\r | |
211 | \r | |
212 | If any reserved bits in Address are set, then ASSERT().\r | |
213 | If StartBit is greater than 7, then ASSERT().\r | |
214 | If EndBit is greater than 7, then ASSERT().\r | |
215 | If EndBit is less than StartBit, then ASSERT().\r | |
216 | \r | |
217 | @param Address PCI configuration register to read.\r | |
218 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
219 | Range 0..7.\r | |
220 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
221 | Range 0..7.\r | |
222 | \r | |
223 | @return The value of the bit field read from the PCI configuration register.\r | |
224 | \r | |
225 | **/\r | |
226 | UINT8\r | |
227 | EFIAPI\r | |
228 | PciSegmentBitFieldRead8 (\r | |
229 | IN UINT64 Address,\r | |
230 | IN UINTN StartBit,\r | |
231 | IN UINTN EndBit\r | |
232 | );\r | |
233 | \r | |
234 | /**\r | |
235 | Writes a bit field to a PCI configuration register.\r | |
236 | \r | |
237 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
238 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
239 | destination PCI configuration register are preserved. The new value of the\r | |
240 | 8-bit register is returned.\r | |
241 | \r | |
242 | If any reserved bits in Address are set, then ASSERT().\r | |
243 | If StartBit is greater than 7, then ASSERT().\r | |
244 | If EndBit is greater than 7, then ASSERT().\r | |
245 | If EndBit is less than StartBit, then ASSERT().\r | |
246 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
247 | \r | |
248 | @param Address PCI configuration register to write.\r | |
249 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
250 | Range 0..7.\r | |
251 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
252 | Range 0..7.\r | |
253 | @param Value New value of the bit field.\r | |
254 | \r | |
255 | @return The value written back to the PCI configuration register.\r | |
256 | \r | |
257 | **/\r | |
258 | UINT8\r | |
259 | EFIAPI\r | |
260 | PciSegmentBitFieldWrite8 (\r | |
261 | IN UINT64 Address,\r | |
262 | IN UINTN StartBit,\r | |
263 | IN UINTN EndBit,\r | |
264 | IN UINT8 Value\r | |
265 | );\r | |
266 | \r | |
267 | /**\r | |
268 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
269 | writes the result back to the bit field in the 8-bit port.\r | |
270 | \r | |
271 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
272 | bitwise OR between the read result and the value specified by\r | |
273 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
274 | specified by Address. The value written to the PCI configuration register is\r | |
275 | returned. This function must guarantee that all PCI read and write operations\r | |
276 | are serialized. Extra left bits in OrData are stripped.\r | |
277 | \r | |
278 | If any reserved bits in Address are set, then ASSERT().\r | |
279 | If StartBit is greater than 7, then ASSERT().\r | |
280 | If EndBit is greater than 7, then ASSERT().\r | |
281 | If EndBit is less than StartBit, then ASSERT().\r | |
282 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
283 | \r | |
284 | @param Address PCI configuration register to write.\r | |
285 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
286 | Range 0..7.\r | |
287 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
288 | Range 0..7.\r | |
289 | @param OrData The value to OR with the PCI configuration register.\r | |
290 | \r | |
291 | @return The value written back to the PCI configuration register.\r | |
292 | \r | |
293 | **/\r | |
294 | UINT8\r | |
295 | EFIAPI\r | |
296 | PciSegmentBitFieldOr8 (\r | |
297 | IN UINT64 Address,\r | |
298 | IN UINTN StartBit,\r | |
299 | IN UINTN EndBit,\r | |
300 | IN UINT8 OrData\r | |
301 | );\r | |
302 | \r | |
303 | /**\r | |
304 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
305 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
306 | \r | |
307 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
308 | bitwise AND between the read result and the value specified by AndData, and\r | |
309 | writes the result to the 8-bit PCI configuration register specified by\r | |
310 | Address. The value written to the PCI configuration register is returned.\r | |
311 | This function must guarantee that all PCI read and write operations are\r | |
312 | serialized. Extra left bits in AndData are stripped.\r | |
313 | \r | |
314 | If any reserved bits in Address are set, then ASSERT().\r | |
315 | If StartBit is greater than 7, then ASSERT().\r | |
316 | If EndBit is greater than 7, then ASSERT().\r | |
317 | If EndBit is less than StartBit, then ASSERT().\r | |
318 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
319 | \r | |
320 | @param Address PCI configuration register to write.\r | |
321 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
322 | Range 0..7.\r | |
323 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
324 | Range 0..7.\r | |
325 | @param AndData The value to AND with the PCI configuration register.\r | |
326 | \r | |
327 | @return The value written back to the PCI configuration register.\r | |
328 | \r | |
329 | **/\r | |
330 | UINT8\r | |
331 | EFIAPI\r | |
332 | PciSegmentBitFieldAnd8 (\r | |
333 | IN UINT64 Address,\r | |
334 | IN UINTN StartBit,\r | |
335 | IN UINTN EndBit,\r | |
336 | IN UINT8 AndData\r | |
337 | );\r | |
338 | \r | |
339 | /**\r | |
340 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
341 | bitwise OR, and writes the result back to the bit field in the 8-bit port.\r | |
342 | \r | |
343 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
344 | bitwise AND followed by a bitwise OR between the read result and\r | |
345 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
346 | configuration register specified by Address. The value written to the PCI\r | |
347 | configuration register is returned. This function must guarantee that all PCI\r | |
348 | read and write operations are serialized. Extra left bits in both AndData and\r | |
349 | OrData are stripped.\r | |
350 | \r | |
351 | If any reserved bits in Address are set, then ASSERT().\r | |
352 | If StartBit is greater than 7, then ASSERT().\r | |
353 | If EndBit is greater than 7, then ASSERT().\r | |
354 | If EndBit is less than StartBit, then ASSERT().\r | |
355 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
356 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
357 | \r | |
358 | @param Address PCI configuration register to write.\r | |
359 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
360 | Range 0..7.\r | |
361 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
362 | Range 0..7.\r | |
363 | @param AndData The value to AND with the PCI configuration register.\r | |
364 | @param OrData The value to OR with the result of the AND operation.\r | |
365 | \r | |
366 | @return The value written back to the PCI configuration register.\r | |
367 | \r | |
368 | **/\r | |
369 | UINT8\r | |
370 | EFIAPI\r | |
371 | PciSegmentBitFieldAndThenOr8 (\r | |
372 | IN UINT64 Address,\r | |
373 | IN UINTN StartBit,\r | |
374 | IN UINTN EndBit,\r | |
375 | IN UINT8 AndData,\r | |
376 | IN UINT8 OrData\r | |
377 | );\r | |
378 | \r | |
379 | /**\r | |
380 | Reads a 16-bit PCI configuration register.\r | |
381 | \r | |
382 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
383 | This function must guarantee that all PCI read and write operations are serialized.\r | |
384 | \r | |
385 | If any reserved bits in Address are set, then ASSERT().\r | |
386 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
387 | \r | |
388 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
389 | \r | |
390 | @return The 16-bit PCI configuration register specified by Address.\r | |
391 | \r | |
392 | **/\r | |
393 | UINT16\r | |
394 | EFIAPI\r | |
395 | PciSegmentRead16 (\r | |
396 | IN UINT64 Address\r | |
397 | );\r | |
398 | \r | |
399 | /**\r | |
400 | Writes a 16-bit PCI configuration register.\r | |
401 | \r | |
402 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r | |
403 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
404 | \r | |
405 | If any reserved bits in Address are set, then ASSERT().\r | |
406 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
407 | \r | |
408 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
409 | @param Value The value to write.\r | |
410 | \r | |
411 | @return The parameter of Value.\r | |
412 | \r | |
413 | **/\r | |
414 | UINT16\r | |
415 | EFIAPI\r | |
416 | PciSegmentWrite16 (\r | |
417 | IN UINT64 Address,\r | |
418 | IN UINT16 Value\r | |
419 | );\r | |
420 | \r | |
421 | /**\r | |
422 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
423 | a 16-bit value.\r | |
424 | \r | |
425 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
426 | bitwise OR between the read result and the value specified by OrData, and\r | |
427 | writes the result to the 16-bit PCI configuration register specified by Address.\r | |
428 | The value written to the PCI configuration register is returned. This function\r | |
429 | must guarantee that all PCI read and write operations are serialized.\r | |
430 | \r | |
431 | If any reserved bits in Address are set, then ASSERT().\r | |
432 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
433 | \r | |
434 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
435 | Register.\r | |
436 | @param OrData The value to OR with the PCI configuration register.\r | |
437 | \r | |
438 | @return The value written back to the PCI configuration register.\r | |
439 | \r | |
440 | **/\r | |
441 | UINT16\r | |
442 | EFIAPI\r | |
443 | PciSegmentOr16 (\r | |
444 | IN UINT64 Address,\r | |
445 | IN UINT16 OrData\r | |
446 | );\r | |
447 | \r | |
448 | /**\r | |
449 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r | |
450 | \r | |
451 | Reads the 16-bit PCI configuration register specified by Address,\r | |
452 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
453 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
454 | The value written to the PCI configuration register is returned.\r | |
455 | This function must guarantee that all PCI read and write operations are serialized.\r | |
456 | \r | |
457 | If any reserved bits in Address are set, then ASSERT().\r | |
458 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
459 | \r | |
460 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
461 | @param AndData The value to AND with the PCI configuration register.\r | |
462 | \r | |
463 | @return The value written to the PCI configuration register.\r | |
464 | \r | |
465 | **/\r | |
466 | UINT16\r | |
467 | EFIAPI\r | |
468 | PciSegmentAnd16 (\r | |
469 | IN UINT64 Address,\r | |
470 | IN UINT16 AndData\r | |
471 | );\r | |
472 | \r | |
473 | /**\r | |
474 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r | |
475 | followed a bitwise OR with another 16-bit value.\r | |
476 | \r | |
477 | Reads the 16-bit PCI configuration register specified by Address,\r | |
478 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
479 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
480 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
481 | The value written to the PCI configuration register is returned.\r | |
482 | This function must guarantee that all PCI read and write operations are serialized.\r | |
483 | \r | |
484 | If any reserved bits in Address are set, then ASSERT().\r | |
485 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
486 | \r | |
487 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
488 | @param AndData The value to AND with the PCI configuration register.\r | |
489 | @param OrData The value to OR with the PCI configuration register.\r | |
490 | \r | |
491 | @return The value written to the PCI configuration register.\r | |
492 | \r | |
493 | **/\r | |
494 | UINT16\r | |
495 | EFIAPI\r | |
496 | PciSegmentAndThenOr16 (\r | |
497 | IN UINT64 Address,\r | |
498 | IN UINT16 AndData,\r | |
499 | IN UINT16 OrData\r | |
500 | );\r | |
501 | \r | |
502 | /**\r | |
503 | Reads a bit field of a PCI configuration register.\r | |
504 | \r | |
505 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
506 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
507 | returned.\r | |
508 | \r | |
509 | If any reserved bits in Address are set, then ASSERT().\r | |
510 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
511 | If StartBit is greater than 15, then ASSERT().\r | |
512 | If EndBit is greater than 15, then ASSERT().\r | |
513 | If EndBit is less than StartBit, then ASSERT().\r | |
514 | \r | |
515 | @param Address PCI configuration register to read.\r | |
516 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
517 | Range 0..15.\r | |
518 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
519 | Range 0..15.\r | |
520 | \r | |
521 | @return The value of the bit field read from the PCI configuration register.\r | |
522 | \r | |
523 | **/\r | |
524 | UINT16\r | |
525 | EFIAPI\r | |
526 | PciSegmentBitFieldRead16 (\r | |
527 | IN UINT64 Address,\r | |
528 | IN UINTN StartBit,\r | |
529 | IN UINTN EndBit\r | |
530 | );\r | |
531 | \r | |
532 | /**\r | |
533 | Writes a bit field to a PCI configuration register.\r | |
534 | \r | |
535 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
536 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
537 | destination PCI configuration register are preserved. The new value of the\r | |
538 | 16-bit register is returned.\r | |
539 | \r | |
540 | If any reserved bits in Address are set, then ASSERT().\r | |
541 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
542 | If StartBit is greater than 15, then ASSERT().\r | |
543 | If EndBit is greater than 15, then ASSERT().\r | |
544 | If EndBit is less than StartBit, then ASSERT().\r | |
545 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
546 | \r | |
547 | @param Address PCI configuration register to write.\r | |
548 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
549 | Range 0..15.\r | |
550 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
551 | Range 0..15.\r | |
552 | @param Value New value of the bit field.\r | |
553 | \r | |
554 | @return The value written back to the PCI configuration register.\r | |
555 | \r | |
556 | **/\r | |
557 | UINT16\r | |
558 | EFIAPI\r | |
559 | PciSegmentBitFieldWrite16 (\r | |
560 | IN UINT64 Address,\r | |
561 | IN UINTN StartBit,\r | |
562 | IN UINTN EndBit,\r | |
563 | IN UINT16 Value\r | |
564 | );\r | |
565 | \r | |
566 | /**\r | |
567 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r | |
568 | the result back to the bit field in the 16-bit port.\r | |
569 | \r | |
570 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
571 | bitwise OR between the read result and the value specified by\r | |
572 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
573 | specified by Address. The value written to the PCI configuration register is\r | |
574 | returned. This function must guarantee that all PCI read and write operations\r | |
575 | are serialized. Extra left bits in OrData are stripped.\r | |
576 | \r | |
577 | If any reserved bits in Address are set, then ASSERT().\r | |
578 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
579 | If StartBit is greater than 15, then ASSERT().\r | |
580 | If EndBit is greater than 15, then ASSERT().\r | |
581 | If EndBit is less than StartBit, then ASSERT().\r | |
582 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
583 | \r | |
584 | @param Address PCI configuration register to write.\r | |
585 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
586 | Range 0..15.\r | |
587 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
588 | Range 0..15.\r | |
589 | @param OrData The value to OR with the PCI configuration register.\r | |
590 | \r | |
591 | @return The value written back to the PCI configuration register.\r | |
592 | \r | |
593 | **/\r | |
594 | UINT16\r | |
595 | EFIAPI\r | |
596 | PciSegmentBitFieldOr16 (\r | |
597 | IN UINT64 Address,\r | |
598 | IN UINTN StartBit,\r | |
599 | IN UINTN EndBit,\r | |
600 | IN UINT16 OrData\r | |
601 | );\r | |
602 | \r | |
603 | /**\r | |
604 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
605 | AND, writes the result back to the bit field in the 16-bit register.\r | |
606 | \r | |
607 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
608 | bitwise AND between the read result and the value specified by AndData, and\r | |
609 | writes the result to the 16-bit PCI configuration register specified by\r | |
610 | Address. The value written to the PCI configuration register is returned.\r | |
611 | This function must guarantee that all PCI read and write operations are\r | |
612 | serialized. Extra left bits in AndData are stripped.\r | |
613 | \r | |
614 | If any reserved bits in Address are set, then ASSERT().\r | |
615 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
616 | If StartBit is greater than 15, then ASSERT().\r | |
617 | If EndBit is greater than 15, then ASSERT().\r | |
618 | If EndBit is less than StartBit, then ASSERT().\r | |
619 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
620 | \r | |
621 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
622 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
623 | Range 0..15.\r | |
624 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
625 | Range 0..15.\r | |
626 | @param AndData The value to AND with the PCI configuration register.\r | |
627 | \r | |
628 | @return The value written back to the PCI configuration register.\r | |
629 | \r | |
630 | **/\r | |
631 | UINT16\r | |
632 | EFIAPI\r | |
633 | PciSegmentBitFieldAnd16 (\r | |
634 | IN UINT64 Address,\r | |
635 | IN UINTN StartBit,\r | |
636 | IN UINTN EndBit,\r | |
637 | IN UINT16 AndData\r | |
638 | );\r | |
639 | \r | |
640 | /**\r | |
641 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
642 | bitwise OR, and writes the result back to the bit field in the\r | |
643 | 16-bit port.\r | |
644 | \r | |
645 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
646 | bitwise AND followed by a bitwise OR between the read result and\r | |
647 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
648 | configuration register specified by Address. The value written to the PCI\r | |
649 | configuration register is returned. This function must guarantee that all PCI\r | |
650 | read and write operations are serialized. Extra left bits in both AndData and\r | |
651 | OrData are stripped.\r | |
652 | \r | |
653 | If any reserved bits in Address are set, then ASSERT().\r | |
654 | If StartBit is greater than 15, then ASSERT().\r | |
655 | If EndBit is greater than 15, then ASSERT().\r | |
656 | If EndBit is less than StartBit, then ASSERT().\r | |
657 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
658 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
659 | \r | |
660 | @param Address PCI configuration register to write.\r | |
661 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
662 | Range 0..15.\r | |
663 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
664 | Range 0..15.\r | |
665 | @param AndData The value to AND with the PCI configuration register.\r | |
666 | @param OrData The value to OR with the result of the AND operation.\r | |
667 | \r | |
668 | @return The value written back to the PCI configuration register.\r | |
669 | \r | |
670 | **/\r | |
671 | UINT16\r | |
672 | EFIAPI\r | |
673 | PciSegmentBitFieldAndThenOr16 (\r | |
674 | IN UINT64 Address,\r | |
675 | IN UINTN StartBit,\r | |
676 | IN UINTN EndBit,\r | |
677 | IN UINT16 AndData,\r | |
678 | IN UINT16 OrData\r | |
679 | );\r | |
680 | \r | |
681 | /**\r | |
682 | Reads a 32-bit PCI configuration register.\r | |
683 | \r | |
684 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
685 | This function must guarantee that all PCI read and write operations are serialized.\r | |
686 | \r | |
687 | If any reserved bits in Address are set, then ASSERT().\r | |
688 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
689 | \r | |
690 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
691 | \r | |
692 | @return The 32-bit PCI configuration register specified by Address.\r | |
693 | \r | |
694 | **/\r | |
695 | UINT32\r | |
696 | EFIAPI\r | |
697 | PciSegmentRead32 (\r | |
698 | IN UINT64 Address\r | |
699 | );\r | |
700 | \r | |
701 | /**\r | |
702 | Writes a 32-bit PCI configuration register.\r | |
703 | \r | |
704 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r | |
705 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
706 | \r | |
707 | If any reserved bits in Address are set, then ASSERT().\r | |
708 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
709 | \r | |
710 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
711 | @param Value The value to write.\r | |
712 | \r | |
713 | @return The parameter of Value.\r | |
714 | \r | |
715 | **/\r | |
716 | UINT32\r | |
717 | EFIAPI\r | |
718 | PciSegmentWrite32 (\r | |
719 | IN UINT64 Address,\r | |
720 | IN UINT32 Value\r | |
721 | );\r | |
722 | \r | |
723 | /**\r | |
724 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r | |
725 | \r | |
726 | Reads the 32-bit PCI configuration register specified by Address,\r | |
727 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
728 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
729 | The value written to the PCI configuration register is returned.\r | |
730 | This function must guarantee that all PCI read and write operations are serialized.\r | |
731 | \r | |
732 | If any reserved bits in Address are set, then ASSERT().\r | |
733 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
734 | \r | |
735 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
736 | @param OrData The value to OR with the PCI configuration register.\r | |
737 | \r | |
738 | @return The value written to the PCI configuration register.\r | |
739 | \r | |
740 | **/\r | |
741 | UINT32\r | |
742 | EFIAPI\r | |
743 | PciSegmentOr32 (\r | |
744 | IN UINT64 Address,\r | |
745 | IN UINT32 OrData\r | |
746 | );\r | |
747 | \r | |
748 | /**\r | |
749 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r | |
750 | \r | |
751 | Reads the 32-bit PCI configuration register specified by Address,\r | |
752 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
753 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
754 | The value written to the PCI configuration register is returned.\r | |
755 | This function must guarantee that all PCI read and write operations are serialized.\r | |
756 | \r | |
757 | If any reserved bits in Address are set, then ASSERT().\r | |
758 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
759 | \r | |
760 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
761 | @param AndData The value to AND with the PCI configuration register.\r | |
762 | \r | |
763 | @return The value written to the PCI configuration register.\r | |
764 | \r | |
765 | **/\r | |
766 | UINT32\r | |
767 | EFIAPI\r | |
768 | PciSegmentAnd32 (\r | |
769 | IN UINT64 Address,\r | |
770 | IN UINT32 AndData\r | |
771 | );\r | |
772 | \r | |
773 | /**\r | |
774 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r | |
775 | followed a bitwise OR with another 32-bit value.\r | |
776 | \r | |
777 | Reads the 32-bit PCI configuration register specified by Address,\r | |
778 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
779 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
780 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
781 | The value written to the PCI configuration register is returned.\r | |
782 | This function must guarantee that all PCI read and write operations are serialized.\r | |
783 | \r | |
784 | If any reserved bits in Address are set, then ASSERT().\r | |
785 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
786 | \r | |
787 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
788 | @param AndData The value to AND with the PCI configuration register.\r | |
789 | @param OrData The value to OR with the PCI configuration register.\r | |
790 | \r | |
791 | @return The value written to the PCI configuration register.\r | |
792 | \r | |
793 | **/\r | |
794 | UINT32\r | |
795 | EFIAPI\r | |
796 | PciSegmentAndThenOr32 (\r | |
797 | IN UINT64 Address,\r | |
798 | IN UINT32 AndData,\r | |
799 | IN UINT32 OrData\r | |
800 | );\r | |
801 | \r | |
802 | /**\r | |
803 | Reads a bit field of a PCI configuration register.\r | |
804 | \r | |
805 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
806 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
807 | returned.\r | |
808 | \r | |
809 | If any reserved bits in Address are set, then ASSERT().\r | |
810 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
811 | If StartBit is greater than 31, then ASSERT().\r | |
812 | If EndBit is greater than 31, then ASSERT().\r | |
813 | If EndBit is less than StartBit, then ASSERT().\r | |
814 | \r | |
815 | @param Address PCI configuration register to read.\r | |
816 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
817 | Range 0..31.\r | |
818 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
819 | Range 0..31.\r | |
820 | \r | |
821 | @return The value of the bit field read from the PCI configuration register.\r | |
822 | \r | |
823 | **/\r | |
824 | UINT32\r | |
825 | EFIAPI\r | |
826 | PciSegmentBitFieldRead32 (\r | |
827 | IN UINT64 Address,\r | |
828 | IN UINTN StartBit,\r | |
829 | IN UINTN EndBit\r | |
830 | );\r | |
831 | \r | |
832 | /**\r | |
833 | Writes a bit field to a PCI configuration register.\r | |
834 | \r | |
835 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
836 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
837 | destination PCI configuration register are preserved. The new value of the\r | |
838 | 32-bit register is returned.\r | |
839 | \r | |
840 | If any reserved bits in Address are set, then ASSERT().\r | |
841 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
842 | If StartBit is greater than 31, then ASSERT().\r | |
843 | If EndBit is greater than 31, then ASSERT().\r | |
844 | If EndBit is less than StartBit, then ASSERT().\r | |
845 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
846 | \r | |
847 | @param Address PCI configuration register to write.\r | |
848 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
849 | Range 0..31.\r | |
850 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
851 | Range 0..31.\r | |
852 | @param Value New value of the bit field.\r | |
853 | \r | |
854 | @return The value written back to the PCI configuration register.\r | |
855 | \r | |
856 | **/\r | |
857 | UINT32\r | |
858 | EFIAPI\r | |
859 | PciSegmentBitFieldWrite32 (\r | |
860 | IN UINT64 Address,\r | |
861 | IN UINTN StartBit,\r | |
862 | IN UINTN EndBit,\r | |
863 | IN UINT32 Value\r | |
864 | );\r | |
865 | \r | |
866 | /**\r | |
867 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
868 | writes the result back to the bit field in the 32-bit port.\r | |
869 | \r | |
870 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
871 | bitwise OR between the read result and the value specified by\r | |
872 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
873 | specified by Address. The value written to the PCI configuration register is\r | |
874 | returned. This function must guarantee that all PCI read and write operations\r | |
875 | are serialized. Extra left bits in OrData are stripped.\r | |
876 | \r | |
877 | If any reserved bits in Address are set, then ASSERT().\r | |
878 | If StartBit is greater than 31, then ASSERT().\r | |
879 | If EndBit is greater than 31, then ASSERT().\r | |
880 | If EndBit is less than StartBit, then ASSERT().\r | |
881 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
882 | \r | |
883 | @param Address PCI configuration register to write.\r | |
884 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
885 | Range 0..31.\r | |
886 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
887 | Range 0..31.\r | |
888 | @param OrData The value to OR with the PCI configuration register.\r | |
889 | \r | |
890 | @return The value written back to the PCI configuration register.\r | |
891 | \r | |
892 | **/\r | |
893 | UINT32\r | |
894 | EFIAPI\r | |
895 | PciSegmentBitFieldOr32 (\r | |
896 | IN UINT64 Address,\r | |
897 | IN UINTN StartBit,\r | |
898 | IN UINTN EndBit,\r | |
899 | IN UINT32 OrData\r | |
900 | );\r | |
901 | \r | |
902 | /**\r | |
903 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
904 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
905 | \r | |
906 | \r | |
907 | Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r | |
908 | AND between the read result and the value specified by AndData, and writes the result\r | |
909 | to the 32-bit PCI configuration register specified by Address. The value written to\r | |
910 | the PCI configuration register is returned. This function must guarantee that all PCI\r | |
911 | read and write operations are serialized. Extra left bits in AndData are stripped.\r | |
912 | If any reserved bits in Address are set, then ASSERT().\r | |
913 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
914 | If StartBit is greater than 31, then ASSERT().\r | |
915 | If EndBit is greater than 31, then ASSERT().\r | |
916 | If EndBit is less than StartBit, then ASSERT().\r | |
917 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
918 | \r | |
919 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
920 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
921 | Range 0..31.\r | |
922 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
923 | Range 0..31.\r | |
924 | @param AndData The value to AND with the PCI configuration register.\r | |
925 | \r | |
926 | @return The value written back to the PCI configuration register.\r | |
927 | \r | |
928 | **/\r | |
929 | UINT32\r | |
930 | EFIAPI\r | |
931 | PciSegmentBitFieldAnd32 (\r | |
932 | IN UINT64 Address,\r | |
933 | IN UINTN StartBit,\r | |
934 | IN UINTN EndBit,\r | |
935 | IN UINT32 AndData\r | |
936 | );\r | |
937 | \r | |
938 | /**\r | |
939 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
940 | bitwise OR, and writes the result back to the bit field in the\r | |
941 | 32-bit port.\r | |
942 | \r | |
943 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
944 | bitwise AND followed by a bitwise OR between the read result and\r | |
945 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
946 | configuration register specified by Address. The value written to the PCI\r | |
947 | configuration register is returned. This function must guarantee that all PCI\r | |
948 | read and write operations are serialized. Extra left bits in both AndData and\r | |
949 | OrData are stripped.\r | |
950 | \r | |
951 | If any reserved bits in Address are set, then ASSERT().\r | |
952 | If StartBit is greater than 31, then ASSERT().\r | |
953 | If EndBit is greater than 31, then ASSERT().\r | |
954 | If EndBit is less than StartBit, then ASSERT().\r | |
955 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
956 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
957 | \r | |
958 | @param Address PCI configuration register to write.\r | |
959 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
960 | Range 0..31.\r | |
961 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
962 | Range 0..31.\r | |
963 | @param AndData The value to AND with the PCI configuration register.\r | |
964 | @param OrData The value to OR with the result of the AND operation.\r | |
965 | \r | |
966 | @return The value written back to the PCI configuration register.\r | |
967 | \r | |
968 | **/\r | |
969 | UINT32\r | |
970 | EFIAPI\r | |
971 | PciSegmentBitFieldAndThenOr32 (\r | |
972 | IN UINT64 Address,\r | |
973 | IN UINTN StartBit,\r | |
974 | IN UINTN EndBit,\r | |
975 | IN UINT32 AndData,\r | |
976 | IN UINT32 OrData\r | |
977 | );\r | |
978 | \r | |
979 | /**\r | |
980 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
981 | \r | |
982 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
983 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
984 | configuration registers from a single PCI function to be read. Size is\r | |
985 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
986 | from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
987 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
988 | end of the range.\r | |
989 | \r | |
990 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
991 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
992 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
993 | \r | |
994 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
995 | Function and Register.\r | |
996 | @param Size Size in bytes of the transfer.\r | |
997 | @param Buffer Pointer to a buffer receiving the data read.\r | |
998 | \r | |
999 | @return Size\r | |
1000 | \r | |
1001 | **/\r | |
1002 | UINTN\r | |
1003 | EFIAPI\r | |
1004 | PciSegmentReadBuffer (\r | |
1005 | IN UINT64 StartAddress,\r | |
1006 | IN UINTN Size,\r | |
1007 | OUT VOID *Buffer\r | |
1008 | );\r | |
1009 | \r | |
1010 | /**\r | |
1011 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1012 | configuration space.\r | |
1013 | \r | |
1014 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1015 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1016 | configuration registers from a single PCI function to be written. Size is\r | |
1017 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1018 | write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r | |
1019 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1020 | and the end of the range.\r | |
1021 | \r | |
1022 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1023 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1024 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1025 | \r | |
1026 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1027 | Function and Register.\r | |
1028 | @param Size Size in bytes of the transfer.\r | |
1029 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1030 | \r | |
1031 | @return The parameter of Size.\r | |
1032 | \r | |
1033 | **/\r | |
1034 | UINTN\r | |
1035 | EFIAPI\r | |
1036 | PciSegmentWriteBuffer (\r | |
1037 | IN UINT64 StartAddress,\r | |
1038 | IN UINTN Size,\r | |
1039 | IN VOID *Buffer\r | |
1040 | );\r | |
1041 | \r | |
1042 | #endif\r |