]>
Commit | Line | Data |
---|---|---|
1 | /** @file\r | |
2 | Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r | |
3 | \r | |
4 | The PCI Segment Library function provide services to read, write, and modify the PCI configuration\r | |
5 | registers on PCI root bridges on any supported PCI segment. These library services take a single \r | |
6 | address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register. \r | |
7 | The layout of this address parameter is as follows:\r | |
8 | \r | |
9 | PCI Register: Bits 0..11\r | |
10 | PCI Function Bits 12..14\r | |
11 | PCI Device Bits 15..19\r | |
12 | PCI Bus Bits 20..27\r | |
13 | Reserved Bits 28..31. Must be 0.\r | |
14 | PCI Segment Bits 32..47\r | |
15 | Reserved Bits 48..63. Must be 0.\r | |
16 | \r | |
17 | | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r | |
18 | 63 48 47 32 31 28 27 20 19 15 14 12 11 0\r | |
19 | \r | |
20 | These functions perform PCI configuration cycles using the default PCI configuration access \r | |
21 | method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it \r | |
22 | may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate \r | |
23 | access method. Modules will typically use the PCI Segment Library for its PCI configuration \r | |
24 | accesses when PCI Segments other than Segment #0 must be accessed. \r | |
25 | \r | |
26 | Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r | |
27 | This program and the accompanying materials\r | |
28 | are licensed and made available under the terms and conditions of the BSD License\r | |
29 | which accompanies this distribution. The full text of the license may be found at\r | |
30 | http://opensource.org/licenses/bsd-license.php\r | |
31 | \r | |
32 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
33 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
34 | \r | |
35 | **/\r | |
36 | \r | |
37 | #ifndef __PCI_SEGMENT_LIB__\r | |
38 | #define __PCI_SEGMENT_LIB__\r | |
39 | \r | |
40 | \r | |
41 | /**\r | |
42 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r | |
43 | and PCI Register to an address that can be passed to the PCI Segment Library functions.\r | |
44 | \r | |
45 | Computes an address that is compatible with the PCI Segment Library functions.\r | |
46 | The unused upper bits of Segment, Bus, Device, Function,\r | |
47 | and Register are stripped prior to the generation of the address.\r | |
48 | \r | |
49 | @param Segment PCI Segment number. Range 0..65535.\r | |
50 | @param Bus PCI Bus number. Range 0..255.\r | |
51 | @param Device PCI Device number. Range 0..31.\r | |
52 | @param Function PCI Function number. Range 0..7.\r | |
53 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r | |
54 | \r | |
55 | @return The address that is compatible with the PCI Segment Library functions.\r | |
56 | \r | |
57 | **/\r | |
58 | #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r | |
59 | ((Segment != 0) ? \\r | |
60 | ( ((Register) & 0xfff) | \\r | |
61 | (((Function) & 0x07) << 12) | \\r | |
62 | (((Device) & 0x1f) << 15) | \\r | |
63 | (((Bus) & 0xff) << 20) | \\r | |
64 | (LShiftU64 ((Segment) & 0xffff, 32)) \\r | |
65 | ) : \\r | |
66 | ( ((Register) & 0xfff) | \\r | |
67 | (((Function) & 0x07) << 12) | \\r | |
68 | (((Device) & 0x1f) << 15) | \\r | |
69 | (((Bus) & 0xff) << 20) \\r | |
70 | ) \\r | |
71 | )\r | |
72 | \r | |
73 | /**\r | |
74 | Register a PCI device so PCI configuration registers may be accessed after \r | |
75 | SetVirtualAddressMap().\r | |
76 | \r | |
77 | If any reserved bits in Address are set, then ASSERT().\r | |
78 | \r | |
79 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
80 | Register.\r | |
81 | \r | |
82 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
83 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
84 | after ExitBootServices().\r | |
85 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
86 | at runtime could not be mapped.\r | |
87 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
88 | complete the registration.\r | |
89 | \r | |
90 | **/\r | |
91 | RETURN_STATUS\r | |
92 | EFIAPI\r | |
93 | PciSegmentRegisterForRuntimeAccess (\r | |
94 | IN UINTN Address\r | |
95 | );\r | |
96 | \r | |
97 | /**\r | |
98 | Reads an 8-bit PCI configuration register.\r | |
99 | \r | |
100 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
101 | This function must guarantee that all PCI read and write operations are serialized.\r | |
102 | \r | |
103 | If any reserved bits in Address are set, then ASSERT().\r | |
104 | \r | |
105 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
106 | \r | |
107 | @return The 8-bit PCI configuration register specified by Address.\r | |
108 | \r | |
109 | **/\r | |
110 | UINT8\r | |
111 | EFIAPI\r | |
112 | PciSegmentRead8 (\r | |
113 | IN UINT64 Address\r | |
114 | );\r | |
115 | \r | |
116 | /**\r | |
117 | Writes an 8-bit PCI configuration register.\r | |
118 | \r | |
119 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r | |
120 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
121 | \r | |
122 | If any reserved bits in Address are set, then ASSERT().\r | |
123 | \r | |
124 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
125 | @param Value The value to write.\r | |
126 | \r | |
127 | @return The value written to the PCI configuration register.\r | |
128 | \r | |
129 | **/\r | |
130 | UINT8\r | |
131 | EFIAPI\r | |
132 | PciSegmentWrite8 (\r | |
133 | IN UINT64 Address,\r | |
134 | IN UINT8 Value\r | |
135 | );\r | |
136 | \r | |
137 | /**\r | |
138 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r | |
139 | \r | |
140 | Reads the 8-bit PCI configuration register specified by Address,\r | |
141 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
142 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
143 | The value written to the PCI configuration register is returned.\r | |
144 | This function must guarantee that all PCI read and write operations are serialized.\r | |
145 | \r | |
146 | If any reserved bits in Address are set, then ASSERT().\r | |
147 | \r | |
148 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
149 | @param OrData The value to OR with the PCI configuration register.\r | |
150 | \r | |
151 | @return The value written to the PCI configuration register.\r | |
152 | \r | |
153 | **/\r | |
154 | UINT8\r | |
155 | EFIAPI\r | |
156 | PciSegmentOr8 (\r | |
157 | IN UINT64 Address,\r | |
158 | IN UINT8 OrData\r | |
159 | );\r | |
160 | \r | |
161 | /**\r | |
162 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r | |
163 | \r | |
164 | Reads the 8-bit PCI configuration register specified by Address,\r | |
165 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
166 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
167 | The value written to the PCI configuration register is returned.\r | |
168 | This function must guarantee that all PCI read and write operations are serialized.\r | |
169 | If any reserved bits in Address are set, then ASSERT().\r | |
170 | \r | |
171 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
172 | @param AndData The value to AND with the PCI configuration register.\r | |
173 | \r | |
174 | @return The value written to the PCI configuration register.\r | |
175 | \r | |
176 | **/\r | |
177 | UINT8\r | |
178 | EFIAPI\r | |
179 | PciSegmentAnd8 (\r | |
180 | IN UINT64 Address,\r | |
181 | IN UINT8 AndData\r | |
182 | );\r | |
183 | \r | |
184 | /**\r | |
185 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r | |
186 | followed a bitwise OR with another 8-bit value.\r | |
187 | \r | |
188 | Reads the 8-bit PCI configuration register specified by Address,\r | |
189 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
190 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
191 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
192 | The value written to the PCI configuration register is returned.\r | |
193 | This function must guarantee that all PCI read and write operations are serialized.\r | |
194 | \r | |
195 | If any reserved bits in Address are set, then ASSERT().\r | |
196 | \r | |
197 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
198 | @param AndData The value to AND with the PCI configuration register.\r | |
199 | @param OrData The value to OR with the PCI configuration register.\r | |
200 | \r | |
201 | @return The value written to the PCI configuration register.\r | |
202 | \r | |
203 | **/\r | |
204 | UINT8\r | |
205 | EFIAPI\r | |
206 | PciSegmentAndThenOr8 (\r | |
207 | IN UINT64 Address,\r | |
208 | IN UINT8 AndData,\r | |
209 | IN UINT8 OrData\r | |
210 | );\r | |
211 | \r | |
212 | /**\r | |
213 | Reads a bit field of a PCI configuration register.\r | |
214 | \r | |
215 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
216 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
217 | returned.\r | |
218 | \r | |
219 | If any reserved bits in Address are set, then ASSERT().\r | |
220 | If StartBit is greater than 7, then ASSERT().\r | |
221 | If EndBit is greater than 7, then ASSERT().\r | |
222 | If EndBit is less than StartBit, then ASSERT().\r | |
223 | \r | |
224 | @param Address PCI configuration register to read.\r | |
225 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
226 | Range 0..7.\r | |
227 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
228 | Range 0..7.\r | |
229 | \r | |
230 | @return The value of the bit field read from the PCI configuration register.\r | |
231 | \r | |
232 | **/\r | |
233 | UINT8\r | |
234 | EFIAPI\r | |
235 | PciSegmentBitFieldRead8 (\r | |
236 | IN UINT64 Address,\r | |
237 | IN UINTN StartBit,\r | |
238 | IN UINTN EndBit\r | |
239 | );\r | |
240 | \r | |
241 | /**\r | |
242 | Writes a bit field to a PCI configuration register.\r | |
243 | \r | |
244 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
245 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
246 | destination PCI configuration register are preserved. The new value of the\r | |
247 | 8-bit register is returned.\r | |
248 | \r | |
249 | If any reserved bits in Address are set, then ASSERT().\r | |
250 | If StartBit is greater than 7, then ASSERT().\r | |
251 | If EndBit is greater than 7, then ASSERT().\r | |
252 | If EndBit is less than StartBit, then ASSERT().\r | |
253 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
254 | \r | |
255 | @param Address PCI configuration register to write.\r | |
256 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
257 | Range 0..7.\r | |
258 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
259 | Range 0..7.\r | |
260 | @param Value New value of the bit field.\r | |
261 | \r | |
262 | @return The value written back to the PCI configuration register.\r | |
263 | \r | |
264 | **/\r | |
265 | UINT8\r | |
266 | EFIAPI\r | |
267 | PciSegmentBitFieldWrite8 (\r | |
268 | IN UINT64 Address,\r | |
269 | IN UINTN StartBit,\r | |
270 | IN UINTN EndBit,\r | |
271 | IN UINT8 Value\r | |
272 | );\r | |
273 | \r | |
274 | /**\r | |
275 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
276 | writes the result back to the bit field in the 8-bit port.\r | |
277 | \r | |
278 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
279 | bitwise OR between the read result and the value specified by\r | |
280 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
281 | specified by Address. The value written to the PCI configuration register is\r | |
282 | returned. This function must guarantee that all PCI read and write operations\r | |
283 | are serialized. Extra left bits in OrData are stripped.\r | |
284 | \r | |
285 | If any reserved bits in Address are set, then ASSERT().\r | |
286 | If StartBit is greater than 7, then ASSERT().\r | |
287 | If EndBit is greater than 7, then ASSERT().\r | |
288 | If EndBit is less than StartBit, then ASSERT().\r | |
289 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
290 | \r | |
291 | @param Address PCI configuration register to write.\r | |
292 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
293 | Range 0..7.\r | |
294 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
295 | Range 0..7.\r | |
296 | @param OrData The value to OR with the PCI configuration register.\r | |
297 | \r | |
298 | @return The value written back to the PCI configuration register.\r | |
299 | \r | |
300 | **/\r | |
301 | UINT8\r | |
302 | EFIAPI\r | |
303 | PciSegmentBitFieldOr8 (\r | |
304 | IN UINT64 Address,\r | |
305 | IN UINTN StartBit,\r | |
306 | IN UINTN EndBit,\r | |
307 | IN UINT8 OrData\r | |
308 | );\r | |
309 | \r | |
310 | /**\r | |
311 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
312 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
313 | \r | |
314 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
315 | bitwise AND between the read result and the value specified by AndData, and\r | |
316 | writes the result to the 8-bit PCI configuration register specified by\r | |
317 | Address. The value written to the PCI configuration register is returned.\r | |
318 | This function must guarantee that all PCI read and write operations are\r | |
319 | serialized. Extra left bits in AndData are stripped.\r | |
320 | \r | |
321 | If any reserved bits in Address are set, then ASSERT().\r | |
322 | If StartBit is greater than 7, then ASSERT().\r | |
323 | If EndBit is greater than 7, then ASSERT().\r | |
324 | If EndBit is less than StartBit, then ASSERT().\r | |
325 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
326 | \r | |
327 | @param Address PCI configuration register to write.\r | |
328 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
329 | Range 0..7.\r | |
330 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
331 | Range 0..7.\r | |
332 | @param AndData The value to AND with the PCI configuration register.\r | |
333 | \r | |
334 | @return The value written back to the PCI configuration register.\r | |
335 | \r | |
336 | **/\r | |
337 | UINT8\r | |
338 | EFIAPI\r | |
339 | PciSegmentBitFieldAnd8 (\r | |
340 | IN UINT64 Address,\r | |
341 | IN UINTN StartBit,\r | |
342 | IN UINTN EndBit,\r | |
343 | IN UINT8 AndData\r | |
344 | );\r | |
345 | \r | |
346 | /**\r | |
347 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
348 | bitwise OR, and writes the result back to the bit field in the 8-bit port.\r | |
349 | \r | |
350 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
351 | bitwise AND followed by a bitwise OR between the read result and\r | |
352 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
353 | configuration register specified by Address. The value written to the PCI\r | |
354 | configuration register is returned. This function must guarantee that all PCI\r | |
355 | read and write operations are serialized. Extra left bits in both AndData and\r | |
356 | OrData are stripped.\r | |
357 | \r | |
358 | If any reserved bits in Address are set, then ASSERT().\r | |
359 | If StartBit is greater than 7, then ASSERT().\r | |
360 | If EndBit is greater than 7, then ASSERT().\r | |
361 | If EndBit is less than StartBit, then ASSERT().\r | |
362 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
363 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
364 | \r | |
365 | @param Address PCI configuration register to write.\r | |
366 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
367 | Range 0..7.\r | |
368 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
369 | Range 0..7.\r | |
370 | @param AndData The value to AND with the PCI configuration register.\r | |
371 | @param OrData The value to OR with the result of the AND operation.\r | |
372 | \r | |
373 | @return The value written back to the PCI configuration register.\r | |
374 | \r | |
375 | **/\r | |
376 | UINT8\r | |
377 | EFIAPI\r | |
378 | PciSegmentBitFieldAndThenOr8 (\r | |
379 | IN UINT64 Address,\r | |
380 | IN UINTN StartBit,\r | |
381 | IN UINTN EndBit,\r | |
382 | IN UINT8 AndData,\r | |
383 | IN UINT8 OrData\r | |
384 | );\r | |
385 | \r | |
386 | /**\r | |
387 | Reads a 16-bit PCI configuration register.\r | |
388 | \r | |
389 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
390 | This function must guarantee that all PCI read and write operations are serialized.\r | |
391 | \r | |
392 | If any reserved bits in Address are set, then ASSERT().\r | |
393 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
394 | \r | |
395 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
396 | \r | |
397 | @return The 16-bit PCI configuration register specified by Address.\r | |
398 | \r | |
399 | **/\r | |
400 | UINT16\r | |
401 | EFIAPI\r | |
402 | PciSegmentRead16 (\r | |
403 | IN UINT64 Address\r | |
404 | );\r | |
405 | \r | |
406 | /**\r | |
407 | Writes a 16-bit PCI configuration register.\r | |
408 | \r | |
409 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r | |
410 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
411 | \r | |
412 | If any reserved bits in Address are set, then ASSERT().\r | |
413 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
414 | \r | |
415 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
416 | @param Value The value to write.\r | |
417 | \r | |
418 | @return The parameter of Value.\r | |
419 | \r | |
420 | **/\r | |
421 | UINT16\r | |
422 | EFIAPI\r | |
423 | PciSegmentWrite16 (\r | |
424 | IN UINT64 Address,\r | |
425 | IN UINT16 Value\r | |
426 | );\r | |
427 | \r | |
428 | /**\r | |
429 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
430 | a 16-bit value.\r | |
431 | \r | |
432 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
433 | bitwise OR between the read result and the value specified by OrData, and\r | |
434 | writes the result to the 16-bit PCI configuration register specified by Address.\r | |
435 | The value written to the PCI configuration register is returned. This function\r | |
436 | must guarantee that all PCI read and write operations are serialized.\r | |
437 | \r | |
438 | If any reserved bits in Address are set, then ASSERT().\r | |
439 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
440 | \r | |
441 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
442 | Register.\r | |
443 | @param OrData The value to OR with the PCI configuration register.\r | |
444 | \r | |
445 | @return The value written back to the PCI configuration register.\r | |
446 | \r | |
447 | **/\r | |
448 | UINT16\r | |
449 | EFIAPI\r | |
450 | PciSegmentOr16 (\r | |
451 | IN UINT64 Address,\r | |
452 | IN UINT16 OrData\r | |
453 | );\r | |
454 | \r | |
455 | /**\r | |
456 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r | |
457 | \r | |
458 | Reads the 16-bit PCI configuration register specified by Address,\r | |
459 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
460 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
461 | The value written to the PCI configuration register is returned.\r | |
462 | This function must guarantee that all PCI read and write operations are serialized.\r | |
463 | \r | |
464 | If any reserved bits in Address are set, then ASSERT().\r | |
465 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
466 | \r | |
467 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
468 | @param AndData The value to AND with the PCI configuration register.\r | |
469 | \r | |
470 | @return The value written to the PCI configuration register.\r | |
471 | \r | |
472 | **/\r | |
473 | UINT16\r | |
474 | EFIAPI\r | |
475 | PciSegmentAnd16 (\r | |
476 | IN UINT64 Address,\r | |
477 | IN UINT16 AndData\r | |
478 | );\r | |
479 | \r | |
480 | /**\r | |
481 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r | |
482 | followed a bitwise OR with another 16-bit value.\r | |
483 | \r | |
484 | Reads the 16-bit PCI configuration register specified by Address,\r | |
485 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
486 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
487 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
488 | The value written to the PCI configuration register is returned.\r | |
489 | This function must guarantee that all PCI read and write operations are serialized.\r | |
490 | \r | |
491 | If any reserved bits in Address are set, then ASSERT().\r | |
492 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
493 | \r | |
494 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
495 | @param AndData The value to AND with the PCI configuration register.\r | |
496 | @param OrData The value to OR with the PCI configuration register.\r | |
497 | \r | |
498 | @return The value written to the PCI configuration register.\r | |
499 | \r | |
500 | **/\r | |
501 | UINT16\r | |
502 | EFIAPI\r | |
503 | PciSegmentAndThenOr16 (\r | |
504 | IN UINT64 Address,\r | |
505 | IN UINT16 AndData,\r | |
506 | IN UINT16 OrData\r | |
507 | );\r | |
508 | \r | |
509 | /**\r | |
510 | Reads a bit field of a PCI configuration register.\r | |
511 | \r | |
512 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
513 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
514 | returned.\r | |
515 | \r | |
516 | If any reserved bits in Address are set, then ASSERT().\r | |
517 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
518 | If StartBit is greater than 15, then ASSERT().\r | |
519 | If EndBit is greater than 15, then ASSERT().\r | |
520 | If EndBit is less than StartBit, then ASSERT().\r | |
521 | \r | |
522 | @param Address PCI configuration register to read.\r | |
523 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
524 | Range 0..15.\r | |
525 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
526 | Range 0..15.\r | |
527 | \r | |
528 | @return The value of the bit field read from the PCI configuration register.\r | |
529 | \r | |
530 | **/\r | |
531 | UINT16\r | |
532 | EFIAPI\r | |
533 | PciSegmentBitFieldRead16 (\r | |
534 | IN UINT64 Address,\r | |
535 | IN UINTN StartBit,\r | |
536 | IN UINTN EndBit\r | |
537 | );\r | |
538 | \r | |
539 | /**\r | |
540 | Writes a bit field to a PCI configuration register.\r | |
541 | \r | |
542 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
543 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
544 | destination PCI configuration register are preserved. The new value of the\r | |
545 | 16-bit register is returned.\r | |
546 | \r | |
547 | If any reserved bits in Address are set, then ASSERT().\r | |
548 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
549 | If StartBit is greater than 15, then ASSERT().\r | |
550 | If EndBit is greater than 15, then ASSERT().\r | |
551 | If EndBit is less than StartBit, then ASSERT().\r | |
552 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
553 | \r | |
554 | @param Address PCI configuration register to write.\r | |
555 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
556 | Range 0..15.\r | |
557 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
558 | Range 0..15.\r | |
559 | @param Value New value of the bit field.\r | |
560 | \r | |
561 | @return The value written back to the PCI configuration register.\r | |
562 | \r | |
563 | **/\r | |
564 | UINT16\r | |
565 | EFIAPI\r | |
566 | PciSegmentBitFieldWrite16 (\r | |
567 | IN UINT64 Address,\r | |
568 | IN UINTN StartBit,\r | |
569 | IN UINTN EndBit,\r | |
570 | IN UINT16 Value\r | |
571 | );\r | |
572 | \r | |
573 | /**\r | |
574 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r | |
575 | the result back to the bit field in the 16-bit port.\r | |
576 | \r | |
577 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
578 | bitwise OR between the read result and the value specified by\r | |
579 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
580 | specified by Address. The value written to the PCI configuration register is\r | |
581 | returned. This function must guarantee that all PCI read and write operations\r | |
582 | are serialized. Extra left bits in OrData are stripped.\r | |
583 | \r | |
584 | If any reserved bits in Address are set, then ASSERT().\r | |
585 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
586 | If StartBit is greater than 15, then ASSERT().\r | |
587 | If EndBit is greater than 15, then ASSERT().\r | |
588 | If EndBit is less than StartBit, then ASSERT().\r | |
589 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
590 | \r | |
591 | @param Address PCI configuration register to write.\r | |
592 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
593 | Range 0..15.\r | |
594 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
595 | Range 0..15.\r | |
596 | @param OrData The value to OR with the PCI configuration register.\r | |
597 | \r | |
598 | @return The value written back to the PCI configuration register.\r | |
599 | \r | |
600 | **/\r | |
601 | UINT16\r | |
602 | EFIAPI\r | |
603 | PciSegmentBitFieldOr16 (\r | |
604 | IN UINT64 Address,\r | |
605 | IN UINTN StartBit,\r | |
606 | IN UINTN EndBit,\r | |
607 | IN UINT16 OrData\r | |
608 | );\r | |
609 | \r | |
610 | /**\r | |
611 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
612 | AND, writes the result back to the bit field in the 16-bit register.\r | |
613 | \r | |
614 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
615 | bitwise AND between the read result and the value specified by AndData, and\r | |
616 | writes the result to the 16-bit PCI configuration register specified by\r | |
617 | Address. The value written to the PCI configuration register is returned.\r | |
618 | This function must guarantee that all PCI read and write operations are\r | |
619 | serialized. Extra left bits in AndData are stripped.\r | |
620 | \r | |
621 | If any reserved bits in Address are set, then ASSERT().\r | |
622 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
623 | If StartBit is greater than 15, then ASSERT().\r | |
624 | If EndBit is greater than 15, then ASSERT().\r | |
625 | If EndBit is less than StartBit, then ASSERT().\r | |
626 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
627 | \r | |
628 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
629 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
630 | Range 0..15.\r | |
631 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
632 | Range 0..15.\r | |
633 | @param AndData The value to AND with the PCI configuration register.\r | |
634 | \r | |
635 | @return The value written back to the PCI configuration register.\r | |
636 | \r | |
637 | **/\r | |
638 | UINT16\r | |
639 | EFIAPI\r | |
640 | PciSegmentBitFieldAnd16 (\r | |
641 | IN UINT64 Address,\r | |
642 | IN UINTN StartBit,\r | |
643 | IN UINTN EndBit,\r | |
644 | IN UINT16 AndData\r | |
645 | );\r | |
646 | \r | |
647 | /**\r | |
648 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
649 | bitwise OR, and writes the result back to the bit field in the\r | |
650 | 16-bit port.\r | |
651 | \r | |
652 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
653 | bitwise AND followed by a bitwise OR between the read result and\r | |
654 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
655 | configuration register specified by Address. The value written to the PCI\r | |
656 | configuration register is returned. This function must guarantee that all PCI\r | |
657 | read and write operations are serialized. Extra left bits in both AndData and\r | |
658 | OrData are stripped.\r | |
659 | \r | |
660 | If any reserved bits in Address are set, then ASSERT().\r | |
661 | If StartBit is greater than 15, then ASSERT().\r | |
662 | If EndBit is greater than 15, then ASSERT().\r | |
663 | If EndBit is less than StartBit, then ASSERT().\r | |
664 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
665 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
666 | \r | |
667 | @param Address PCI configuration register to write.\r | |
668 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
669 | Range 0..15.\r | |
670 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
671 | Range 0..15.\r | |
672 | @param AndData The value to AND with the PCI configuration register.\r | |
673 | @param OrData The value to OR with the result of the AND operation.\r | |
674 | \r | |
675 | @return The value written back to the PCI configuration register.\r | |
676 | \r | |
677 | **/\r | |
678 | UINT16\r | |
679 | EFIAPI\r | |
680 | PciSegmentBitFieldAndThenOr16 (\r | |
681 | IN UINT64 Address,\r | |
682 | IN UINTN StartBit,\r | |
683 | IN UINTN EndBit,\r | |
684 | IN UINT16 AndData,\r | |
685 | IN UINT16 OrData\r | |
686 | );\r | |
687 | \r | |
688 | /**\r | |
689 | Reads a 32-bit PCI configuration register.\r | |
690 | \r | |
691 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
692 | This function must guarantee that all PCI read and write operations are serialized.\r | |
693 | \r | |
694 | If any reserved bits in Address are set, then ASSERT().\r | |
695 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
696 | \r | |
697 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
698 | \r | |
699 | @return The 32-bit PCI configuration register specified by Address.\r | |
700 | \r | |
701 | **/\r | |
702 | UINT32\r | |
703 | EFIAPI\r | |
704 | PciSegmentRead32 (\r | |
705 | IN UINT64 Address\r | |
706 | );\r | |
707 | \r | |
708 | /**\r | |
709 | Writes a 32-bit PCI configuration register.\r | |
710 | \r | |
711 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r | |
712 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
713 | \r | |
714 | If any reserved bits in Address are set, then ASSERT().\r | |
715 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
716 | \r | |
717 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
718 | @param Value The value to write.\r | |
719 | \r | |
720 | @return The parameter of Value.\r | |
721 | \r | |
722 | **/\r | |
723 | UINT32\r | |
724 | EFIAPI\r | |
725 | PciSegmentWrite32 (\r | |
726 | IN UINT64 Address,\r | |
727 | IN UINT32 Value\r | |
728 | );\r | |
729 | \r | |
730 | /**\r | |
731 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r | |
732 | \r | |
733 | Reads the 32-bit PCI configuration register specified by Address,\r | |
734 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
735 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
736 | The value written to the PCI configuration register is returned.\r | |
737 | This function must guarantee that all PCI read and write operations are serialized.\r | |
738 | \r | |
739 | If any reserved bits in Address are set, then ASSERT().\r | |
740 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
741 | \r | |
742 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
743 | @param OrData The value to OR with the PCI configuration register.\r | |
744 | \r | |
745 | @return The value written to the PCI configuration register.\r | |
746 | \r | |
747 | **/\r | |
748 | UINT32\r | |
749 | EFIAPI\r | |
750 | PciSegmentOr32 (\r | |
751 | IN UINT64 Address,\r | |
752 | IN UINT32 OrData\r | |
753 | );\r | |
754 | \r | |
755 | /**\r | |
756 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r | |
757 | \r | |
758 | Reads the 32-bit PCI configuration register specified by Address,\r | |
759 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
760 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
761 | The value written to the PCI configuration register is returned.\r | |
762 | This function must guarantee that all PCI read and write operations are serialized.\r | |
763 | \r | |
764 | If any reserved bits in Address are set, then ASSERT().\r | |
765 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
766 | \r | |
767 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
768 | @param AndData The value to AND with the PCI configuration register.\r | |
769 | \r | |
770 | @return The value written to the PCI configuration register.\r | |
771 | \r | |
772 | **/\r | |
773 | UINT32\r | |
774 | EFIAPI\r | |
775 | PciSegmentAnd32 (\r | |
776 | IN UINT64 Address,\r | |
777 | IN UINT32 AndData\r | |
778 | );\r | |
779 | \r | |
780 | /**\r | |
781 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r | |
782 | followed a bitwise OR with another 32-bit value.\r | |
783 | \r | |
784 | Reads the 32-bit PCI configuration register specified by Address,\r | |
785 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
786 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
787 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
788 | The value written to the PCI configuration register is returned.\r | |
789 | This function must guarantee that all PCI read and write operations are serialized.\r | |
790 | \r | |
791 | If any reserved bits in Address are set, then ASSERT().\r | |
792 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
793 | \r | |
794 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
795 | @param AndData The value to AND with the PCI configuration register.\r | |
796 | @param OrData The value to OR with the PCI configuration register.\r | |
797 | \r | |
798 | @return The value written to the PCI configuration register.\r | |
799 | \r | |
800 | **/\r | |
801 | UINT32\r | |
802 | EFIAPI\r | |
803 | PciSegmentAndThenOr32 (\r | |
804 | IN UINT64 Address,\r | |
805 | IN UINT32 AndData,\r | |
806 | IN UINT32 OrData\r | |
807 | );\r | |
808 | \r | |
809 | /**\r | |
810 | Reads a bit field of a PCI configuration register.\r | |
811 | \r | |
812 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
813 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
814 | returned.\r | |
815 | \r | |
816 | If any reserved bits in Address are set, then ASSERT().\r | |
817 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
818 | If StartBit is greater than 31, then ASSERT().\r | |
819 | If EndBit is greater than 31, then ASSERT().\r | |
820 | If EndBit is less than StartBit, then ASSERT().\r | |
821 | \r | |
822 | @param Address PCI configuration register to read.\r | |
823 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
824 | Range 0..31.\r | |
825 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
826 | Range 0..31.\r | |
827 | \r | |
828 | @return The value of the bit field read from the PCI configuration register.\r | |
829 | \r | |
830 | **/\r | |
831 | UINT32\r | |
832 | EFIAPI\r | |
833 | PciSegmentBitFieldRead32 (\r | |
834 | IN UINT64 Address,\r | |
835 | IN UINTN StartBit,\r | |
836 | IN UINTN EndBit\r | |
837 | );\r | |
838 | \r | |
839 | /**\r | |
840 | Writes a bit field to a PCI configuration register.\r | |
841 | \r | |
842 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
843 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
844 | destination PCI configuration register are preserved. The new value of the\r | |
845 | 32-bit register is returned.\r | |
846 | \r | |
847 | If any reserved bits in Address are set, then ASSERT().\r | |
848 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
849 | If StartBit is greater than 31, then ASSERT().\r | |
850 | If EndBit is greater than 31, then ASSERT().\r | |
851 | If EndBit is less than StartBit, then ASSERT().\r | |
852 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
853 | \r | |
854 | @param Address PCI configuration register to write.\r | |
855 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
856 | Range 0..31.\r | |
857 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
858 | Range 0..31.\r | |
859 | @param Value New value of the bit field.\r | |
860 | \r | |
861 | @return The value written back to the PCI configuration register.\r | |
862 | \r | |
863 | **/\r | |
864 | UINT32\r | |
865 | EFIAPI\r | |
866 | PciSegmentBitFieldWrite32 (\r | |
867 | IN UINT64 Address,\r | |
868 | IN UINTN StartBit,\r | |
869 | IN UINTN EndBit,\r | |
870 | IN UINT32 Value\r | |
871 | );\r | |
872 | \r | |
873 | /**\r | |
874 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
875 | writes the result back to the bit field in the 32-bit port.\r | |
876 | \r | |
877 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
878 | bitwise OR between the read result and the value specified by\r | |
879 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
880 | specified by Address. The value written to the PCI configuration register is\r | |
881 | returned. This function must guarantee that all PCI read and write operations\r | |
882 | are serialized. Extra left bits in OrData are stripped.\r | |
883 | \r | |
884 | If any reserved bits in Address are set, then ASSERT().\r | |
885 | If StartBit is greater than 31, then ASSERT().\r | |
886 | If EndBit is greater than 31, then ASSERT().\r | |
887 | If EndBit is less than StartBit, then ASSERT().\r | |
888 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
889 | \r | |
890 | @param Address PCI configuration register to write.\r | |
891 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
892 | Range 0..31.\r | |
893 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
894 | Range 0..31.\r | |
895 | @param OrData The value to OR with the PCI configuration register.\r | |
896 | \r | |
897 | @return The value written back to the PCI configuration register.\r | |
898 | \r | |
899 | **/\r | |
900 | UINT32\r | |
901 | EFIAPI\r | |
902 | PciSegmentBitFieldOr32 (\r | |
903 | IN UINT64 Address,\r | |
904 | IN UINTN StartBit,\r | |
905 | IN UINTN EndBit,\r | |
906 | IN UINT32 OrData\r | |
907 | );\r | |
908 | \r | |
909 | /**\r | |
910 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
911 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
912 | \r | |
913 | \r | |
914 | Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r | |
915 | AND between the read result and the value specified by AndData, and writes the result\r | |
916 | to the 32-bit PCI configuration register specified by Address. The value written to\r | |
917 | the PCI configuration register is returned. This function must guarantee that all PCI\r | |
918 | read and write operations are serialized. Extra left bits in AndData are stripped.\r | |
919 | If any reserved bits in Address are set, then ASSERT().\r | |
920 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
921 | If StartBit is greater than 31, then ASSERT().\r | |
922 | If EndBit is greater than 31, then ASSERT().\r | |
923 | If EndBit is less than StartBit, then ASSERT().\r | |
924 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
925 | \r | |
926 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
927 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
928 | Range 0..31.\r | |
929 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
930 | Range 0..31.\r | |
931 | @param AndData The value to AND with the PCI configuration register.\r | |
932 | \r | |
933 | @return The value written back to the PCI configuration register.\r | |
934 | \r | |
935 | **/\r | |
936 | UINT32\r | |
937 | EFIAPI\r | |
938 | PciSegmentBitFieldAnd32 (\r | |
939 | IN UINT64 Address,\r | |
940 | IN UINTN StartBit,\r | |
941 | IN UINTN EndBit,\r | |
942 | IN UINT32 AndData\r | |
943 | );\r | |
944 | \r | |
945 | /**\r | |
946 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
947 | bitwise OR, and writes the result back to the bit field in the\r | |
948 | 32-bit port.\r | |
949 | \r | |
950 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
951 | bitwise AND followed by a bitwise OR between the read result and\r | |
952 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
953 | configuration register specified by Address. The value written to the PCI\r | |
954 | configuration register is returned. This function must guarantee that all PCI\r | |
955 | read and write operations are serialized. Extra left bits in both AndData and\r | |
956 | OrData are stripped.\r | |
957 | \r | |
958 | If any reserved bits in Address are set, then ASSERT().\r | |
959 | If StartBit is greater than 31, then ASSERT().\r | |
960 | If EndBit is greater than 31, then ASSERT().\r | |
961 | If EndBit is less than StartBit, then ASSERT().\r | |
962 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
963 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
964 | \r | |
965 | @param Address PCI configuration register to write.\r | |
966 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
967 | Range 0..31.\r | |
968 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
969 | Range 0..31.\r | |
970 | @param AndData The value to AND with the PCI configuration register.\r | |
971 | @param OrData The value to OR with the result of the AND operation.\r | |
972 | \r | |
973 | @return The value written back to the PCI configuration register.\r | |
974 | \r | |
975 | **/\r | |
976 | UINT32\r | |
977 | EFIAPI\r | |
978 | PciSegmentBitFieldAndThenOr32 (\r | |
979 | IN UINT64 Address,\r | |
980 | IN UINTN StartBit,\r | |
981 | IN UINTN EndBit,\r | |
982 | IN UINT32 AndData,\r | |
983 | IN UINT32 OrData\r | |
984 | );\r | |
985 | \r | |
986 | /**\r | |
987 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
988 | \r | |
989 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
990 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
991 | configuration registers from a single PCI function to be read. Size is\r | |
992 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
993 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
994 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
995 | end of the range.\r | |
996 | \r | |
997 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
998 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
999 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1000 | \r | |
1001 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1002 | Function and Register.\r | |
1003 | @param Size Size in bytes of the transfer.\r | |
1004 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1005 | \r | |
1006 | @return Size\r | |
1007 | \r | |
1008 | **/\r | |
1009 | UINTN\r | |
1010 | EFIAPI\r | |
1011 | PciSegmentReadBuffer (\r | |
1012 | IN UINT64 StartAddress,\r | |
1013 | IN UINTN Size,\r | |
1014 | OUT VOID *Buffer\r | |
1015 | );\r | |
1016 | \r | |
1017 | /**\r | |
1018 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1019 | configuration space.\r | |
1020 | \r | |
1021 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1022 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1023 | configuration registers from a single PCI function to be written. Size is\r | |
1024 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1025 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1026 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1027 | and the end of the range.\r | |
1028 | \r | |
1029 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1030 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1031 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1032 | \r | |
1033 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1034 | Function and Register.\r | |
1035 | @param Size Size in bytes of the transfer.\r | |
1036 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1037 | \r | |
1038 | @return The parameter of Size.\r | |
1039 | \r | |
1040 | **/\r | |
1041 | UINTN\r | |
1042 | EFIAPI\r | |
1043 | PciSegmentWriteBuffer (\r | |
1044 | IN UINT64 StartAddress,\r | |
1045 | IN UINTN Size,\r | |
1046 | IN VOID *Buffer\r | |
1047 | );\r | |
1048 | \r | |
1049 | #endif\r |