| | 1 | /** @file\r |
| | 2 | Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r |
| | 3 | \r |
| | 4 | The PCI Segment Library function provide services to read, write, and modify the PCI configuration\r |
| | 5 | registers on PCI root bridges on any supported PCI segment. These library services take a single\r |
| | 6 | address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.\r |
| | 7 | The layout of this address parameter is as follows:\r |
| | 8 | \r |
| | 9 | PCI Register: Bits 0..11\r |
| | 10 | PCI Function Bits 12..14\r |
| | 11 | PCI Device Bits 15..19\r |
| | 12 | PCI Bus Bits 20..27\r |
| | 13 | Reserved Bits 28..31. Must be 0.\r |
| | 14 | PCI Segment Bits 32..47\r |
| | 15 | Reserved Bits 48..63. Must be 0.\r |
| | 16 | \r |
| | 17 | | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r |
| | 18 | 63 48 47 32 31 28 27 20 19 15 14 12 11 0\r |
| | 19 | \r |
| | 20 | These functions perform PCI configuration cycles using the default PCI configuration access\r |
| | 21 | method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it\r |
| | 22 | may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate\r |
| | 23 | access method. Modules will typically use the PCI Segment Library for its PCI configuration\r |
| | 24 | accesses when PCI Segments other than Segment #0 must be accessed.\r |
| | 25 | \r |
| | 26 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| | 27 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| | 28 | \r |
| | 29 | **/\r |
| | 30 | \r |
| | 31 | #ifndef __PCI_SEGMENT_LIB__\r |
| | 32 | #define __PCI_SEGMENT_LIB__\r |
| | 33 | \r |
| | 34 | \r |
| | 35 | /**\r |
| | 36 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r |
| | 37 | and PCI Register to an address that can be passed to the PCI Segment Library functions.\r |
| | 38 | \r |
| | 39 | Computes an address that is compatible with the PCI Segment Library functions.\r |
| | 40 | The unused upper bits of Segment, Bus, Device, Function,\r |
| | 41 | and Register are stripped prior to the generation of the address.\r |
| | 42 | \r |
| | 43 | @param Segment PCI Segment number. Range 0..65535.\r |
| | 44 | @param Bus PCI Bus number. Range 0..255.\r |
| | 45 | @param Device PCI Device number. Range 0..31.\r |
| | 46 | @param Function PCI Function number. Range 0..7.\r |
| | 47 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r |
| | 48 | \r |
| | 49 | @return The address that is compatible with the PCI Segment Library functions.\r |
| | 50 | \r |
| | 51 | **/\r |
| | 52 | #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r |
| | 53 | ((Segment != 0) ? \\r |
| | 54 | ( ((Register) & 0xfff) | \\r |
| | 55 | (((Function) & 0x07) << 12) | \\r |
| | 56 | (((Device) & 0x1f) << 15) | \\r |
| | 57 | (((Bus) & 0xff) << 20) | \\r |
| | 58 | (LShiftU64 ((Segment) & 0xffff, 32)) \\r |
| | 59 | ) : \\r |
| | 60 | ( ((Register) & 0xfff) | \\r |
| | 61 | (((Function) & 0x07) << 12) | \\r |
| | 62 | (((Device) & 0x1f) << 15) | \\r |
| | 63 | (((Bus) & 0xff) << 20) \\r |
| | 64 | ) \\r |
| | 65 | )\r |
| | 66 | \r |
| | 67 | /**\r |
| | 68 | Register a PCI device so PCI configuration registers may be accessed after\r |
| | 69 | SetVirtualAddressMap().\r |
| | 70 | \r |
| | 71 | If any reserved bits in Address are set, then ASSERT().\r |
| | 72 | \r |
| | 73 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| | 74 | Register.\r |
| | 75 | \r |
| | 76 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
| | 77 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
| | 78 | after ExitBootServices().\r |
| | 79 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r |
| | 80 | at runtime could not be mapped.\r |
| | 81 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r |
| | 82 | complete the registration.\r |
| | 83 | \r |
| | 84 | **/\r |
| | 85 | RETURN_STATUS\r |
| | 86 | EFIAPI\r |
| | 87 | PciSegmentRegisterForRuntimeAccess (\r |
| | 88 | IN UINTN Address\r |
| | 89 | );\r |
| | 90 | \r |
| | 91 | /**\r |
| | 92 | Reads an 8-bit PCI configuration register.\r |
| | 93 | \r |
| | 94 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| | 95 | This function must guarantee that all PCI read and write operations are serialized.\r |
| | 96 | \r |
| | 97 | If any reserved bits in Address are set, then ASSERT().\r |
| | 98 | \r |
| | 99 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 100 | \r |
| | 101 | @return The 8-bit PCI configuration register specified by Address.\r |
| | 102 | \r |
| | 103 | **/\r |
| | 104 | UINT8\r |
| | 105 | EFIAPI\r |
| | 106 | PciSegmentRead8 (\r |
| | 107 | IN UINT64 Address\r |
| | 108 | );\r |
| | 109 | \r |
| | 110 | /**\r |
| | 111 | Writes an 8-bit PCI configuration register.\r |
| | 112 | \r |
| | 113 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r |
| | 114 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| | 115 | \r |
| | 116 | If any reserved bits in Address are set, then ASSERT().\r |
| | 117 | \r |
| | 118 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 119 | @param Value The value to write.\r |
| | 120 | \r |
| | 121 | @return The value written to the PCI configuration register.\r |
| | 122 | \r |
| | 123 | **/\r |
| | 124 | UINT8\r |
| | 125 | EFIAPI\r |
| | 126 | PciSegmentWrite8 (\r |
| | 127 | IN UINT64 Address,\r |
| | 128 | IN UINT8 Value\r |
| | 129 | );\r |
| | 130 | \r |
| | 131 | /**\r |
| | 132 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r |
| | 133 | \r |
| | 134 | Reads the 8-bit PCI configuration register specified by Address,\r |
| | 135 | performs a bitwise OR between the read result and the value specified by OrData,\r |
| | 136 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| | 137 | The value written to the PCI configuration register is returned.\r |
| | 138 | This function must guarantee that all PCI read and write operations are serialized.\r |
| | 139 | \r |
| | 140 | If any reserved bits in Address are set, then ASSERT().\r |
| | 141 | \r |
| | 142 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 143 | @param OrData The value to OR with the PCI configuration register.\r |
| | 144 | \r |
| | 145 | @return The value written to the PCI configuration register.\r |
| | 146 | \r |
| | 147 | **/\r |
| | 148 | UINT8\r |
| | 149 | EFIAPI\r |
| | 150 | PciSegmentOr8 (\r |
| | 151 | IN UINT64 Address,\r |
| | 152 | IN UINT8 OrData\r |
| | 153 | );\r |
| | 154 | \r |
| | 155 | /**\r |
| | 156 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r |
| | 157 | \r |
| | 158 | Reads the 8-bit PCI configuration register specified by Address,\r |
| | 159 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| | 160 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| | 161 | The value written to the PCI configuration register is returned.\r |
| | 162 | This function must guarantee that all PCI read and write operations are serialized.\r |
| | 163 | If any reserved bits in Address are set, then ASSERT().\r |
| | 164 | \r |
| | 165 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 166 | @param AndData The value to AND with the PCI configuration register.\r |
| | 167 | \r |
| | 168 | @return The value written to the PCI configuration register.\r |
| | 169 | \r |
| | 170 | **/\r |
| | 171 | UINT8\r |
| | 172 | EFIAPI\r |
| | 173 | PciSegmentAnd8 (\r |
| | 174 | IN UINT64 Address,\r |
| | 175 | IN UINT8 AndData\r |
| | 176 | );\r |
| | 177 | \r |
| | 178 | /**\r |
| | 179 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r |
| | 180 | followed a bitwise OR with another 8-bit value.\r |
| | 181 | \r |
| | 182 | Reads the 8-bit PCI configuration register specified by Address,\r |
| | 183 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| | 184 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
| | 185 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| | 186 | The value written to the PCI configuration register is returned.\r |
| | 187 | This function must guarantee that all PCI read and write operations are serialized.\r |
| | 188 | \r |
| | 189 | If any reserved bits in Address are set, then ASSERT().\r |
| | 190 | \r |
| | 191 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 192 | @param AndData The value to AND with the PCI configuration register.\r |
| | 193 | @param OrData The value to OR with the PCI configuration register.\r |
| | 194 | \r |
| | 195 | @return The value written to the PCI configuration register.\r |
| | 196 | \r |
| | 197 | **/\r |
| | 198 | UINT8\r |
| | 199 | EFIAPI\r |
| | 200 | PciSegmentAndThenOr8 (\r |
| | 201 | IN UINT64 Address,\r |
| | 202 | IN UINT8 AndData,\r |
| | 203 | IN UINT8 OrData\r |
| | 204 | );\r |
| | 205 | \r |
| | 206 | /**\r |
| | 207 | Reads a bit field of a PCI configuration register.\r |
| | 208 | \r |
| | 209 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| | 210 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| | 211 | returned.\r |
| | 212 | \r |
| | 213 | If any reserved bits in Address are set, then ASSERT().\r |
| | 214 | If StartBit is greater than 7, then ASSERT().\r |
| | 215 | If EndBit is greater than 7, then ASSERT().\r |
| | 216 | If EndBit is less than StartBit, then ASSERT().\r |
| | 217 | \r |
| | 218 | @param Address PCI configuration register to read.\r |
| | 219 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 220 | Range 0..7.\r |
| | 221 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 222 | Range 0..7.\r |
| | 223 | \r |
| | 224 | @return The value of the bit field read from the PCI configuration register.\r |
| | 225 | \r |
| | 226 | **/\r |
| | 227 | UINT8\r |
| | 228 | EFIAPI\r |
| | 229 | PciSegmentBitFieldRead8 (\r |
| | 230 | IN UINT64 Address,\r |
| | 231 | IN UINTN StartBit,\r |
| | 232 | IN UINTN EndBit\r |
| | 233 | );\r |
| | 234 | \r |
| | 235 | /**\r |
| | 236 | Writes a bit field to a PCI configuration register.\r |
| | 237 | \r |
| | 238 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| | 239 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| | 240 | destination PCI configuration register are preserved. The new value of the\r |
| | 241 | 8-bit register is returned.\r |
| | 242 | \r |
| | 243 | If any reserved bits in Address are set, then ASSERT().\r |
| | 244 | If StartBit is greater than 7, then ASSERT().\r |
| | 245 | If EndBit is greater than 7, then ASSERT().\r |
| | 246 | If EndBit is less than StartBit, then ASSERT().\r |
| | 247 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 248 | \r |
| | 249 | @param Address PCI configuration register to write.\r |
| | 250 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 251 | Range 0..7.\r |
| | 252 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 253 | Range 0..7.\r |
| | 254 | @param Value New value of the bit field.\r |
| | 255 | \r |
| | 256 | @return The value written back to the PCI configuration register.\r |
| | 257 | \r |
| | 258 | **/\r |
| | 259 | UINT8\r |
| | 260 | EFIAPI\r |
| | 261 | PciSegmentBitFieldWrite8 (\r |
| | 262 | IN UINT64 Address,\r |
| | 263 | IN UINTN StartBit,\r |
| | 264 | IN UINTN EndBit,\r |
| | 265 | IN UINT8 Value\r |
| | 266 | );\r |
| | 267 | \r |
| | 268 | /**\r |
| | 269 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| | 270 | writes the result back to the bit field in the 8-bit port.\r |
| | 271 | \r |
| | 272 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| | 273 | bitwise OR between the read result and the value specified by\r |
| | 274 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| | 275 | specified by Address. The value written to the PCI configuration register is\r |
| | 276 | returned. This function must guarantee that all PCI read and write operations\r |
| | 277 | are serialized. Extra left bits in OrData are stripped.\r |
| | 278 | \r |
| | 279 | If any reserved bits in Address are set, then ASSERT().\r |
| | 280 | If StartBit is greater than 7, then ASSERT().\r |
| | 281 | If EndBit is greater than 7, then ASSERT().\r |
| | 282 | If EndBit is less than StartBit, then ASSERT().\r |
| | 283 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 284 | \r |
| | 285 | @param Address PCI configuration register to write.\r |
| | 286 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 287 | Range 0..7.\r |
| | 288 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 289 | Range 0..7.\r |
| | 290 | @param OrData The value to OR with the PCI configuration register.\r |
| | 291 | \r |
| | 292 | @return The value written back to the PCI configuration register.\r |
| | 293 | \r |
| | 294 | **/\r |
| | 295 | UINT8\r |
| | 296 | EFIAPI\r |
| | 297 | PciSegmentBitFieldOr8 (\r |
| | 298 | IN UINT64 Address,\r |
| | 299 | IN UINTN StartBit,\r |
| | 300 | IN UINTN EndBit,\r |
| | 301 | IN UINT8 OrData\r |
| | 302 | );\r |
| | 303 | \r |
| | 304 | /**\r |
| | 305 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| | 306 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| | 307 | \r |
| | 308 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| | 309 | bitwise AND between the read result and the value specified by AndData, and\r |
| | 310 | writes the result to the 8-bit PCI configuration register specified by\r |
| | 311 | Address. The value written to the PCI configuration register is returned.\r |
| | 312 | This function must guarantee that all PCI read and write operations are\r |
| | 313 | serialized. Extra left bits in AndData are stripped.\r |
| | 314 | \r |
| | 315 | If any reserved bits in Address are set, then ASSERT().\r |
| | 316 | If StartBit is greater than 7, then ASSERT().\r |
| | 317 | If EndBit is greater than 7, then ASSERT().\r |
| | 318 | If EndBit is less than StartBit, then ASSERT().\r |
| | 319 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 320 | \r |
| | 321 | @param Address PCI configuration register to write.\r |
| | 322 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 323 | Range 0..7.\r |
| | 324 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 325 | Range 0..7.\r |
| | 326 | @param AndData The value to AND with the PCI configuration register.\r |
| | 327 | \r |
| | 328 | @return The value written back to the PCI configuration register.\r |
| | 329 | \r |
| | 330 | **/\r |
| | 331 | UINT8\r |
| | 332 | EFIAPI\r |
| | 333 | PciSegmentBitFieldAnd8 (\r |
| | 334 | IN UINT64 Address,\r |
| | 335 | IN UINTN StartBit,\r |
| | 336 | IN UINTN EndBit,\r |
| | 337 | IN UINT8 AndData\r |
| | 338 | );\r |
| | 339 | \r |
| | 340 | /**\r |
| | 341 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| | 342 | bitwise OR, and writes the result back to the bit field in the 8-bit port.\r |
| | 343 | \r |
| | 344 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| | 345 | bitwise AND followed by a bitwise OR between the read result and\r |
| | 346 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| | 347 | configuration register specified by Address. The value written to the PCI\r |
| | 348 | configuration register is returned. This function must guarantee that all PCI\r |
| | 349 | read and write operations are serialized. Extra left bits in both AndData and\r |
| | 350 | OrData are stripped.\r |
| | 351 | \r |
| | 352 | If any reserved bits in Address are set, then ASSERT().\r |
| | 353 | If StartBit is greater than 7, then ASSERT().\r |
| | 354 | If EndBit is greater than 7, then ASSERT().\r |
| | 355 | If EndBit is less than StartBit, then ASSERT().\r |
| | 356 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 357 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 358 | \r |
| | 359 | @param Address PCI configuration register to write.\r |
| | 360 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 361 | Range 0..7.\r |
| | 362 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 363 | Range 0..7.\r |
| | 364 | @param AndData The value to AND with the PCI configuration register.\r |
| | 365 | @param OrData The value to OR with the result of the AND operation.\r |
| | 366 | \r |
| | 367 | @return The value written back to the PCI configuration register.\r |
| | 368 | \r |
| | 369 | **/\r |
| | 370 | UINT8\r |
| | 371 | EFIAPI\r |
| | 372 | PciSegmentBitFieldAndThenOr8 (\r |
| | 373 | IN UINT64 Address,\r |
| | 374 | IN UINTN StartBit,\r |
| | 375 | IN UINTN EndBit,\r |
| | 376 | IN UINT8 AndData,\r |
| | 377 | IN UINT8 OrData\r |
| | 378 | );\r |
| | 379 | \r |
| | 380 | /**\r |
| | 381 | Reads a 16-bit PCI configuration register.\r |
| | 382 | \r |
| | 383 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| | 384 | This function must guarantee that all PCI read and write operations are serialized.\r |
| | 385 | \r |
| | 386 | If any reserved bits in Address are set, then ASSERT().\r |
| | 387 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 388 | \r |
| | 389 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 390 | \r |
| | 391 | @return The 16-bit PCI configuration register specified by Address.\r |
| | 392 | \r |
| | 393 | **/\r |
| | 394 | UINT16\r |
| | 395 | EFIAPI\r |
| | 396 | PciSegmentRead16 (\r |
| | 397 | IN UINT64 Address\r |
| | 398 | );\r |
| | 399 | \r |
| | 400 | /**\r |
| | 401 | Writes a 16-bit PCI configuration register.\r |
| | 402 | \r |
| | 403 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r |
| | 404 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| | 405 | \r |
| | 406 | If any reserved bits in Address are set, then ASSERT().\r |
| | 407 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 408 | \r |
| | 409 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 410 | @param Value The value to write.\r |
| | 411 | \r |
| | 412 | @return The parameter of Value.\r |
| | 413 | \r |
| | 414 | **/\r |
| | 415 | UINT16\r |
| | 416 | EFIAPI\r |
| | 417 | PciSegmentWrite16 (\r |
| | 418 | IN UINT64 Address,\r |
| | 419 | IN UINT16 Value\r |
| | 420 | );\r |
| | 421 | \r |
| | 422 | /**\r |
| | 423 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
| | 424 | a 16-bit value.\r |
| | 425 | \r |
| | 426 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| | 427 | bitwise OR between the read result and the value specified by OrData, and\r |
| | 428 | writes the result to the 16-bit PCI configuration register specified by Address.\r |
| | 429 | The value written to the PCI configuration register is returned. This function\r |
| | 430 | must guarantee that all PCI read and write operations are serialized.\r |
| | 431 | \r |
| | 432 | If any reserved bits in Address are set, then ASSERT().\r |
| | 433 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 434 | \r |
| | 435 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| | 436 | Register.\r |
| | 437 | @param OrData The value to OR with the PCI configuration register.\r |
| | 438 | \r |
| | 439 | @return The value written back to the PCI configuration register.\r |
| | 440 | \r |
| | 441 | **/\r |
| | 442 | UINT16\r |
| | 443 | EFIAPI\r |
| | 444 | PciSegmentOr16 (\r |
| | 445 | IN UINT64 Address,\r |
| | 446 | IN UINT16 OrData\r |
| | 447 | );\r |
| | 448 | \r |
| | 449 | /**\r |
| | 450 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r |
| | 451 | \r |
| | 452 | Reads the 16-bit PCI configuration register specified by Address,\r |
| | 453 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| | 454 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| | 455 | The value written to the PCI configuration register is returned.\r |
| | 456 | This function must guarantee that all PCI read and write operations are serialized.\r |
| | 457 | \r |
| | 458 | If any reserved bits in Address are set, then ASSERT().\r |
| | 459 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 460 | \r |
| | 461 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 462 | @param AndData The value to AND with the PCI configuration register.\r |
| | 463 | \r |
| | 464 | @return The value written to the PCI configuration register.\r |
| | 465 | \r |
| | 466 | **/\r |
| | 467 | UINT16\r |
| | 468 | EFIAPI\r |
| | 469 | PciSegmentAnd16 (\r |
| | 470 | IN UINT64 Address,\r |
| | 471 | IN UINT16 AndData\r |
| | 472 | );\r |
| | 473 | \r |
| | 474 | /**\r |
| | 475 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r |
| | 476 | followed a bitwise OR with another 16-bit value.\r |
| | 477 | \r |
| | 478 | Reads the 16-bit PCI configuration register specified by Address,\r |
| | 479 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| | 480 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
| | 481 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| | 482 | The value written to the PCI configuration register is returned.\r |
| | 483 | This function must guarantee that all PCI read and write operations are serialized.\r |
| | 484 | \r |
| | 485 | If any reserved bits in Address are set, then ASSERT().\r |
| | 486 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 487 | \r |
| | 488 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 489 | @param AndData The value to AND with the PCI configuration register.\r |
| | 490 | @param OrData The value to OR with the PCI configuration register.\r |
| | 491 | \r |
| | 492 | @return The value written to the PCI configuration register.\r |
| | 493 | \r |
| | 494 | **/\r |
| | 495 | UINT16\r |
| | 496 | EFIAPI\r |
| | 497 | PciSegmentAndThenOr16 (\r |
| | 498 | IN UINT64 Address,\r |
| | 499 | IN UINT16 AndData,\r |
| | 500 | IN UINT16 OrData\r |
| | 501 | );\r |
| | 502 | \r |
| | 503 | /**\r |
| | 504 | Reads a bit field of a PCI configuration register.\r |
| | 505 | \r |
| | 506 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| | 507 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| | 508 | returned.\r |
| | 509 | \r |
| | 510 | If any reserved bits in Address are set, then ASSERT().\r |
| | 511 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 512 | If StartBit is greater than 15, then ASSERT().\r |
| | 513 | If EndBit is greater than 15, then ASSERT().\r |
| | 514 | If EndBit is less than StartBit, then ASSERT().\r |
| | 515 | \r |
| | 516 | @param Address PCI configuration register to read.\r |
| | 517 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 518 | Range 0..15.\r |
| | 519 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 520 | Range 0..15.\r |
| | 521 | \r |
| | 522 | @return The value of the bit field read from the PCI configuration register.\r |
| | 523 | \r |
| | 524 | **/\r |
| | 525 | UINT16\r |
| | 526 | EFIAPI\r |
| | 527 | PciSegmentBitFieldRead16 (\r |
| | 528 | IN UINT64 Address,\r |
| | 529 | IN UINTN StartBit,\r |
| | 530 | IN UINTN EndBit\r |
| | 531 | );\r |
| | 532 | \r |
| | 533 | /**\r |
| | 534 | Writes a bit field to a PCI configuration register.\r |
| | 535 | \r |
| | 536 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| | 537 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| | 538 | destination PCI configuration register are preserved. The new value of the\r |
| | 539 | 16-bit register is returned.\r |
| | 540 | \r |
| | 541 | If any reserved bits in Address are set, then ASSERT().\r |
| | 542 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 543 | If StartBit is greater than 15, then ASSERT().\r |
| | 544 | If EndBit is greater than 15, then ASSERT().\r |
| | 545 | If EndBit is less than StartBit, then ASSERT().\r |
| | 546 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 547 | \r |
| | 548 | @param Address PCI configuration register to write.\r |
| | 549 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 550 | Range 0..15.\r |
| | 551 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 552 | Range 0..15.\r |
| | 553 | @param Value New value of the bit field.\r |
| | 554 | \r |
| | 555 | @return The value written back to the PCI configuration register.\r |
| | 556 | \r |
| | 557 | **/\r |
| | 558 | UINT16\r |
| | 559 | EFIAPI\r |
| | 560 | PciSegmentBitFieldWrite16 (\r |
| | 561 | IN UINT64 Address,\r |
| | 562 | IN UINTN StartBit,\r |
| | 563 | IN UINTN EndBit,\r |
| | 564 | IN UINT16 Value\r |
| | 565 | );\r |
| | 566 | \r |
| | 567 | /**\r |
| | 568 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r |
| | 569 | the result back to the bit field in the 16-bit port.\r |
| | 570 | \r |
| | 571 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| | 572 | bitwise OR between the read result and the value specified by\r |
| | 573 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| | 574 | specified by Address. The value written to the PCI configuration register is\r |
| | 575 | returned. This function must guarantee that all PCI read and write operations\r |
| | 576 | are serialized. Extra left bits in OrData are stripped.\r |
| | 577 | \r |
| | 578 | If any reserved bits in Address are set, then ASSERT().\r |
| | 579 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 580 | If StartBit is greater than 15, then ASSERT().\r |
| | 581 | If EndBit is greater than 15, then ASSERT().\r |
| | 582 | If EndBit is less than StartBit, then ASSERT().\r |
| | 583 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 584 | \r |
| | 585 | @param Address PCI configuration register to write.\r |
| | 586 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 587 | Range 0..15.\r |
| | 588 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 589 | Range 0..15.\r |
| | 590 | @param OrData The value to OR with the PCI configuration register.\r |
| | 591 | \r |
| | 592 | @return The value written back to the PCI configuration register.\r |
| | 593 | \r |
| | 594 | **/\r |
| | 595 | UINT16\r |
| | 596 | EFIAPI\r |
| | 597 | PciSegmentBitFieldOr16 (\r |
| | 598 | IN UINT64 Address,\r |
| | 599 | IN UINTN StartBit,\r |
| | 600 | IN UINTN EndBit,\r |
| | 601 | IN UINT16 OrData\r |
| | 602 | );\r |
| | 603 | \r |
| | 604 | /**\r |
| | 605 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| | 606 | AND, writes the result back to the bit field in the 16-bit register.\r |
| | 607 | \r |
| | 608 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| | 609 | bitwise AND between the read result and the value specified by AndData, and\r |
| | 610 | writes the result to the 16-bit PCI configuration register specified by\r |
| | 611 | Address. The value written to the PCI configuration register is returned.\r |
| | 612 | This function must guarantee that all PCI read and write operations are\r |
| | 613 | serialized. Extra left bits in AndData are stripped.\r |
| | 614 | \r |
| | 615 | If any reserved bits in Address are set, then ASSERT().\r |
| | 616 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| | 617 | If StartBit is greater than 15, then ASSERT().\r |
| | 618 | If EndBit is greater than 15, then ASSERT().\r |
| | 619 | If EndBit is less than StartBit, then ASSERT().\r |
| | 620 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 621 | \r |
| | 622 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 623 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 624 | Range 0..15.\r |
| | 625 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 626 | Range 0..15.\r |
| | 627 | @param AndData The value to AND with the PCI configuration register.\r |
| | 628 | \r |
| | 629 | @return The value written back to the PCI configuration register.\r |
| | 630 | \r |
| | 631 | **/\r |
| | 632 | UINT16\r |
| | 633 | EFIAPI\r |
| | 634 | PciSegmentBitFieldAnd16 (\r |
| | 635 | IN UINT64 Address,\r |
| | 636 | IN UINTN StartBit,\r |
| | 637 | IN UINTN EndBit,\r |
| | 638 | IN UINT16 AndData\r |
| | 639 | );\r |
| | 640 | \r |
| | 641 | /**\r |
| | 642 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| | 643 | bitwise OR, and writes the result back to the bit field in the\r |
| | 644 | 16-bit port.\r |
| | 645 | \r |
| | 646 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| | 647 | bitwise AND followed by a bitwise OR between the read result and\r |
| | 648 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| | 649 | configuration register specified by Address. The value written to the PCI\r |
| | 650 | configuration register is returned. This function must guarantee that all PCI\r |
| | 651 | read and write operations are serialized. Extra left bits in both AndData and\r |
| | 652 | OrData are stripped.\r |
| | 653 | \r |
| | 654 | If any reserved bits in Address are set, then ASSERT().\r |
| | 655 | If StartBit is greater than 15, then ASSERT().\r |
| | 656 | If EndBit is greater than 15, then ASSERT().\r |
| | 657 | If EndBit is less than StartBit, then ASSERT().\r |
| | 658 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 659 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 660 | \r |
| | 661 | @param Address PCI configuration register to write.\r |
| | 662 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 663 | Range 0..15.\r |
| | 664 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 665 | Range 0..15.\r |
| | 666 | @param AndData The value to AND with the PCI configuration register.\r |
| | 667 | @param OrData The value to OR with the result of the AND operation.\r |
| | 668 | \r |
| | 669 | @return The value written back to the PCI configuration register.\r |
| | 670 | \r |
| | 671 | **/\r |
| | 672 | UINT16\r |
| | 673 | EFIAPI\r |
| | 674 | PciSegmentBitFieldAndThenOr16 (\r |
| | 675 | IN UINT64 Address,\r |
| | 676 | IN UINTN StartBit,\r |
| | 677 | IN UINTN EndBit,\r |
| | 678 | IN UINT16 AndData,\r |
| | 679 | IN UINT16 OrData\r |
| | 680 | );\r |
| | 681 | \r |
| | 682 | /**\r |
| | 683 | Reads a 32-bit PCI configuration register.\r |
| | 684 | \r |
| | 685 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| | 686 | This function must guarantee that all PCI read and write operations are serialized.\r |
| | 687 | \r |
| | 688 | If any reserved bits in Address are set, then ASSERT().\r |
| | 689 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 690 | \r |
| | 691 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 692 | \r |
| | 693 | @return The 32-bit PCI configuration register specified by Address.\r |
| | 694 | \r |
| | 695 | **/\r |
| | 696 | UINT32\r |
| | 697 | EFIAPI\r |
| | 698 | PciSegmentRead32 (\r |
| | 699 | IN UINT64 Address\r |
| | 700 | );\r |
| | 701 | \r |
| | 702 | /**\r |
| | 703 | Writes a 32-bit PCI configuration register.\r |
| | 704 | \r |
| | 705 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r |
| | 706 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| | 707 | \r |
| | 708 | If any reserved bits in Address are set, then ASSERT().\r |
| | 709 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 710 | \r |
| | 711 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 712 | @param Value The value to write.\r |
| | 713 | \r |
| | 714 | @return The parameter of Value.\r |
| | 715 | \r |
| | 716 | **/\r |
| | 717 | UINT32\r |
| | 718 | EFIAPI\r |
| | 719 | PciSegmentWrite32 (\r |
| | 720 | IN UINT64 Address,\r |
| | 721 | IN UINT32 Value\r |
| | 722 | );\r |
| | 723 | \r |
| | 724 | /**\r |
| | 725 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r |
| | 726 | \r |
| | 727 | Reads the 32-bit PCI configuration register specified by Address,\r |
| | 728 | performs a bitwise OR between the read result and the value specified by OrData,\r |
| | 729 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| | 730 | The value written to the PCI configuration register is returned.\r |
| | 731 | This function must guarantee that all PCI read and write operations are serialized.\r |
| | 732 | \r |
| | 733 | If any reserved bits in Address are set, then ASSERT().\r |
| | 734 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 735 | \r |
| | 736 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 737 | @param OrData The value to OR with the PCI configuration register.\r |
| | 738 | \r |
| | 739 | @return The value written to the PCI configuration register.\r |
| | 740 | \r |
| | 741 | **/\r |
| | 742 | UINT32\r |
| | 743 | EFIAPI\r |
| | 744 | PciSegmentOr32 (\r |
| | 745 | IN UINT64 Address,\r |
| | 746 | IN UINT32 OrData\r |
| | 747 | );\r |
| | 748 | \r |
| | 749 | /**\r |
| | 750 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r |
| | 751 | \r |
| | 752 | Reads the 32-bit PCI configuration register specified by Address,\r |
| | 753 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| | 754 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| | 755 | The value written to the PCI configuration register is returned.\r |
| | 756 | This function must guarantee that all PCI read and write operations are serialized.\r |
| | 757 | \r |
| | 758 | If any reserved bits in Address are set, then ASSERT().\r |
| | 759 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 760 | \r |
| | 761 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 762 | @param AndData The value to AND with the PCI configuration register.\r |
| | 763 | \r |
| | 764 | @return The value written to the PCI configuration register.\r |
| | 765 | \r |
| | 766 | **/\r |
| | 767 | UINT32\r |
| | 768 | EFIAPI\r |
| | 769 | PciSegmentAnd32 (\r |
| | 770 | IN UINT64 Address,\r |
| | 771 | IN UINT32 AndData\r |
| | 772 | );\r |
| | 773 | \r |
| | 774 | /**\r |
| | 775 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r |
| | 776 | followed a bitwise OR with another 32-bit value.\r |
| | 777 | \r |
| | 778 | Reads the 32-bit PCI configuration register specified by Address,\r |
| | 779 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| | 780 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
| | 781 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| | 782 | The value written to the PCI configuration register is returned.\r |
| | 783 | This function must guarantee that all PCI read and write operations are serialized.\r |
| | 784 | \r |
| | 785 | If any reserved bits in Address are set, then ASSERT().\r |
| | 786 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 787 | \r |
| | 788 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 789 | @param AndData The value to AND with the PCI configuration register.\r |
| | 790 | @param OrData The value to OR with the PCI configuration register.\r |
| | 791 | \r |
| | 792 | @return The value written to the PCI configuration register.\r |
| | 793 | \r |
| | 794 | **/\r |
| | 795 | UINT32\r |
| | 796 | EFIAPI\r |
| | 797 | PciSegmentAndThenOr32 (\r |
| | 798 | IN UINT64 Address,\r |
| | 799 | IN UINT32 AndData,\r |
| | 800 | IN UINT32 OrData\r |
| | 801 | );\r |
| | 802 | \r |
| | 803 | /**\r |
| | 804 | Reads a bit field of a PCI configuration register.\r |
| | 805 | \r |
| | 806 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| | 807 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| | 808 | returned.\r |
| | 809 | \r |
| | 810 | If any reserved bits in Address are set, then ASSERT().\r |
| | 811 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 812 | If StartBit is greater than 31, then ASSERT().\r |
| | 813 | If EndBit is greater than 31, then ASSERT().\r |
| | 814 | If EndBit is less than StartBit, then ASSERT().\r |
| | 815 | \r |
| | 816 | @param Address PCI configuration register to read.\r |
| | 817 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 818 | Range 0..31.\r |
| | 819 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 820 | Range 0..31.\r |
| | 821 | \r |
| | 822 | @return The value of the bit field read from the PCI configuration register.\r |
| | 823 | \r |
| | 824 | **/\r |
| | 825 | UINT32\r |
| | 826 | EFIAPI\r |
| | 827 | PciSegmentBitFieldRead32 (\r |
| | 828 | IN UINT64 Address,\r |
| | 829 | IN UINTN StartBit,\r |
| | 830 | IN UINTN EndBit\r |
| | 831 | );\r |
| | 832 | \r |
| | 833 | /**\r |
| | 834 | Writes a bit field to a PCI configuration register.\r |
| | 835 | \r |
| | 836 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| | 837 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| | 838 | destination PCI configuration register are preserved. The new value of the\r |
| | 839 | 32-bit register is returned.\r |
| | 840 | \r |
| | 841 | If any reserved bits in Address are set, then ASSERT().\r |
| | 842 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 843 | If StartBit is greater than 31, then ASSERT().\r |
| | 844 | If EndBit is greater than 31, then ASSERT().\r |
| | 845 | If EndBit is less than StartBit, then ASSERT().\r |
| | 846 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 847 | \r |
| | 848 | @param Address PCI configuration register to write.\r |
| | 849 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 850 | Range 0..31.\r |
| | 851 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 852 | Range 0..31.\r |
| | 853 | @param Value New value of the bit field.\r |
| | 854 | \r |
| | 855 | @return The value written back to the PCI configuration register.\r |
| | 856 | \r |
| | 857 | **/\r |
| | 858 | UINT32\r |
| | 859 | EFIAPI\r |
| | 860 | PciSegmentBitFieldWrite32 (\r |
| | 861 | IN UINT64 Address,\r |
| | 862 | IN UINTN StartBit,\r |
| | 863 | IN UINTN EndBit,\r |
| | 864 | IN UINT32 Value\r |
| | 865 | );\r |
| | 866 | \r |
| | 867 | /**\r |
| | 868 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| | 869 | writes the result back to the bit field in the 32-bit port.\r |
| | 870 | \r |
| | 871 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| | 872 | bitwise OR between the read result and the value specified by\r |
| | 873 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| | 874 | specified by Address. The value written to the PCI configuration register is\r |
| | 875 | returned. This function must guarantee that all PCI read and write operations\r |
| | 876 | are serialized. Extra left bits in OrData are stripped.\r |
| | 877 | \r |
| | 878 | If any reserved bits in Address are set, then ASSERT().\r |
| | 879 | If StartBit is greater than 31, then ASSERT().\r |
| | 880 | If EndBit is greater than 31, then ASSERT().\r |
| | 881 | If EndBit is less than StartBit, then ASSERT().\r |
| | 882 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 883 | \r |
| | 884 | @param Address PCI configuration register to write.\r |
| | 885 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 886 | Range 0..31.\r |
| | 887 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 888 | Range 0..31.\r |
| | 889 | @param OrData The value to OR with the PCI configuration register.\r |
| | 890 | \r |
| | 891 | @return The value written back to the PCI configuration register.\r |
| | 892 | \r |
| | 893 | **/\r |
| | 894 | UINT32\r |
| | 895 | EFIAPI\r |
| | 896 | PciSegmentBitFieldOr32 (\r |
| | 897 | IN UINT64 Address,\r |
| | 898 | IN UINTN StartBit,\r |
| | 899 | IN UINTN EndBit,\r |
| | 900 | IN UINT32 OrData\r |
| | 901 | );\r |
| | 902 | \r |
| | 903 | /**\r |
| | 904 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| | 905 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| | 906 | \r |
| | 907 | \r |
| | 908 | Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r |
| | 909 | AND between the read result and the value specified by AndData, and writes the result\r |
| | 910 | to the 32-bit PCI configuration register specified by Address. The value written to\r |
| | 911 | the PCI configuration register is returned. This function must guarantee that all PCI\r |
| | 912 | read and write operations are serialized. Extra left bits in AndData are stripped.\r |
| | 913 | If any reserved bits in Address are set, then ASSERT().\r |
| | 914 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| | 915 | If StartBit is greater than 31, then ASSERT().\r |
| | 916 | If EndBit is greater than 31, then ASSERT().\r |
| | 917 | If EndBit is less than StartBit, then ASSERT().\r |
| | 918 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 919 | \r |
| | 920 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| | 921 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 922 | Range 0..31.\r |
| | 923 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 924 | Range 0..31.\r |
| | 925 | @param AndData The value to AND with the PCI configuration register.\r |
| | 926 | \r |
| | 927 | @return The value written back to the PCI configuration register.\r |
| | 928 | \r |
| | 929 | **/\r |
| | 930 | UINT32\r |
| | 931 | EFIAPI\r |
| | 932 | PciSegmentBitFieldAnd32 (\r |
| | 933 | IN UINT64 Address,\r |
| | 934 | IN UINTN StartBit,\r |
| | 935 | IN UINTN EndBit,\r |
| | 936 | IN UINT32 AndData\r |
| | 937 | );\r |
| | 938 | \r |
| | 939 | /**\r |
| | 940 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| | 941 | bitwise OR, and writes the result back to the bit field in the\r |
| | 942 | 32-bit port.\r |
| | 943 | \r |
| | 944 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| | 945 | bitwise AND followed by a bitwise OR between the read result and\r |
| | 946 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| | 947 | configuration register specified by Address. The value written to the PCI\r |
| | 948 | configuration register is returned. This function must guarantee that all PCI\r |
| | 949 | read and write operations are serialized. Extra left bits in both AndData and\r |
| | 950 | OrData are stripped.\r |
| | 951 | \r |
| | 952 | If any reserved bits in Address are set, then ASSERT().\r |
| | 953 | If StartBit is greater than 31, then ASSERT().\r |
| | 954 | If EndBit is greater than 31, then ASSERT().\r |
| | 955 | If EndBit is less than StartBit, then ASSERT().\r |
| | 956 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 957 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
| | 958 | \r |
| | 959 | @param Address PCI configuration register to write.\r |
| | 960 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| | 961 | Range 0..31.\r |
| | 962 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| | 963 | Range 0..31.\r |
| | 964 | @param AndData The value to AND with the PCI configuration register.\r |
| | 965 | @param OrData The value to OR with the result of the AND operation.\r |
| | 966 | \r |
| | 967 | @return The value written back to the PCI configuration register.\r |
| | 968 | \r |
| | 969 | **/\r |
| | 970 | UINT32\r |
| | 971 | EFIAPI\r |
| | 972 | PciSegmentBitFieldAndThenOr32 (\r |
| | 973 | IN UINT64 Address,\r |
| | 974 | IN UINTN StartBit,\r |
| | 975 | IN UINTN EndBit,\r |
| | 976 | IN UINT32 AndData,\r |
| | 977 | IN UINT32 OrData\r |
| | 978 | );\r |
| | 979 | \r |
| | 980 | /**\r |
| | 981 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| | 982 | \r |
| | 983 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| | 984 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| | 985 | configuration registers from a single PCI function to be read. Size is\r |
| | 986 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| | 987 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| | 988 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| | 989 | end of the range.\r |
| | 990 | \r |
| | 991 | If any reserved bits in StartAddress are set, then ASSERT().\r |
| | 992 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| | 993 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| | 994 | \r |
| | 995 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r |
| | 996 | Function and Register.\r |
| | 997 | @param Size Size in bytes of the transfer.\r |
| | 998 | @param Buffer Pointer to a buffer receiving the data read.\r |
| | 999 | \r |
| | 1000 | @return Size\r |
| | 1001 | \r |
| | 1002 | **/\r |
| | 1003 | UINTN\r |
| | 1004 | EFIAPI\r |
| | 1005 | PciSegmentReadBuffer (\r |
| | 1006 | IN UINT64 StartAddress,\r |
| | 1007 | IN UINTN Size,\r |
| | 1008 | OUT VOID *Buffer\r |
| | 1009 | );\r |
| | 1010 | \r |
| | 1011 | /**\r |
| | 1012 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| | 1013 | configuration space.\r |
| | 1014 | \r |
| | 1015 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| | 1016 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| | 1017 | configuration registers from a single PCI function to be written. Size is\r |
| | 1018 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| | 1019 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| | 1020 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| | 1021 | and the end of the range.\r |
| | 1022 | \r |
| | 1023 | If any reserved bits in StartAddress are set, then ASSERT().\r |
| | 1024 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| | 1025 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| | 1026 | \r |
| | 1027 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r |
| | 1028 | Function and Register.\r |
| | 1029 | @param Size Size in bytes of the transfer.\r |
| | 1030 | @param Buffer Pointer to a buffer containing the data to write.\r |
| | 1031 | \r |
| | 1032 | @return The parameter of Size.\r |
| | 1033 | \r |
| | 1034 | **/\r |
| | 1035 | UINTN\r |
| | 1036 | EFIAPI\r |
| | 1037 | PciSegmentWriteBuffer (\r |
| | 1038 | IN UINT64 StartAddress,\r |
| | 1039 | IN UINTN Size,\r |
| | 1040 | IN VOID *Buffer\r |
| | 1041 | );\r |
| | 1042 | \r |
| | 1043 | #endif\r |
projects / mirror_edk2.git / blame_incremental