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1 | /** @file\r | |
2 | Provides a service to retrieve a pointer to the PEI Services Table.\r | |
3 | \r | |
4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | \r | |
7 | **/\r | |
8 | \r | |
9 | #ifndef __PEI_SERVICES_TABLE_POINTER_LIB_H__\r | |
10 | #define __PEI_SERVICES_TABLE_POINTER_LIB_H__\r | |
11 | \r | |
12 | /**\r | |
13 | Retrieves the cached value of the PEI Services Table pointer.\r | |
14 | \r | |
15 | Returns the cached value of the PEI Services Table pointer in a CPU specific manner\r | |
16 | as specified in the CPU binding section of the Platform Initialization Pre-EFI\r | |
17 | Initialization Core Interface Specification.\r | |
18 | \r | |
19 | If the cached PEI Services Table pointer is NULL, then ASSERT().\r | |
20 | \r | |
21 | @return The pointer to PeiServices.\r | |
22 | \r | |
23 | **/\r | |
24 | CONST EFI_PEI_SERVICES **\r | |
25 | EFIAPI\r | |
26 | GetPeiServicesTablePointer (\r | |
27 | VOID\r | |
28 | );\r | |
29 | \r | |
30 | /**\r | |
31 | Caches a pointer PEI Services Table.\r | |
32 | \r | |
33 | Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer\r | |
34 | in a CPU specific manner as specified in the CPU binding section of the Platform Initialization\r | |
35 | Pre-EFI Initialization Core Interface Specification.\r | |
36 | \r | |
37 | If PeiServicesTablePointer is NULL, then ASSERT().\r | |
38 | \r | |
39 | @param PeiServicesTablePointer The address of PeiServices pointer.\r | |
40 | **/\r | |
41 | VOID\r | |
42 | EFIAPI\r | |
43 | SetPeiServicesTablePointer (\r | |
44 | IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer\r | |
45 | );\r | |
46 | \r | |
47 | /**\r | |
48 | Perform CPU specific actions required to migrate the PEI Services Table\r | |
49 | pointer from temporary RAM to permanent RAM.\r | |
50 | \r | |
51 | For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes\r | |
52 | immediately preceding the Interrupt Descriptor Table (IDT) in memory.\r | |
53 | For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes\r | |
54 | immediately preceding the Interrupt Descriptor Table (IDT) in memory.\r | |
55 | For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in\r | |
56 | a dedicated CPU register. This means that there is no memory storage\r | |
57 | associated with storing the PEI Services Table pointer, so no additional\r | |
58 | migration actions are required for Itanium or ARM CPUs.\r | |
59 | \r | |
60 | **/\r | |
61 | VOID\r | |
62 | EFIAPI\r | |
63 | MigratePeiServicesTablePointer (\r | |
64 | VOID\r | |
65 | );\r | |
66 | \r | |
67 | #endif\r |