[mirror_edk2.git] / MdePkg / Include / Protocol / PciRootBridgeIo.h

/** @file\r
  PCI Root Bridge I/O protocol as defined in the UEFI 2.0 specification.\r
\r
  PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O,\r
  and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform\r
  defferent types of bus mastering DMA.\r
\r
  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __PCI_ROOT_BRIDGE_IO_H__\r
#define __PCI_ROOT_BRIDGE_IO_H__\r
\r
#include <Library/BaseLib.h>\r
\r
#define EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \\r
  { \\r
    0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
  }\r
\r
typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
\r
///\r
/// *******************************************************\r
/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH\r
/// *******************************************************\r
///\r
typedef enum {\r
  EfiPciWidthUint8,\r
  EfiPciWidthUint16,\r
  EfiPciWidthUint32,\r
  EfiPciWidthUint64,\r
  EfiPciWidthFifoUint8,\r
  EfiPciWidthFifoUint16,\r
  EfiPciWidthFifoUint32,\r
  EfiPciWidthFifoUint64,\r
  EfiPciWidthFillUint8,\r
  EfiPciWidthFillUint16,\r
  EfiPciWidthFillUint32,\r
  EfiPciWidthFillUint64,\r
  EfiPciWidthMaximum\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH;\r
\r
///\r
/// *******************************************************\r
/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION\r
/// *******************************************************\r
///\r
typedef enum {\r
  ///\r
  /// A read operation from system memory by a bus master that is not capable of producing\r
  /// PCI dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterRead,\r
  ///\r
  /// A write operation from system memory by a bus master that is not capable of producing\r
  /// PCI dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterWrite,\r
  ///\r
  /// Provides both read and write access to system memory by both the processor and a bus\r
  /// master that is not capable of producing PCI dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterCommonBuffer,\r
  ///\r
  /// A read operation from system memory by a bus master that is capable of producing PCI\r
  /// dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterRead64,\r
  ///\r
  /// A write operation to system memory by a bus master that is capable of producing PCI\r
  /// dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterWrite64,\r
  ///\r
  /// Provides both read and write access to system memory by both the processor and a bus\r
  /// master that is capable of producing PCI dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterCommonBuffer64,\r
  EfiPciOperationMaximum\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;\r
\r
#define EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO          0x0001\r
#define EFI_PCI_ATTRIBUTE_ISA_IO                      0x0002\r
#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO              0x0004\r
#define EFI_PCI_ATTRIBUTE_VGA_MEMORY                  0x0008\r
#define EFI_PCI_ATTRIBUTE_VGA_IO                      0x0010\r
#define EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO              0x0020\r
#define EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO            0x0040\r
#define EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE        0x0080\r
#define EFI_PCI_ATTRIBUTE_MEMORY_CACHED               0x0800\r
#define EFI_PCI_ATTRIBUTE_MEMORY_DISABLE              0x1000\r
#define EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE          0x8000\r
#define EFI_PCI_ATTRIBUTE_ISA_IO_16                   0x10000\r
#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16           0x20000\r
#define EFI_PCI_ATTRIBUTE_VGA_IO_16                   0x40000\r
\r
#define EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER   (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED | EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE)\r
\r
#define EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER (~EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER)\r
\r
#define EFI_PCI_ADDRESS(bus, dev, func, reg) \\r
  (UINT64) ( \\r
  (((UINTN) bus) << 24) | \\r
  (((UINTN) dev) << 16) | \\r
  (((UINTN) func) << 8) | \\r
  (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))\r
\r
typedef struct {\r
  UINT8   Register;\r
  UINT8   Function;\r
  UINT8   Device;\r
  UINT8   Bus;\r
  UINT32  ExtendedRegister;\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS;\r
\r
/**\r
  Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
  satisfied or after a defined duration.\r
\r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Width                 Signifies the width of the memory or I/O operations.\r
  @param  Address               The base address of the memory or I/O operations.\r
  @param  Mask                  Mask used for the polling criteria.\r
  @param  Value                 The comparison value used for the polling exit criteria.\r
  @param  Delay                 The number of 100 ns units to poll.\r
  @param  Result                Pointer to the last value read from the memory location.\r
\r
  @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.\r
  @retval EFI_TIMEOUT           Delay expired before a match occurred.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN  UINT64                                   Address,\r
  IN  UINT64                                   Mask,\r
  IN  UINT64                                   Value,\r
  IN  UINT64                                   Delay,\r
  OUT UINT64                                   *Result\r
  );\r
\r
/**\r
  Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
\r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Width                 Signifies the width of the memory operations.\r
  @param  Address               The base address of the memory operations.\r
  @param  Count                 The number of memory operations to perform.\r
  @param  Buffer                For read operations, the destination buffer to store the results. For write\r
                                operations, the source buffer to write data from.\r
\r
  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT64                                   Address,\r
  IN     UINTN                                    Count,\r
  IN OUT VOID                                     *Buffer\r
  );\r
\r
typedef struct {\r
  ///\r
  /// Read PCI controller registers in the PCI root bridge memory space.\r
  ///\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Read;\r
  ///\r
  /// Write PCI controller registers in the PCI root bridge memory space.\r
  ///\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Write;\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;\r
\r
/**\r
  Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
  root bridge memory space.\r
\r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
  @param  Width                 Signifies the width of the memory operations.\r
  @param  DestAddress           The destination address of the memory operation.\r
  @param  SrcAddress            The source address of the memory operation.\r
  @param  Count                 The number of memory operations to perform.\r
\r
  @retval EFI_SUCCESS           The data was copied from one memory region to another memory region.\r
  @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT64                                   DestAddress,\r
  IN     UINT64                                   SrcAddress,\r
  IN     UINTN                                    Count\r
  );\r
\r
/**\r
  Provides the PCI controller-specific addresses required to access system memory from a\r
  DMA bus master.\r
\r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Operation             Indicates if the bus master is going to read or write to system memory.\r
  @param  HostAddress           The system memory address to map to the PCI controller.\r
  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes\r
                                that were mapped.\r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param  Mapping               A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL                *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,\r
  IN     VOID                                       *HostAddress,\r
  IN OUT UINTN                                      *NumberOfBytes,\r
  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,\r
  OUT    VOID                                       **Mapping\r
  );\r
\r
/**\r
  Completes the Map() operation and releases any corresponding resources.\r
\r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Mapping               The mapping value returned from Map().\r
\r
  @retval EFI_SUCCESS           The range was unmapped.\r
  @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  IN  VOID                                     *Mapping\r
  );\r
\r
/**\r
  Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
  EfiPciOperationBusMasterCommonBuffer64 mapping.\r
\r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Type                  This parameter is not used and must be ignored.\r
  @param  MemoryType            The type of memory to allocate, EfiBootServicesData or\r
                                EfiRuntimeServicesData.\r
  @param  Pages                 The number of pages to allocate.\r
  @param  HostAddress           A pointer to store the base system memory address of the\r
                                allocated range.\r
  @param  Attributes            The requested bit mask of attributes for the allocated range.\r
\r
  @retval EFI_SUCCESS           The requested memory pages were allocated.\r
  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are\r
                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_ALLOCATE_TYPE                        Type,\r
  IN     EFI_MEMORY_TYPE                          MemoryType,\r
  IN     UINTN                                    Pages,\r
  IN OUT VOID                                     **HostAddress,\r
  IN     UINT64                                   Attributes\r
  );\r
\r
/**\r
  Frees memory that was allocated with AllocateBuffer().\r
\r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Pages                 The number of pages to free.\r
  @param  HostAddress           The base system memory address of the allocated range.\r
\r
  @retval EFI_SUCCESS           The requested memory pages were freed.\r
  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
                                was not allocated with AllocateBuffer().\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  IN  UINTN                                    Pages,\r
  IN  VOID                                     *HostAddress\r
  );\r
\r
/**\r
  Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
\r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
\r
  @retval EFI_SUCCESS           The PCI posted write transactions were flushed from the PCI host\r
                                bridge to system memory.\r
  @retval EFI_DEVICE_ERROR      The PCI posted write transactions were not flushed from the PCI\r
                                host bridge due to a hardware error.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This\r
  );\r
\r
/**\r
  Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
  attributes that a PCI root bridge is currently using.\r
\r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Supports              A pointer to the mask of attributes that this PCI root bridge supports\r
                                setting with SetAttributes().\r
  @param  Attributes            A pointer to the mask of attributes that this PCI root bridge is currently\r
                                using.\r
\r
  @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI root\r
                                bridge supports is returned in Supports. If Attributes is\r
                                not NULL, then the attributes that the PCI root bridge is currently\r
                                using is returned in Attributes.\r
  @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  OUT UINT64                                   *Supports,\r
  OUT UINT64                                   *Attributes\r
  );\r
\r
/**\r
  Sets attributes for a resource range on a PCI root bridge.\r
\r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Attributes            The mask of attributes to set.\r
  @param  ResourceBase          A pointer to the base address of the resource range to be modified by the\r
                                attributes specified by Attributes.\r
  @param  ResourceLength        A pointer to the length of the resource range to be modified by the\r
                                attributes specified by Attributes.\r
\r
  @retval EFI_SUCCESS           The set of attributes specified by Attributes for the resource\r
                                range specified by ResourceBase and ResourceLength\r
                                were set on the PCI root bridge, and the actual resource range is\r
                                returned in ResuourceBase and ResourceLength.\r
  @retval EFI_UNSUPPORTED       A bit is set in Attributes that is not supported by the PCI Root\r
                                Bridge.\r
  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to set the attributes on the\r
                                resource range specified by BaseAddress and Length.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     UINT64                                   Attributes,\r
  IN OUT UINT64                                   *ResourceBase,\r
  IN OUT UINT64                                   *ResourceLength\r
  );\r
\r
/**\r
  Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI\r
  resource descriptors.\r
\r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Resources             A pointer to the resource descriptors that describe the current\r
                                configuration of this PCI root bridge.\r
\r
  @retval EFI_SUCCESS           The current configuration of this PCI root bridge was returned in\r
                                Resources.\r
  @retval EFI_UNSUPPORTED       The current configuration of this PCI root bridge could not be\r
                                retrieved.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION)(\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL          *This,\r
  OUT VOID                                     **Resources\r
  );\r
\r
///\r
/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are\r
/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller.\r
///\r
struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {\r
  ///\r
  /// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
  ///\r
  EFI_HANDLE                                      ParentHandle;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM     PollMem;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM     PollIo;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS          Mem;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS          Io;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS          Pci;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM        CopyMem;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP             Map;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP           Unmap;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER     FreeBuffer;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH           Flush;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES  GetAttributes;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES  SetAttributes;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION   Configuration;\r
\r
  ///\r
  /// The segment number that this PCI root bridge resides.\r
  ///\r
  UINT32                                          SegmentNumber;\r
};\r
\r
extern EFI_GUID gEfiPciRootBridgeIoProtocolGuid;\r
\r
#endif\r
Commit	Line	Data
	1	/** @file\r
	2	PCI Root Bridge I/O protocol as defined in the UEFI 2.0 specification.\r
	3	\r
	4	PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O,\r
	5	and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform\r
	6	defferent types of bus mastering DMA.\r
	7	\r
	8	Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
	9	SPDX-License-Identifier: BSD-2-Clause-Patent\r
	10	\r
	11	**/\r
	12	\r
	13	#ifndef __PCI_ROOT_BRIDGE_IO_H__\r
	14	#define __PCI_ROOT_BRIDGE_IO_H__\r
	15	\r
	16	#include <Library/BaseLib.h>\r
	17	\r
	18	#define EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \\r
	19	{ \\r
	20	0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
	21	}\r
	22	\r
	23	typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
	24	\r
	25	///\r
	26	/// *******************************************************\r
	27	/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH\r
	28	/// *******************************************************\r
	29	///\r
	30	typedef enum {\r
	31	EfiPciWidthUint8,\r
	32	EfiPciWidthUint16,\r
	33	EfiPciWidthUint32,\r
	34	EfiPciWidthUint64,\r
	35	EfiPciWidthFifoUint8,\r
	36	EfiPciWidthFifoUint16,\r
	37	EfiPciWidthFifoUint32,\r
	38	EfiPciWidthFifoUint64,\r
	39	EfiPciWidthFillUint8,\r
	40	EfiPciWidthFillUint16,\r
	41	EfiPciWidthFillUint32,\r
	42	EfiPciWidthFillUint64,\r
	43	EfiPciWidthMaximum\r
	44	} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH;\r
	45	\r
	46	///\r
	47	/// *******************************************************\r
	48	/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION\r
	49	/// *******************************************************\r
	50	///\r
	51	typedef enum {\r
	52	///\r
	53	/// A read operation from system memory by a bus master that is not capable of producing\r
	54	/// PCI dual address cycles.\r
	55	///\r
	56	EfiPciOperationBusMasterRead,\r
	57	///\r
	58	/// A write operation from system memory by a bus master that is not capable of producing\r
	59	/// PCI dual address cycles.\r
	60	///\r
	61	EfiPciOperationBusMasterWrite,\r
	62	///\r
	63	/// Provides both read and write access to system memory by both the processor and a bus\r
	64	/// master that is not capable of producing PCI dual address cycles.\r
	65	///\r
	66	EfiPciOperationBusMasterCommonBuffer,\r
	67	///\r
	68	/// A read operation from system memory by a bus master that is capable of producing PCI\r
	69	/// dual address cycles.\r
	70	///\r
	71	EfiPciOperationBusMasterRead64,\r
	72	///\r
	73	/// A write operation to system memory by a bus master that is capable of producing PCI\r
	74	/// dual address cycles.\r
	75	///\r
	76	EfiPciOperationBusMasterWrite64,\r
	77	///\r
	78	/// Provides both read and write access to system memory by both the processor and a bus\r
	79	/// master that is capable of producing PCI dual address cycles.\r
	80	///\r
	81	EfiPciOperationBusMasterCommonBuffer64,\r
	82	EfiPciOperationMaximum\r
	83	} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;\r
	84	\r
	85	#define EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001\r
	86	#define EFI_PCI_ATTRIBUTE_ISA_IO 0x0002\r
	87	#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO 0x0004\r
	88	#define EFI_PCI_ATTRIBUTE_VGA_MEMORY 0x0008\r
	89	#define EFI_PCI_ATTRIBUTE_VGA_IO 0x0010\r
	90	#define EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO 0x0020\r
	91	#define EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO 0x0040\r
	92	#define EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080\r
	93	#define EFI_PCI_ATTRIBUTE_MEMORY_CACHED 0x0800\r
	94	#define EFI_PCI_ATTRIBUTE_MEMORY_DISABLE 0x1000\r
	95	#define EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000\r
	96	#define EFI_PCI_ATTRIBUTE_ISA_IO_16 0x10000\r
	97	#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000\r
	98	#define EFI_PCI_ATTRIBUTE_VGA_IO_16 0x40000\r
	99	\r
	100	#define EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE \| EFI_PCI_ATTRIBUTE_MEMORY_CACHED \| EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE)\r
	101	\r
	102	#define EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER (~EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER)\r
	103	\r
	104	#define EFI_PCI_ADDRESS(bus, dev, func, reg) \\r
	105	(UINT64) ( \\r
	106	(((UINTN) bus) << 24) \| \\r
	107	(((UINTN) dev) << 16) \| \\r
	108	(((UINTN) func) << 8) \| \\r
	109	(((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))\r
	110	\r
	111	typedef struct {\r
	112	UINT8 Register;\r
	113	UINT8 Function;\r
	114	UINT8 Device;\r
	115	UINT8 Bus;\r
	116	UINT32 ExtendedRegister;\r
	117	} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS;\r
	118	\r
	119	/**\r
	120	Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
	121	satisfied or after a defined duration.\r
	122	\r
	123	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	124	@param Width Signifies the width of the memory or I/O operations.\r
	125	@param Address The base address of the memory or I/O operations.\r
	126	@param Mask Mask used for the polling criteria.\r
	127	@param Value The comparison value used for the polling exit criteria.\r
	128	@param Delay The number of 100 ns units to poll.\r
	129	@param Result Pointer to the last value read from the memory location.\r
	130	\r
	131	@retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
	132	@retval EFI_TIMEOUT Delay expired before a match occurred.\r
	133	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	134	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	135	\r
	136	**/\r
	137	typedef\r
	138	EFI_STATUS\r
	139	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM)(\r
	140	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	141	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
	142	IN UINT64 Address,\r
	143	IN UINT64 Mask,\r
	144	IN UINT64 Value,\r
	145	IN UINT64 Delay,\r
	146	OUT UINT64 *Result\r
	147	);\r
	148	\r
	149	/**\r
	150	Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
	151	\r
	152	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	153	@param Width Signifies the width of the memory operations.\r
	154	@param Address The base address of the memory operations.\r
	155	@param Count The number of memory operations to perform.\r
	156	@param Buffer For read operations, the destination buffer to store the results. For write\r
	157	operations, the source buffer to write data from.\r
	158	\r
	159	@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
	160	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	161	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	162	\r
	163	**/\r
	164	typedef\r
	165	EFI_STATUS\r
	166	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM)(\r
	167	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	168	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
	169	IN UINT64 Address,\r
	170	IN UINTN Count,\r
	171	IN OUT VOID *Buffer\r
	172	);\r
	173	\r
	174	typedef struct {\r
	175	///\r
	176	/// Read PCI controller registers in the PCI root bridge memory space.\r
	177	///\r
	178	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Read;\r
	179	///\r
	180	/// Write PCI controller registers in the PCI root bridge memory space.\r
	181	///\r
	182	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Write;\r
	183	} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;\r
	184	\r
	185	/**\r
	186	Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
	187	root bridge memory space.\r
	188	\r
	189	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
	190	@param Width Signifies the width of the memory operations.\r
	191	@param DestAddress The destination address of the memory operation.\r
	192	@param SrcAddress The source address of the memory operation.\r
	193	@param Count The number of memory operations to perform.\r
	194	\r
	195	@retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
	196	@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
	197	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	198	\r
	199	**/\r
	200	typedef\r
	201	EFI_STATUS\r
	202	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM)(\r
	203	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	204	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
	205	IN UINT64 DestAddress,\r
	206	IN UINT64 SrcAddress,\r
	207	IN UINTN Count\r
	208	);\r
	209	\r
	210	/**\r
	211	Provides the PCI controller-specific addresses required to access system memory from a\r
	212	DMA bus master.\r
	213	\r
	214	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	215	@param Operation Indicates if the bus master is going to read or write to system memory.\r
	216	@param HostAddress The system memory address to map to the PCI controller.\r
	217	@param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
	218	that were mapped.\r
	219	@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
	220	access the hosts HostAddress.\r
	221	@param Mapping A resulting value to pass to Unmap().\r
	222	\r
	223	@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
	224	@retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
	225	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	226	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	227	@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
	228	\r
	229	**/\r
	230	typedef\r
	231	EFI_STATUS\r
	232	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP)(\r
	233	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	234	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
	235	IN VOID *HostAddress,\r
	236	IN OUT UINTN *NumberOfBytes,\r
	237	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
	238	OUT VOID **Mapping\r
	239	);\r
	240	\r
	241	/**\r
	242	Completes the Map() operation and releases any corresponding resources.\r
	243	\r
	244	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	245	@param Mapping The mapping value returned from Map().\r
	246	\r
	247	@retval EFI_SUCCESS The range was unmapped.\r
	248	@retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
	249	@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
	250	\r
	251	**/\r
	252	typedef\r
	253	EFI_STATUS\r
	254	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP)(\r
	255	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	256	IN VOID *Mapping\r
	257	);\r
	258	\r
	259	/**\r
	260	Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
	261	EfiPciOperationBusMasterCommonBuffer64 mapping.\r
	262	\r
	263	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	264	@param Type This parameter is not used and must be ignored.\r
	265	@param MemoryType The type of memory to allocate, EfiBootServicesData or\r
	266	EfiRuntimeServicesData.\r
	267	@param Pages The number of pages to allocate.\r
	268	@param HostAddress A pointer to store the base system memory address of the\r
	269	allocated range.\r
	270	@param Attributes The requested bit mask of attributes for the allocated range.\r
	271	\r
	272	@retval EFI_SUCCESS The requested memory pages were allocated.\r
	273	@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
	274	MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
	275	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	276	@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
	277	\r
	278	**/\r
	279	typedef\r
	280	EFI_STATUS\r
	281	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER)(\r
	282	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	283	IN EFI_ALLOCATE_TYPE Type,\r
	284	IN EFI_MEMORY_TYPE MemoryType,\r
	285	IN UINTN Pages,\r
	286	IN OUT VOID **HostAddress,\r
	287	IN UINT64 Attributes\r
	288	);\r
	289	\r
	290	/**\r
	291	Frees memory that was allocated with AllocateBuffer().\r
	292	\r
	293	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	294	@param Pages The number of pages to free.\r
	295	@param HostAddress The base system memory address of the allocated range.\r
	296	\r
	297	@retval EFI_SUCCESS The requested memory pages were freed.\r
	298	@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
	299	was not allocated with AllocateBuffer().\r
	300	\r
	301	**/\r
	302	typedef\r
	303	EFI_STATUS\r
	304	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER)(\r
	305	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	306	IN UINTN Pages,\r
	307	IN VOID *HostAddress\r
	308	);\r
	309	\r
	310	/**\r
	311	Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
	312	\r
	313	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	314	\r
	315	@retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
	316	bridge to system memory.\r
	317	@retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
	318	host bridge due to a hardware error.\r
	319	\r
	320	**/\r
	321	typedef\r
	322	EFI_STATUS\r
	323	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH)(\r
	324	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
	325	);\r
	326	\r
	327	/**\r
	328	Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
	329	attributes that a PCI root bridge is currently using.\r
	330	\r
	331	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	332	@param Supports A pointer to the mask of attributes that this PCI root bridge supports\r
	333	setting with SetAttributes().\r
	334	@param Attributes A pointer to the mask of attributes that this PCI root bridge is currently\r
	335	using.\r
	336	\r
	337	@retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root\r
	338	bridge supports is returned in Supports. If Attributes is\r
	339	not NULL, then the attributes that the PCI root bridge is currently\r
	340	using is returned in Attributes.\r
	341	@retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
	342	\r
	343	\r
	344	**/\r
	345	typedef\r
	346	EFI_STATUS\r
	347	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES)(\r
	348	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	349	OUT UINT64 *Supports,\r
	350	OUT UINT64 *Attributes\r
	351	);\r
	352	\r
	353	/**\r
	354	Sets attributes for a resource range on a PCI root bridge.\r
	355	\r
	356	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	357	@param Attributes The mask of attributes to set.\r
	358	@param ResourceBase A pointer to the base address of the resource range to be modified by the\r
	359	attributes specified by Attributes.\r
	360	@param ResourceLength A pointer to the length of the resource range to be modified by the\r
	361	attributes specified by Attributes.\r
	362	\r
	363	@retval EFI_SUCCESS The set of attributes specified by Attributes for the resource\r
	364	range specified by ResourceBase and ResourceLength\r
	365	were set on the PCI root bridge, and the actual resource range is\r
	366	returned in ResuourceBase and ResourceLength.\r
	367	@retval EFI_UNSUPPORTED A bit is set in Attributes that is not supported by the PCI Root\r
	368	Bridge.\r
	369	@retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
	370	resource range specified by BaseAddress and Length.\r
	371	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	372	\r
	373	**/\r
	374	typedef\r
	375	EFI_STATUS\r
	376	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES)(\r
	377	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	378	IN UINT64 Attributes,\r
	379	IN OUT UINT64 *ResourceBase,\r
	380	IN OUT UINT64 *ResourceLength\r
	381	);\r
	382	\r
	383	/**\r
	384	Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI\r
	385	resource descriptors.\r
	386	\r
	387	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	388	@param Resources A pointer to the resource descriptors that describe the current\r
	389	configuration of this PCI root bridge.\r
	390	\r
	391	@retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in\r
	392	Resources.\r
	393	@retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be\r
	394	retrieved.\r
	395	\r
	396	**/\r
	397	typedef\r
	398	EFI_STATUS\r
	399	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION)(\r
	400	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	401	OUT VOID **Resources\r
	402	);\r
	403	\r
	404	///\r
	405	/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are\r
	406	/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller.\r
	407	///\r
	408	struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {\r
	409	///\r
	410	/// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
	411	///\r
	412	EFI_HANDLE ParentHandle;\r
	413	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
	414	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
	415	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Mem;\r
	416	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Io;\r
	417	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Pci;\r
	418	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM CopyMem;\r
	419	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP Map;\r
	420	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP Unmap;\r
	421	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
	422	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
	423	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH Flush;\r
	424	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES GetAttributes;\r
	425	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES SetAttributes;\r
	426	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION Configuration;\r
	427	\r
	428	///\r
	429	/// The segment number that this PCI root bridge resides.\r
	430	///\r
	431	UINT32 SegmentNumber;\r
	432	};\r
	433	\r
	434	extern EFI_GUID gEfiPciRootBridgeIoProtocolGuid;\r
	435	\r
	436	#endif\r