[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / x86Cache.c

/** @file\r
  Cache Maintenance Functions.\r
\r
  Copyright (c) 2006, Intel Corporation<BR>\r
  All rights reserved. This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
  Module Name:  x86Cache.c\r
\r
**/\r
\r
/**\r
  Invalidates the entire instruction cache in cache coherency domain of the\r
  calling CPU.\r
\r
  Invalidates the entire instruction cache in cache coherency domain of the\r
  calling CPU.\r
\r
**/\r
VOID\r
EFIAPI\r
InvalidateInstructionCache (\r
  VOID\r
  )\r
{\r
}\r
\r
/**\r
  Invalidates a range of instruction cache lines in the cache coherency domain\r
  of the calling CPU.\r
\r
  Invalidates the instruction cache lines specified by Address and Length. If\r
  Address is not aligned on a cache line boundary, then entire instruction\r
  cache line containing Address is invalidated. If Address + Length is not\r
  aligned on a cache line boundary, then the entire instruction cache line\r
  containing Address + Length -1 is invalidated. This function may choose to\r
  invalidate the entire instruction cache if that is more efficient than\r
  invalidating the specified range. If Length is 0, the no instruction cache\r
  lines are invalidated. Address is returned.\r
\r
  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
\r
  @param  Address The base address of the instruction cache lines to\r
                  invalidate. If the CPU is in a physical addressing mode, then\r
                  Address is a physical address. If the CPU is in a virtual\r
                  addressing mode, then Address is a virtual address.\r
\r
  @param  Length  The number of bytes to invalidate from the instruction cache.\r
\r
  @return Address\r
\r
**/\r
VOID *\r
EFIAPI\r
InvalidateInstructionCacheRange (\r
  IN      VOID                      *Address,\r
  IN      UINTN                     Length\r
  )\r
{\r
  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
  return Address;\r
}\r
\r
/**\r
  Writes Back and Invalidates the entire data cache in cache coherency domain\r
  of the calling CPU.\r
\r
  Writes Back and Invalidates the entire data cache in cache coherency domain\r
  of the calling CPU. This function guarantees that all dirty cache lines are\r
  written back to system memory, and also invalidates all the data cache lines\r
  in the cache coherency domain of the calling CPU.\r
\r
**/\r
VOID\r
EFIAPI\r
WriteBackInvalidateDataCache (\r
  VOID\r
  )\r
{\r
  AsmWbinvd ();\r
}\r
\r
/**\r
  Writes Back and Invalidates a range of data cache lines in the cache\r
  coherency domain of the calling CPU.\r
\r
  Writes Back and Invalidate the data cache lines specified by Address and\r
  Length. If Address is not aligned on a cache line boundary, then entire data\r
  cache line containing Address is written back and invalidated. If Address +\r
  Length is not aligned on a cache line boundary, then the entire data cache\r
  line containing Address + Length -1 is written back and invalidated. This\r
  function may choose to write back and invalidate the entire data cache if\r
  that is more efficient than writing back and invalidating the specified\r
  range. If Length is 0, the no data cache lines are written back and\r
  invalidated. Address is returned.\r
\r
  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
\r
  @param  Address The base address of the data cache lines to write back and\r
                  invalidate. If the CPU is in a physical addressing mode, then\r
                  Address is a physical address. If the CPU is in a virtual\r
                  addressing mode, then Address is a virtual address.\r
  @param  Length  The number of bytes to write back and invalidate from the\r
                  data cache.\r
\r
  @return Address\r
\r
**/\r
VOID *\r
EFIAPI\r
WriteBackInvalidateDataCacheRange (\r
  IN      VOID                      *Address,\r
  IN      UINTN                     Length\r
  )\r
{\r
  UINT8                             (*Uint8Ptr)[32];\r
\r
  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
\r
  Uint8Ptr = Address;\r
  while (Length > sizeof (*Uint8Ptr)) {\r
    AsmFlushCacheLine (Uint8Ptr++);\r
    Length -= sizeof (*Uint8Ptr);\r
  }\r
  if (Length > 0) {\r
    AsmFlushCacheLine (Uint8Ptr);\r
    AsmFlushCacheLine (&(*Uint8Ptr)[Length - 1]);\r
  }\r
  return Address;\r
}\r
\r
/**\r
  Writes Back the entire data cache in cache coherency domain of the calling\r
  CPU.\r
\r
  Writes Back the entire data cache in cache coherency domain of the calling\r
  CPU. This function guarantees that all dirty cache lines are written back to\r
  system memory. This function may also invalidate all the data cache lines in\r
  the cache coherency domain of the calling CPU.\r
\r
**/\r
VOID\r
EFIAPI\r
WriteBackDataCache (\r
  VOID\r
  )\r
{\r
  WriteBackInvalidateDataCache ();\r
}\r
\r
/**\r
  Writes Back a range of data cache lines in the cache coherency domain of the\r
  calling CPU.\r
\r
  Writes Back the data cache lines specified by Address and Length. If Address\r
  is not aligned on a cache line boundary, then entire data cache line\r
  containing Address is written back. If Address + Length is not aligned on a\r
  cache line boundary, then the entire data cache line containing Address +\r
  Length -1 is written back. This function may choose to write back the entire\r
  data cache if that is more efficient than writing back the specified range.\r
  If Length is 0, the no data cache lines are written back. This function may\r
  also invalidate all the data cache lines in the specified range of the cache\r
  coherency domain of the calling CPU. Address is returned.\r
\r
  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
\r
  @param  Address The base address of the data cache lines to write back. If\r
                  the CPU is in a physical addressing mode, then Address is a\r
                  physical address. If the CPU is in a virtual addressing\r
                  mode, then Address is a virtual address.\r
  @param  Length  The number of bytes to write back from the data cache.\r
\r
  @return Address\r
\r
**/\r
VOID *\r
EFIAPI\r
WriteBackDataCacheRange (\r
  IN      VOID                      *Address,\r
  IN      UINTN                     Length\r
  )\r
{\r
  return WriteBackInvalidateDataCacheRange (Address, Length);\r
}\r
\r
/**\r
  Invalidates the entire data cache in cache coherency domain of the calling\r
  CPU.\r
\r
  Invalidates the entire data cache in cache coherency domain of the calling\r
  CPU. This function must be used with care because dirty cache lines are not\r
  written back to system memory. It is typically used for cache diagnostics. If\r
  the CPU does not support invalidation of the entire data cache, then a write\r
  back and invalidate operation should be performed on the entire data cache.\r
\r
**/\r
VOID\r
EFIAPI\r
InvalidateDataCache (\r
  VOID\r
  )\r
{\r
  AsmInvd ();\r
}\r
\r
/**\r
  Invalidates a range of data cache lines in the cache coherency domain of the\r
  calling CPU.\r
\r
  Invalidates the data cache lines specified by Address and Length. If Address\r
  is not aligned on a cache line boundary, then entire data cache line\r
  containing Address is invalidated. If Address + Length is not aligned on a\r
  cache line boundary, then the entire data cache line containing Address +\r
  Length -1 is invalidated. This function must never invalidate any cache lines\r
  outside the specified range. If Length is 0, the no data cache lines are\r
  invalidated. Address is returned. This function must be used with care\r
  because dirty cache lines are not written back to system memory. It is\r
  typically used for cache diagnostics. If the CPU does not support\r
  invalidation of a data cache range, then a write back and invalidate\r
  operation should be performed on the data cache range.\r
\r
  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
\r
  @param  Address The base address of the data cache lines to invalidate. If\r
                  the CPU is in a physical addressing mode, then Address is a\r
                  physical address. If the CPU is in a virtual addressing mode,\r
                  then Address is a virtual address.\r
  @param  Length  The number of bytes to invalidate from the data cache.\r
\r
  @return Address\r
\r
**/\r
VOID *\r
EFIAPI\r
InvalidateDataCacheRange (\r
  IN      VOID                      *Address,\r
  IN      UINTN                     Length\r
  )\r
{\r
  return WriteBackInvalidateDataCacheRange (Address, Length);\r
}\r
Commit	Line	Data
	1	/** @file\r
	2	Cache Maintenance Functions.\r
	3	\r
	4	Copyright (c) 2006, Intel Corporation<BR>\r
	5	All rights reserved. This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	Module Name: x86Cache.c\r
	14	\r
	15	**/\r
	16	\r
	17	/**\r
	18	Invalidates the entire instruction cache in cache coherency domain of the\r
	19	calling CPU.\r
	20	\r
	21	Invalidates the entire instruction cache in cache coherency domain of the\r
	22	calling CPU.\r
	23	\r
	24	**/\r
	25	VOID\r
	26	EFIAPI\r
	27	InvalidateInstructionCache (\r
	28	VOID\r
	29	)\r
	30	{\r
	31	}\r
	32	\r
	33	/**\r
	34	Invalidates a range of instruction cache lines in the cache coherency domain\r
	35	of the calling CPU.\r
	36	\r
	37	Invalidates the instruction cache lines specified by Address and Length. If\r
	38	Address is not aligned on a cache line boundary, then entire instruction\r
	39	cache line containing Address is invalidated. If Address + Length is not\r
	40	aligned on a cache line boundary, then the entire instruction cache line\r
	41	containing Address + Length -1 is invalidated. This function may choose to\r
	42	invalidate the entire instruction cache if that is more efficient than\r
	43	invalidating the specified range. If Length is 0, the no instruction cache\r
	44	lines are invalidated. Address is returned.\r
	45	\r
	46	If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
	47	\r
	48	@param Address The base address of the instruction cache lines to\r
	49	invalidate. If the CPU is in a physical addressing mode, then\r
	50	Address is a physical address. If the CPU is in a virtual\r
	51	addressing mode, then Address is a virtual address.\r
	52	\r
	53	@param Length The number of bytes to invalidate from the instruction cache.\r
	54	\r
	55	@return Address\r
	56	\r
	57	**/\r
	58	VOID *\r
	59	EFIAPI\r
	60	InvalidateInstructionCacheRange (\r
	61	IN VOID *Address,\r
	62	IN UINTN Length\r
	63	)\r
	64	{\r
	65	ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
	66	return Address;\r
	67	}\r
	68	\r
	69	/**\r
	70	Writes Back and Invalidates the entire data cache in cache coherency domain\r
	71	of the calling CPU.\r
	72	\r
	73	Writes Back and Invalidates the entire data cache in cache coherency domain\r
	74	of the calling CPU. This function guarantees that all dirty cache lines are\r
	75	written back to system memory, and also invalidates all the data cache lines\r
	76	in the cache coherency domain of the calling CPU.\r
	77	\r
	78	**/\r
	79	VOID\r
	80	EFIAPI\r
	81	WriteBackInvalidateDataCache (\r
	82	VOID\r
	83	)\r
	84	{\r
	85	AsmWbinvd ();\r
	86	}\r
	87	\r
	88	/**\r
	89	Writes Back and Invalidates a range of data cache lines in the cache\r
	90	coherency domain of the calling CPU.\r
	91	\r
	92	Writes Back and Invalidate the data cache lines specified by Address and\r
	93	Length. If Address is not aligned on a cache line boundary, then entire data\r
	94	cache line containing Address is written back and invalidated. If Address +\r
	95	Length is not aligned on a cache line boundary, then the entire data cache\r
	96	line containing Address + Length -1 is written back and invalidated. This\r
	97	function may choose to write back and invalidate the entire data cache if\r
	98	that is more efficient than writing back and invalidating the specified\r
	99	range. If Length is 0, the no data cache lines are written back and\r
	100	invalidated. Address is returned.\r
	101	\r
	102	If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
	103	\r
	104	@param Address The base address of the data cache lines to write back and\r
	105	invalidate. If the CPU is in a physical addressing mode, then\r
	106	Address is a physical address. If the CPU is in a virtual\r
	107	addressing mode, then Address is a virtual address.\r
	108	@param Length The number of bytes to write back and invalidate from the\r
	109	data cache.\r
	110	\r
	111	@return Address\r
	112	\r
	113	**/\r
	114	VOID *\r
	115	EFIAPI\r
	116	WriteBackInvalidateDataCacheRange (\r
	117	IN VOID *Address,\r
	118	IN UINTN Length\r
	119	)\r
	120	{\r
	121	UINT8 (*Uint8Ptr)[32];\r
	122	\r
	123	ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
	124	\r
	125	Uint8Ptr = Address;\r
	126	while (Length > sizeof (*Uint8Ptr)) {\r
	127	AsmFlushCacheLine (Uint8Ptr++);\r
	128	Length -= sizeof (*Uint8Ptr);\r
	129	}\r
	130	if (Length > 0) {\r
	131	AsmFlushCacheLine (Uint8Ptr);\r
	132	AsmFlushCacheLine (&(*Uint8Ptr)[Length - 1]);\r
	133	}\r
	134	return Address;\r
	135	}\r
	136	\r
	137	/**\r
	138	Writes Back the entire data cache in cache coherency domain of the calling\r
	139	CPU.\r
	140	\r
	141	Writes Back the entire data cache in cache coherency domain of the calling\r
	142	CPU. This function guarantees that all dirty cache lines are written back to\r
	143	system memory. This function may also invalidate all the data cache lines in\r
	144	the cache coherency domain of the calling CPU.\r
	145	\r
	146	**/\r
	147	VOID\r
	148	EFIAPI\r
	149	WriteBackDataCache (\r
	150	VOID\r
	151	)\r
	152	{\r
	153	WriteBackInvalidateDataCache ();\r
	154	}\r
	155	\r
	156	/**\r
	157	Writes Back a range of data cache lines in the cache coherency domain of the\r
	158	calling CPU.\r
	159	\r
	160	Writes Back the data cache lines specified by Address and Length. If Address\r
	161	is not aligned on a cache line boundary, then entire data cache line\r
	162	containing Address is written back. If Address + Length is not aligned on a\r
	163	cache line boundary, then the entire data cache line containing Address +\r
	164	Length -1 is written back. This function may choose to write back the entire\r
	165	data cache if that is more efficient than writing back the specified range.\r
	166	If Length is 0, the no data cache lines are written back. This function may\r
	167	also invalidate all the data cache lines in the specified range of the cache\r
	168	coherency domain of the calling CPU. Address is returned.\r
	169	\r
	170	If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
	171	\r
	172	@param Address The base address of the data cache lines to write back. If\r
	173	the CPU is in a physical addressing mode, then Address is a\r
	174	physical address. If the CPU is in a virtual addressing\r
	175	mode, then Address is a virtual address.\r
	176	@param Length The number of bytes to write back from the data cache.\r
	177	\r
	178	@return Address\r
	179	\r
	180	**/\r
	181	VOID *\r
	182	EFIAPI\r
	183	WriteBackDataCacheRange (\r
	184	IN VOID *Address,\r
	185	IN UINTN Length\r
	186	)\r
	187	{\r
	188	return WriteBackInvalidateDataCacheRange (Address, Length);\r
	189	}\r
	190	\r
	191	/**\r
	192	Invalidates the entire data cache in cache coherency domain of the calling\r
	193	CPU.\r
	194	\r
	195	Invalidates the entire data cache in cache coherency domain of the calling\r
	196	CPU. This function must be used with care because dirty cache lines are not\r
	197	written back to system memory. It is typically used for cache diagnostics. If\r
	198	the CPU does not support invalidation of the entire data cache, then a write\r
	199	back and invalidate operation should be performed on the entire data cache.\r
	200	\r
	201	**/\r
	202	VOID\r
	203	EFIAPI\r
	204	InvalidateDataCache (\r
	205	VOID\r
	206	)\r
	207	{\r
	208	AsmInvd ();\r
	209	}\r
	210	\r
	211	/**\r
	212	Invalidates a range of data cache lines in the cache coherency domain of the\r
	213	calling CPU.\r
	214	\r
	215	Invalidates the data cache lines specified by Address and Length. If Address\r
	216	is not aligned on a cache line boundary, then entire data cache line\r
	217	containing Address is invalidated. If Address + Length is not aligned on a\r
	218	cache line boundary, then the entire data cache line containing Address +\r
	219	Length -1 is invalidated. This function must never invalidate any cache lines\r
	220	outside the specified range. If Length is 0, the no data cache lines are\r
	221	invalidated. Address is returned. This function must be used with care\r
	222	because dirty cache lines are not written back to system memory. It is\r
	223	typically used for cache diagnostics. If the CPU does not support\r
	224	invalidation of a data cache range, then a write back and invalidate\r
	225	operation should be performed on the data cache range.\r
	226	\r
	227	If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
	228	\r
	229	@param Address The base address of the data cache lines to invalidate. If\r
	230	the CPU is in a physical addressing mode, then Address is a\r
	231	physical address. If the CPU is in a virtual addressing mode,\r
	232	then Address is a virtual address.\r
	233	@param Length The number of bytes to invalidate from the data cache.\r
	234	\r
	235	@return Address\r
	236	\r
	237	**/\r
	238	VOID *\r
	239	EFIAPI\r
	240	InvalidateDataCacheRange (\r
	241	IN VOID *Address,\r
	242	IN UINTN Length\r
	243	)\r
	244	{\r
	245	return WriteBackInvalidateDataCacheRange (Address, Length);\r
	246	}\r