[mirror_edk2.git] / MdePkg / Library / BaseLib / Arm / CpuBreakpoint.asm

;------------------------------------------------------------------------------\r
;\r
; CpuBreakpoint() for ARM\r
;\r
; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution.  The full text of the license may be found at\r
; http://opensource.org/licenses/bsd-license.php.\r
;\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
;------------------------------------------------------------------------------\r
\r
    EXPORT CpuBreakpoint\r
\r
; Force ARM mode for this section, as MSFT assembler defaults to THUMB\r
  AREA Cpu_Breakpoint, CODE, READONLY, ARM\r
\r
  ARM\r
\r
;/**\r
;  Generates a breakpoint on the CPU.\r
;\r
;  Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
;  that code can resume normal execution after the breakpoint.\r
;\r
;**/\r
;VOID\r
;EFIAPI\r
;CpuBreakpoint (\r
;  VOID\r
;  );\r
;\r
CpuBreakpoint\r
    swi   0xdbdbdb\r
    bx    lr\r
\r
  END\r
Commit	Line	Data
	1	;------------------------------------------------------------------------------\r
	2	;\r
	3	; CpuBreakpoint() for ARM\r
	4	;\r
	5	; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
	6	; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
	7	; This program and the accompanying materials\r
	8	; are licensed and made available under the terms and conditions of the BSD License\r
	9	; which accompanies this distribution. The full text of the license may be found at\r
	10	; http://opensource.org/licenses/bsd-license.php.\r
	11	;\r
	12	; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	;\r
	15	;------------------------------------------------------------------------------\r
	16	\r
	17	EXPORT CpuBreakpoint\r
	18	\r
	19	; Force ARM mode for this section, as MSFT assembler defaults to THUMB\r
	20	AREA Cpu_Breakpoint, CODE, READONLY, ARM\r
	21	\r
	22	ARM\r
	23	\r
	24	;/**\r
	25	; Generates a breakpoint on the CPU.\r
	26	;\r
	27	; Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
	28	; that code can resume normal execution after the breakpoint.\r
	29	;\r
	30	;**/\r
	31	;VOID\r
	32	;EFIAPI\r
	33	;CpuBreakpoint (\r
	34	; VOID\r
	35	; );\r
	36	;\r
	37	CpuBreakpoint\r
	38	swi 0xdbdbdb\r
	39	bx lr\r
	40	\r
	41	END\r