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1 | /** @file | |
2 | ||
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> | |
4 | ||
5 | This program and the accompanying materials | |
6 | are licensed and made available under the terms and conditions of the BSD License | |
7 | which accompanies this distribution. The full text of the license may be found at | |
8 | http://opensource.org/licenses/bsd-license.php | |
9 | ||
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | ||
13 | **/ | |
14 | ||
15 | #ifndef __OMAP3530GPMC_H__ | |
16 | #define __OMAP3530GPMC_H__ | |
17 | ||
18 | #define GPMC_BASE (0x6E000000) | |
19 | ||
20 | //GPMC NAND definitions. | |
21 | #define GPMC_SYSCONFIG (GPMC_BASE + 0x10) | |
22 | #define SMARTIDLEMODE (0x2UL << 3) | |
23 | ||
24 | #define GPMC_SYSSTATUS (GPMC_BASE + 0x14) | |
25 | #define GPMC_IRQSTATUS (GPMC_BASE + 0x18) | |
26 | #define GPMC_IRQENABLE (GPMC_BASE + 0x1C) | |
27 | ||
28 | #define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40) | |
29 | #define TIMEOUTENABLE BIT0 | |
30 | #define TIMEOUTDISABLE (0x0UL << 0) | |
31 | ||
32 | #define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44) | |
33 | #define GPMC_ERR_TYPE (GPMC_BASE + 0x48) | |
34 | ||
35 | #define GPMC_CONFIG (GPMC_BASE + 0x50) | |
36 | #define WRITEPROTECT_HIGH BIT4 | |
37 | #define WRITEPROTECT_LOW (0x0UL << 4) | |
38 | ||
39 | #define GPMC_STATUS (GPMC_BASE + 0x54) | |
40 | ||
41 | #define GPMC_CONFIG1_0 (GPMC_BASE + 0x60) | |
42 | #define DEVICETYPE_NOR (0x0UL << 10) | |
43 | #define DEVICETYPE_NAND (0x2UL << 10) | |
44 | #define DEVICESIZE_X8 (0x0UL << 12) | |
45 | #define DEVICESIZE_X16 BIT12 | |
46 | ||
47 | #define GPMC_CONFIG2_0 (GPMC_BASE + 0x64) | |
48 | #define CSONTIME (0x0UL << 0) | |
49 | #define CSRDOFFTIME (0x14UL << 8) | |
50 | #define CSWROFFTIME (0x14UL << 16) | |
51 | ||
52 | #define GPMC_CONFIG3_0 (GPMC_BASE + 0x68) | |
53 | #define ADVRDOFFTIME (0x14UL << 8) | |
54 | #define ADVWROFFTIME (0x14UL << 16) | |
55 | ||
56 | #define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C) | |
57 | #define OEONTIME BIT0 | |
58 | #define OEOFFTIME (0xFUL << 8) | |
59 | #define WEONTIME BIT16 | |
60 | #define WEOFFTIME (0xFUL << 24) | |
61 | ||
62 | #define GPMC_CONFIG5_0 (GPMC_BASE + 0x70) | |
63 | #define RDCYCLETIME (0x14UL << 0) | |
64 | #define WRCYCLETIME (0x14UL << 8) | |
65 | #define RDACCESSTIME (0xCUL << 16) | |
66 | #define PAGEBURSTACCESSTIME BIT24 | |
67 | ||
68 | #define GPMC_CONFIG6_0 (GPMC_BASE + 0x74) | |
69 | #define CYCLE2CYCLESAMECSEN BIT7 | |
70 | #define CYCLE2CYCLEDELAY (0xAUL << 8) | |
71 | #define WRDATAONADMUXBUS (0xFUL << 16) | |
72 | #define WRACCESSTIME BIT24 | |
73 | ||
74 | #define GPMC_CONFIG7_0 (GPMC_BASE + 0x78) | |
75 | #define BASEADDRESS (0x30UL << 0) | |
76 | #define CSVALID BIT6 | |
77 | #define MASKADDRESS_128MB (0x8UL << 8) | |
78 | ||
79 | #define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C) | |
80 | #define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80) | |
81 | #define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84) | |
82 | ||
83 | #define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4) | |
84 | #define ECCENABLE BIT0 | |
85 | #define ECCDISABLE (0x0UL << 0) | |
86 | #define ECCCS_0 (0x0UL << 1) | |
87 | #define ECC16B BIT7 | |
88 | ||
89 | #define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8) | |
90 | #define ECCPOINTER_REG1 BIT0 | |
91 | #define ECCCLEAR BIT8 | |
92 | ||
93 | #define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC) | |
94 | #define ECCSIZE0_512BYTES (0xFFUL << 12) | |
95 | #define ECCSIZE1_512BYTES (0xFFUL << 22) | |
96 | ||
97 | #define GPMC_ECC1_RESULT (GPMC_BASE + 0x200) | |
98 | #define GPMC_ECC2_RESULT (GPMC_BASE + 0x204) | |
99 | #define GPMC_ECC3_RESULT (GPMC_BASE + 0x208) | |
100 | #define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C) | |
101 | #define GPMC_ECC5_RESULT (GPMC_BASE + 0x210) | |
102 | #define GPMC_ECC6_RESULT (GPMC_BASE + 0x214) | |
103 | #define GPMC_ECC7_RESULT (GPMC_BASE + 0x218) | |
104 | #define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C) | |
105 | #define GPMC_ECC9_RESULT (GPMC_BASE + 0x220) | |
106 | ||
107 | #endif //__OMAP3530GPMC_H__ |