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1/** @file\r
2 The CPU specific programming for PiSmmCpuDxeSmm module.\r
3\r
4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
5\r
6 This program and the accompanying materials are licensed and made available\r
7 under the terms and conditions of the BSD License which accompanies this\r
8 distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
12 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13**/\r
14\r
15#include <Library/BaseLib.h>\r
16#include <Library/BaseMemoryLib.h>\r
17#include <Library/DebugLib.h>\r
18#include <Library/MemEncryptSevLib.h>\r
19#include <Library/SmmCpuFeaturesLib.h>\r
20#include <Library/SmmServicesTableLib.h>\r
21#include <Library/UefiBootServicesTableLib.h>\r
22#include <PiSmm.h>\r
23#include <Register/QemuSmramSaveStateMap.h>\r
24\r
25//\r
26// EFER register LMA bit\r
27//\r
28#define LMA BIT10\r
29\r
30/**\r
31 The constructor function\r
32\r
33 @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
34 @param[in] SystemTable A pointer to the EFI System Table.\r
35\r
36 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
37\r
38**/\r
39EFI_STATUS\r
40EFIAPI\r
41SmmCpuFeaturesLibConstructor (\r
42 IN EFI_HANDLE ImageHandle,\r
43 IN EFI_SYSTEM_TABLE *SystemTable\r
44 )\r
45{\r
46 //\r
47 // No need to program SMRRs on our virtual platform.\r
48 //\r
49 return EFI_SUCCESS;\r
50}\r
51\r
52/**\r
53 Called during the very first SMI into System Management Mode to initialize\r
54 CPU features, including SMBASE, for the currently executing CPU. Since this\r
55 is the first SMI, the SMRAM Save State Map is at the default address of\r
56 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r
57 CPU is specified by CpuIndex and CpuIndex can be used to access information\r
58 about the currently executing CPU in the ProcessorInfo array and the\r
59 HotPlugCpuData data structure.\r
60\r
61 @param[in] CpuIndex The index of the CPU to initialize. The value\r
62 must be between 0 and the NumberOfCpus field in\r
63 the System Management System Table (SMST).\r
64 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r
65 was elected as monarch during System Management\r
66 Mode initialization.\r
67 FALSE if the CpuIndex is not the index of the CPU\r
68 that was elected as monarch during System\r
69 Management Mode initialization.\r
70 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r
71 structures. ProcessorInfo[CpuIndex] contains the\r
72 information for the currently executing CPU.\r
73 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r
74 contains the ApidId and SmBase arrays.\r
75**/\r
76VOID\r
77EFIAPI\r
78SmmCpuFeaturesInitializeProcessor (\r
79 IN UINTN CpuIndex,\r
80 IN BOOLEAN IsMonarch,\r
81 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r
82 IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r
83 )\r
84{\r
85 QEMU_SMRAM_SAVE_STATE_MAP *CpuState;\r
86\r
87 //\r
88 // Configure SMBASE.\r
89 //\r
90 CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(\r
91 SMM_DEFAULT_SMBASE +\r
92 SMRAM_SAVE_STATE_MAP_OFFSET\r
93 );\r
94 if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {\r
95 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
96 } else {\r
97 CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
98 }\r
99\r
100 //\r
101 // No need to program SMRRs on our virtual platform.\r
102 //\r
103}\r
104\r
105/**\r
106 This function updates the SMRAM save state on the currently executing CPU\r
107 to resume execution at a specific address after an RSM instruction. This\r
108 function must evaluate the SMRAM save state to determine the execution mode\r
109 the RSM instruction resumes and update the resume execution address with\r
110 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r
111 flag in the SMRAM save state must always be cleared. This function returns\r
112 the value of the instruction pointer from the SMRAM save state that was\r
113 replaced. If this function returns 0, then the SMRAM save state was not\r
114 modified.\r
115\r
116 This function is called during the very first SMI on each CPU after\r
117 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
118 to signal that the SMBASE of each CPU has been updated before the default\r
119 SMBASE address is used for the first SMI to the next CPU.\r
120\r
121 @param[in] CpuIndex The index of the CPU to hook. The value\r
122 must be between 0 and the NumberOfCpus\r
123 field in the System Management System\r
124 Table (SMST).\r
125 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
126 currently executing CPU.\r
127 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
128 32-bit execution mode from 64-bit SMM.\r
129 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
130 same execution mode as SMM.\r
131\r
132 @retval 0 This function did modify the SMRAM save state.\r
133 @retval > 0 The original instruction pointer value from the SMRAM save state\r
134 before it was replaced.\r
135**/\r
136UINT64\r
137EFIAPI\r
138SmmCpuFeaturesHookReturnFromSmm (\r
139 IN UINTN CpuIndex,\r
140 IN SMRAM_SAVE_STATE_MAP *CpuState,\r
141 IN UINT64 NewInstructionPointer32,\r
142 IN UINT64 NewInstructionPointer\r
143 )\r
144{\r
145 UINT64 OriginalInstructionPointer;\r
146 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
147\r
148 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;\r
149 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
150 OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;\r
151 CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;\r
152 //\r
153 // Clear the auto HALT restart flag so the RSM instruction returns\r
154 // program control to the instruction following the HLT instruction.\r
155 //\r
156 if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {\r
157 CpuSaveState->x86.AutoHALTRestart &= ~BIT0;\r
158 }\r
159 } else {\r
160 OriginalInstructionPointer = CpuSaveState->x64._RIP;\r
161 if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {\r
162 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;\r
163 } else {\r
164 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;\r
165 }\r
166 //\r
167 // Clear the auto HALT restart flag so the RSM instruction returns\r
168 // program control to the instruction following the HLT instruction.\r
169 //\r
170 if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {\r
171 CpuSaveState->x64.AutoHALTRestart &= ~BIT0;\r
172 }\r
173 }\r
174 return OriginalInstructionPointer;\r
175}\r
176\r
177/**\r
178 Hook point in normal execution mode that allows the one CPU that was elected\r
179 as monarch during System Management Mode initialization to perform additional\r
180 initialization actions immediately after all of the CPUs have processed their\r
181 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
182 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
183**/\r
184VOID\r
185EFIAPI\r
186SmmCpuFeaturesSmmRelocationComplete (\r
187 VOID\r
188 )\r
189{\r
190 EFI_STATUS Status;\r
191 UINTN MapPagesBase;\r
192 UINTN MapPagesCount;\r
193\r
194 if (!MemEncryptSevIsEnabled ()) {\r
195 return;\r
196 }\r
197\r
198 //\r
199 // Now that SMBASE relocation is complete, re-encrypt the original SMRAM save\r
200 // state map's container pages, and release the pages to DXE. (The pages were\r
201 // allocated in PlatformPei.)\r
202 //\r
203 Status = MemEncryptSevLocateInitialSmramSaveStateMapPages (\r
204 &MapPagesBase,\r
205 &MapPagesCount\r
206 );\r
207 ASSERT_EFI_ERROR (Status);\r
208\r
209 Status = MemEncryptSevSetPageEncMask (\r
210 0, // Cr3BaseAddress -- use current CR3\r
211 MapPagesBase, // BaseAddress\r
212 MapPagesCount, // NumPages\r
213 TRUE // Flush\r
214 );\r
215 if (EFI_ERROR (Status)) {\r
216 DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevSetPageEncMask(): %r\n",\r
217 __FUNCTION__, Status));\r
218 ASSERT (FALSE);\r
219 CpuDeadLoop ();\r
220 }\r
221\r
222 ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount));\r
223\r
224 Status = gBS->FreePages (MapPagesBase, MapPagesCount);\r
225 ASSERT_EFI_ERROR (Status);\r
226}\r
227\r
228/**\r
229 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r
230 returned, then a custom SMI handler is not provided by this library,\r
231 and the default SMI handler must be used.\r
232\r
233 @retval 0 Use the default SMI handler.\r
234 @retval > 0 Use the SMI handler installed by\r
235 SmmCpuFeaturesInstallSmiHandler(). The caller is required to\r
236 allocate enough SMRAM for each CPU to support the size of the\r
237 custom SMI handler.\r
238**/\r
239UINTN\r
240EFIAPI\r
241SmmCpuFeaturesGetSmiHandlerSize (\r
242 VOID\r
243 )\r
244{\r
245 return 0;\r
246}\r
247\r
248/**\r
249 Install a custom SMI handler for the CPU specified by CpuIndex. This\r
250 function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size\r
251 is greater than zero and is called by the CPU that was elected as monarch\r
252 during System Management Mode initialization.\r
253\r
254 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
255 The value must be between 0 and the NumberOfCpus field\r
256 in the System Management System Table (SMST).\r
257 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
258 @param[in] SmiStack The stack to use when an SMI is processed by the\r
259 the CPU specified by CpuIndex.\r
260 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
261 processed by the CPU specified by CpuIndex.\r
262 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
263 processed by the CPU specified by CpuIndex.\r
264 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
265 processed by the CPU specified by CpuIndex.\r
266 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
267 processed by the CPU specified by CpuIndex.\r
268 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
269 processed by the CPU specified by CpuIndex.\r
270 @param[in] Cr3 The base address of the page tables to use when an SMI\r
271 is processed by the CPU specified by CpuIndex.\r
272**/\r
273VOID\r
274EFIAPI\r
275SmmCpuFeaturesInstallSmiHandler (\r
276 IN UINTN CpuIndex,\r
277 IN UINT32 SmBase,\r
278 IN VOID *SmiStack,\r
279 IN UINTN StackSize,\r
280 IN UINTN GdtBase,\r
281 IN UINTN GdtSize,\r
282 IN UINTN IdtBase,\r
283 IN UINTN IdtSize,\r
284 IN UINT32 Cr3\r
285 )\r
286{\r
287}\r
288\r
289/**\r
290 Determines if MTRR registers must be configured to set SMRAM cache-ability\r
291 when executing in System Management Mode.\r
292\r
293 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r
294 @retval FALSE MTRR registers do not need to be configured to set SMRAM\r
295 cache-ability.\r
296**/\r
297BOOLEAN\r
298EFIAPI\r
299SmmCpuFeaturesNeedConfigureMtrrs (\r
300 VOID\r
301 )\r
302{\r
303 return FALSE;\r
304}\r
305\r
306/**\r
307 Disable SMRR register if SMRR is supported and\r
308 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r
309**/\r
310VOID\r
311EFIAPI\r
312SmmCpuFeaturesDisableSmrr (\r
313 VOID\r
314 )\r
315{\r
316 //\r
317 // No SMRR support, nothing to do\r
318 //\r
319}\r
320\r
321/**\r
322 Enable SMRR register if SMRR is supported and\r
323 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r
324**/\r
325VOID\r
326EFIAPI\r
327SmmCpuFeaturesReenableSmrr (\r
328 VOID\r
329 )\r
330{\r
331 //\r
332 // No SMRR support, nothing to do\r
333 //\r
334}\r
335\r
336/**\r
337 Processor specific hook point each time a CPU enters System Management Mode.\r
338\r
339 @param[in] CpuIndex The index of the CPU that has entered SMM. The value\r
340 must be between 0 and the NumberOfCpus field in the\r
341 System Management System Table (SMST).\r
342**/\r
343VOID\r
344EFIAPI\r
345SmmCpuFeaturesRendezvousEntry (\r
346 IN UINTN CpuIndex\r
347 )\r
348{\r
349 //\r
350 // No SMRR support, nothing to do\r
351 //\r
352}\r
353\r
354/**\r
355 Processor specific hook point each time a CPU exits System Management Mode.\r
356\r
357 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value\r
358 must be between 0 and the NumberOfCpus field in the\r
359 System Management System Table (SMST).\r
360**/\r
361VOID\r
362EFIAPI\r
363SmmCpuFeaturesRendezvousExit (\r
364 IN UINTN CpuIndex\r
365 )\r
366{\r
367}\r
368\r
369/**\r
370 Check to see if an SMM register is supported by a specified CPU.\r
371\r
372 @param[in] CpuIndex The index of the CPU to check for SMM register support.\r
373 The value must be between 0 and the NumberOfCpus field\r
374 in the System Management System Table (SMST).\r
375 @param[in] RegName Identifies the SMM register to check for support.\r
376\r
377 @retval TRUE The SMM register specified by RegName is supported by the CPU\r
378 specified by CpuIndex.\r
379 @retval FALSE The SMM register specified by RegName is not supported by the\r
380 CPU specified by CpuIndex.\r
381**/\r
382BOOLEAN\r
383EFIAPI\r
384SmmCpuFeaturesIsSmmRegisterSupported (\r
385 IN UINTN CpuIndex,\r
386 IN SMM_REG_NAME RegName\r
387 )\r
388{\r
389 ASSERT (RegName == SmmRegFeatureControl);\r
390 return FALSE;\r
391}\r
392\r
393/**\r
394 Returns the current value of the SMM register for the specified CPU.\r
395 If the SMM register is not supported, then 0 is returned.\r
396\r
397 @param[in] CpuIndex The index of the CPU to read the SMM register. The\r
398 value must be between 0 and the NumberOfCpus field in\r
399 the System Management System Table (SMST).\r
400 @param[in] RegName Identifies the SMM register to read.\r
401\r
402 @return The value of the SMM register specified by RegName from the CPU\r
403 specified by CpuIndex.\r
404**/\r
405UINT64\r
406EFIAPI\r
407SmmCpuFeaturesGetSmmRegister (\r
408 IN UINTN CpuIndex,\r
409 IN SMM_REG_NAME RegName\r
410 )\r
411{\r
412 //\r
413 // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.\r
414 // The last of these should actually be SmmRegSmmDisable, so we can just\r
415 // return FALSE.\r
416 //\r
417 return 0;\r
418}\r
419\r
420/**\r
421 Sets the value of an SMM register on a specified CPU.\r
422 If the SMM register is not supported, then no action is performed.\r
423\r
424 @param[in] CpuIndex The index of the CPU to write the SMM register. The\r
425 value must be between 0 and the NumberOfCpus field in\r
426 the System Management System Table (SMST).\r
427 @param[in] RegName Identifies the SMM register to write.\r
428 registers are read-only.\r
429 @param[in] Value The value to write to the SMM register.\r
430**/\r
431VOID\r
432EFIAPI\r
433SmmCpuFeaturesSetSmmRegister (\r
434 IN UINTN CpuIndex,\r
435 IN SMM_REG_NAME RegName,\r
436 IN UINT64 Value\r
437 )\r
438{\r
439 ASSERT (FALSE);\r
440}\r
441\r
442///\r
443/// Macro used to simplify the lookup table entries of type\r
444/// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
445///\r
446#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)\r
447\r
448///\r
449/// Macro used to simplify the lookup table entries of type\r
450/// CPU_SMM_SAVE_STATE_REGISTER_RANGE\r
451///\r
452#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r
453\r
454///\r
455/// Structure used to describe a range of registers\r
456///\r
457typedef struct {\r
458 EFI_SMM_SAVE_STATE_REGISTER Start;\r
459 EFI_SMM_SAVE_STATE_REGISTER End;\r
460 UINTN Length;\r
461} CPU_SMM_SAVE_STATE_REGISTER_RANGE;\r
462\r
463///\r
464/// Structure used to build a lookup table to retrieve the widths and offsets\r
465/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value\r
466///\r
467\r
468#define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1\r
469\r
470typedef struct {\r
471 UINT8 Width32;\r
472 UINT8 Width64;\r
473 UINT16 Offset32;\r
474 UINT16 Offset64Lo;\r
475 UINT16 Offset64Hi;\r
476 BOOLEAN Writeable;\r
477} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;\r
478\r
479///\r
480/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER\r
481/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
482///\r
483STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r
484 SMM_REGISTER_RANGE (\r
485 EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,\r
486 EFI_SMM_SAVE_STATE_REGISTER_LDTINFO\r
487 ),\r
488 SMM_REGISTER_RANGE (\r
489 EFI_SMM_SAVE_STATE_REGISTER_ES,\r
490 EFI_SMM_SAVE_STATE_REGISTER_RIP\r
491 ),\r
492 SMM_REGISTER_RANGE (\r
493 EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,\r
494 EFI_SMM_SAVE_STATE_REGISTER_CR4\r
495 ),\r
496 { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }\r
497};\r
498\r
499///\r
500/// Lookup table used to retrieve the widths and offsets associated with each\r
501/// supported EFI_SMM_SAVE_STATE_REGISTER value\r
502///\r
503STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r
504 {\r
505 0, // Width32\r
506 0, // Width64\r
507 0, // Offset32\r
508 0, // Offset64Lo\r
509 0, // Offset64Hi\r
510 FALSE // Writeable\r
511 }, // Reserved\r
512\r
513 //\r
514 // CPU Save State registers defined in PI SMM CPU Protocol.\r
515 //\r
516 {\r
517 0, // Width32\r
518 8, // Width64\r
519 0, // Offset32\r
520 SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo\r
521 SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi\r
522 FALSE // Writeable\r
523 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4\r
524\r
525 {\r
526 0, // Width32\r
527 8, // Width64\r
528 0, // Offset32\r
529 SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo\r
530 SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi\r
531 FALSE // Writeable\r
532 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5\r
533\r
534 {\r
535 0, // Width32\r
536 8, // Width64\r
537 0, // Offset32\r
538 SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo\r
539 SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi\r
540 FALSE // Writeable\r
541 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6\r
542\r
543 {\r
544 0, // Width32\r
545 0, // Width64\r
546 0, // Offset32\r
547 SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo\r
548 SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi\r
549 FALSE // Writeable\r
550 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
551\r
552 {\r
553 0, // Width32\r
554 0, // Width64\r
555 0, // Offset32\r
556 SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo\r
557 SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi\r
558 FALSE // Writeable\r
559 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
560\r
561 {\r
562 0, // Width32\r
563 0, // Width64\r
564 0, // Offset32\r
565 SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo\r
566 SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi\r
567 FALSE // Writeable\r
568 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
569\r
570 {\r
571 0, // Width32\r
572 0, // Width64\r
573 0, // Offset32\r
574 0, // Offset64Lo\r
575 0 + 4, // Offset64Hi\r
576 FALSE // Writeable\r
577 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10\r
578\r
579 {\r
580 4, // Width32\r
581 4, // Width64\r
582 SMM_CPU_OFFSET (x86._ES), // Offset32\r
583 SMM_CPU_OFFSET (x64._ES), // Offset64Lo\r
584 0, // Offset64Hi\r
585 FALSE // Writeable\r
586 }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20\r
587\r
588 {\r
589 4, // Width32\r
590 4, // Width64\r
591 SMM_CPU_OFFSET (x86._CS), // Offset32\r
592 SMM_CPU_OFFSET (x64._CS), // Offset64Lo\r
593 0, // Offset64Hi\r
594 FALSE // Writeable\r
595 }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21\r
596\r
597 {\r
598 4, // Width32\r
599 4, // Width64\r
600 SMM_CPU_OFFSET (x86._SS), // Offset32\r
601 SMM_CPU_OFFSET (x64._SS), // Offset64Lo\r
602 0, // Offset64Hi\r
603 FALSE // Writeable\r
604 }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22\r
605\r
606 {\r
607 4, // Width32\r
608 4, // Width64\r
609 SMM_CPU_OFFSET (x86._DS), // Offset32\r
610 SMM_CPU_OFFSET (x64._DS), // Offset64Lo\r
611 0, // Offset64Hi\r
612 FALSE // Writeable\r
613 }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23\r
614\r
615 {\r
616 4, // Width32\r
617 4, // Width64\r
618 SMM_CPU_OFFSET (x86._FS), // Offset32\r
619 SMM_CPU_OFFSET (x64._FS), // Offset64Lo\r
620 0, // Offset64Hi\r
621 FALSE // Writeable\r
622 }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24\r
623\r
624 {\r
625 4, // Width32\r
626 4, // Width64\r
627 SMM_CPU_OFFSET (x86._GS), // Offset32\r
628 SMM_CPU_OFFSET (x64._GS), // Offset64Lo\r
629 0, // Offset64Hi\r
630 FALSE // Writeable\r
631 }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25\r
632\r
633 {\r
634 0, // Width32\r
635 4, // Width64\r
636 0, // Offset32\r
637 SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo\r
638 0, // Offset64Hi\r
639 FALSE // Writeable\r
640 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r
641\r
642 {\r
643 4, // Width32\r
644 4, // Width64\r
645 SMM_CPU_OFFSET (x86._TR), // Offset32\r
646 SMM_CPU_OFFSET (x64._TR), // Offset64Lo\r
647 0, // Offset64Hi\r
648 FALSE // Writeable\r
649 }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27\r
650\r
651 {\r
652 4, // Width32\r
653 8, // Width64\r
654 SMM_CPU_OFFSET (x86._DR7), // Offset32\r
655 SMM_CPU_OFFSET (x64._DR7), // Offset64Lo\r
656 SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi\r
657 FALSE // Writeable\r
658 }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28\r
659\r
660 {\r
661 4, // Width32\r
662 8, // Width64\r
663 SMM_CPU_OFFSET (x86._DR6), // Offset32\r
664 SMM_CPU_OFFSET (x64._DR6), // Offset64Lo\r
665 SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi\r
666 FALSE // Writeable\r
667 }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29\r
668\r
669 {\r
670 0, // Width32\r
671 8, // Width64\r
672 0, // Offset32\r
673 SMM_CPU_OFFSET (x64._R8), // Offset64Lo\r
674 SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi\r
675 TRUE // Writeable\r
676 }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30\r
677\r
678 {\r
679 0, // Width32\r
680 8, // Width64\r
681 0, // Offset32\r
682 SMM_CPU_OFFSET (x64._R9), // Offset64Lo\r
683 SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi\r
684 TRUE // Writeable\r
685 }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31\r
686\r
687 {\r
688 0, // Width32\r
689 8, // Width64\r
690 0, // Offset32\r
691 SMM_CPU_OFFSET (x64._R10), // Offset64Lo\r
692 SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi\r
693 TRUE // Writeable\r
694 }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32\r
695\r
696 {\r
697 0, // Width32\r
698 8, // Width64\r
699 0, // Offset32\r
700 SMM_CPU_OFFSET (x64._R11), // Offset64Lo\r
701 SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi\r
702 TRUE // Writeable\r
703 }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33\r
704\r
705 {\r
706 0, // Width32\r
707 8, // Width64\r
708 0, // Offset32\r
709 SMM_CPU_OFFSET (x64._R12), // Offset64Lo\r
710 SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi\r
711 TRUE // Writeable\r
712 }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34\r
713\r
714 {\r
715 0, // Width32\r
716 8, // Width64\r
717 0, // Offset32\r
718 SMM_CPU_OFFSET (x64._R13), // Offset64Lo\r
719 SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi\r
720 TRUE // Writeable\r
721 }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35\r
722\r
723 {\r
724 0, // Width32\r
725 8, // Width64\r
726 0, // Offset32\r
727 SMM_CPU_OFFSET (x64._R14), // Offset64Lo\r
728 SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi\r
729 TRUE // Writeable\r
730 }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36\r
731\r
732 {\r
733 0, // Width32\r
734 8, // Width64\r
735 0, // Offset32\r
736 SMM_CPU_OFFSET (x64._R15), // Offset64Lo\r
737 SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi\r
738 TRUE // Writeable\r
739 }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37\r
740\r
741 {\r
742 4, // Width32\r
743 8, // Width64\r
744 SMM_CPU_OFFSET (x86._EAX), // Offset32\r
745 SMM_CPU_OFFSET (x64._RAX), // Offset64Lo\r
746 SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi\r
747 TRUE // Writeable\r
748 }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38\r
749\r
750 {\r
751 4, // Width32\r
752 8, // Width64\r
753 SMM_CPU_OFFSET (x86._EBX), // Offset32\r
754 SMM_CPU_OFFSET (x64._RBX), // Offset64Lo\r
755 SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi\r
756 TRUE // Writeable\r
757 }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39\r
758\r
759 {\r
760 4, // Width32\r
761 8, // Width64\r
762 SMM_CPU_OFFSET (x86._ECX), // Offset32\r
763 SMM_CPU_OFFSET (x64._RCX), // Offset64Lo\r
764 SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi\r
765 TRUE // Writeable\r
766 }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40\r
767\r
768 {\r
769 4, // Width32\r
770 8, // Width64\r
771 SMM_CPU_OFFSET (x86._EDX), // Offset32\r
772 SMM_CPU_OFFSET (x64._RDX), // Offset64Lo\r
773 SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi\r
774 TRUE // Writeable\r
775 }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41\r
776\r
777 {\r
778 4, // Width32\r
779 8, // Width64\r
780 SMM_CPU_OFFSET (x86._ESP), // Offset32\r
781 SMM_CPU_OFFSET (x64._RSP), // Offset64Lo\r
782 SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi\r
783 TRUE // Writeable\r
784 }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42\r
785\r
786 {\r
787 4, // Width32\r
788 8, // Width64\r
789 SMM_CPU_OFFSET (x86._EBP), // Offset32\r
790 SMM_CPU_OFFSET (x64._RBP), // Offset64Lo\r
791 SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi\r
792 TRUE // Writeable\r
793 }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43\r
794\r
795 {\r
796 4, // Width32\r
797 8, // Width64\r
798 SMM_CPU_OFFSET (x86._ESI), // Offset32\r
799 SMM_CPU_OFFSET (x64._RSI), // Offset64Lo\r
800 SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi\r
801 TRUE // Writeable\r
802 }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44\r
803\r
804 {\r
805 4, // Width32\r
806 8, // Width64\r
807 SMM_CPU_OFFSET (x86._EDI), // Offset32\r
808 SMM_CPU_OFFSET (x64._RDI), // Offset64Lo\r
809 SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi\r
810 TRUE // Writeable\r
811 }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45\r
812\r
813 {\r
814 4, // Width32\r
815 8, // Width64\r
816 SMM_CPU_OFFSET (x86._EIP), // Offset32\r
817 SMM_CPU_OFFSET (x64._RIP), // Offset64Lo\r
818 SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi\r
819 TRUE // Writeable\r
820 }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46\r
821\r
822 {\r
823 4, // Width32\r
824 8, // Width64\r
825 SMM_CPU_OFFSET (x86._EFLAGS), // Offset32\r
826 SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo\r
827 SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi\r
828 TRUE // Writeable\r
829 }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51\r
830\r
831 {\r
832 4, // Width32\r
833 8, // Width64\r
834 SMM_CPU_OFFSET (x86._CR0), // Offset32\r
835 SMM_CPU_OFFSET (x64._CR0), // Offset64Lo\r
836 SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi\r
837 FALSE // Writeable\r
838 }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52\r
839\r
840 {\r
841 4, // Width32\r
842 8, // Width64\r
843 SMM_CPU_OFFSET (x86._CR3), // Offset32\r
844 SMM_CPU_OFFSET (x64._CR3), // Offset64Lo\r
845 SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi\r
846 FALSE // Writeable\r
847 }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53\r
848\r
849 {\r
850 0, // Width32\r
851 4, // Width64\r
852 0, // Offset32\r
853 SMM_CPU_OFFSET (x64._CR4), // Offset64Lo\r
854 SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi\r
855 FALSE // Writeable\r
856 }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54\r
857};\r
858\r
859//\r
860// No support for I/O restart\r
861//\r
862\r
863/**\r
864 Read information from the CPU save state.\r
865\r
866 @param Register Specifies the CPU register to read form the save state.\r
867\r
868 @retval 0 Register is not valid\r
869 @retval >0 Index into mSmmCpuWidthOffset[] associated with Register\r
870\r
871**/\r
872STATIC\r
873UINTN\r
874GetRegisterIndex (\r
875 IN EFI_SMM_SAVE_STATE_REGISTER Register\r
876 )\r
877{\r
878 UINTN Index;\r
879 UINTN Offset;\r
880\r
881 for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;\r
882 mSmmCpuRegisterRanges[Index].Length != 0;\r
883 Index++) {\r
884 if (Register >= mSmmCpuRegisterRanges[Index].Start &&\r
885 Register <= mSmmCpuRegisterRanges[Index].End) {\r
886 return Register - mSmmCpuRegisterRanges[Index].Start + Offset;\r
887 }\r
888 Offset += mSmmCpuRegisterRanges[Index].Length;\r
889 }\r
890 return 0;\r
891}\r
892\r
893/**\r
894 Read a CPU Save State register on the target processor.\r
895\r
896 This function abstracts the differences that whether the CPU Save State\r
897 register is in the IA32 CPU Save State Map or X64 CPU Save State Map.\r
898\r
899 This function supports reading a CPU Save State register in SMBase relocation\r
900 handler.\r
901\r
902 @param[in] CpuIndex Specifies the zero-based index of the CPU save\r
903 state.\r
904 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
905 @param[in] Width The number of bytes to read from the CPU save\r
906 state.\r
907 @param[out] Buffer Upon return, this holds the CPU register value\r
908 read from the save state.\r
909\r
910 @retval EFI_SUCCESS The register was read from Save State.\r
911 @retval EFI_NOT_FOUND The register is not defined for the Save State\r
912 of Processor.\r
913 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
914\r
915**/\r
916STATIC\r
917EFI_STATUS\r
918ReadSaveStateRegisterByIndex (\r
919 IN UINTN CpuIndex,\r
920 IN UINTN RegisterIndex,\r
921 IN UINTN Width,\r
922 OUT VOID *Buffer\r
923 )\r
924{\r
925 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
926\r
927 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
928\r
929 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
930 //\r
931 // If 32-bit mode width is zero, then the specified register can not be\r
932 // accessed\r
933 //\r
934 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
935 return EFI_NOT_FOUND;\r
936 }\r
937\r
938 //\r
939 // If Width is bigger than the 32-bit mode width, then the specified\r
940 // register can not be accessed\r
941 //\r
942 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
943 return EFI_INVALID_PARAMETER;\r
944 }\r
945\r
946 //\r
947 // Write return buffer\r
948 //\r
949 ASSERT(CpuSaveState != NULL);\r
950 CopyMem (\r
951 Buffer,\r
952 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r
953 Width\r
954 );\r
955 } else {\r
956 //\r
957 // If 64-bit mode width is zero, then the specified register can not be\r
958 // accessed\r
959 //\r
960 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
961 return EFI_NOT_FOUND;\r
962 }\r
963\r
964 //\r
965 // If Width is bigger than the 64-bit mode width, then the specified\r
966 // register can not be accessed\r
967 //\r
968 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
969 return EFI_INVALID_PARAMETER;\r
970 }\r
971\r
972 //\r
973 // Write lower 32-bits of return buffer\r
974 //\r
975 CopyMem (\r
976 Buffer,\r
977 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r
978 MIN (4, Width)\r
979 );\r
980 if (Width >= 4) {\r
981 //\r
982 // Write upper 32-bits of return buffer\r
983 //\r
984 CopyMem (\r
985 (UINT8 *)Buffer + 4,\r
986 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r
987 Width - 4\r
988 );\r
989 }\r
990 }\r
991 return EFI_SUCCESS;\r
992}\r
993\r
994/**\r
995 Read an SMM Save State register on the target processor. If this function\r
996 returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
997 SMM Save Sate register.\r
998\r
999 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r
1000 value must be between 0 and the NumberOfCpus field in\r
1001 the System Management System Table (SMST).\r
1002 @param[in] Register The SMM Save State register to read.\r
1003 @param[in] Width The number of bytes to read from the CPU save state.\r
1004 @param[out] Buffer Upon return, this holds the CPU register value read\r
1005 from the save state.\r
1006\r
1007 @retval EFI_SUCCESS The register was read from Save State.\r
1008 @retval EFI_INVALID_PARAMTER Buffer is NULL.\r
1009 @retval EFI_UNSUPPORTED This function does not support reading\r
1010 Register.\r
1011**/\r
1012EFI_STATUS\r
1013EFIAPI\r
1014SmmCpuFeaturesReadSaveStateRegister (\r
1015 IN UINTN CpuIndex,\r
1016 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
1017 IN UINTN Width,\r
1018 OUT VOID *Buffer\r
1019 )\r
1020{\r
1021 UINTN RegisterIndex;\r
1022 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
1023\r
1024 //\r
1025 // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA\r
1026 //\r
1027 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
1028 //\r
1029 // Only byte access is supported for this register\r
1030 //\r
1031 if (Width != 1) {\r
1032 return EFI_INVALID_PARAMETER;\r
1033 }\r
1034\r
1035 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
1036\r
1037 //\r
1038 // Check CPU mode\r
1039 //\r
1040 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
1041 *(UINT8 *)Buffer = 32;\r
1042 } else {\r
1043 *(UINT8 *)Buffer = 64;\r
1044 }\r
1045\r
1046 return EFI_SUCCESS;\r
1047 }\r
1048\r
1049 //\r
1050 // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO\r
1051 //\r
1052 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
1053 return EFI_NOT_FOUND;\r
1054 }\r
1055\r
1056 //\r
1057 // Convert Register to a register lookup table index. Let\r
1058 // PiSmmCpuDxeSmm implement other special registers (currently\r
1059 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r
1060 //\r
1061 RegisterIndex = GetRegisterIndex (Register);\r
1062 if (RegisterIndex == 0) {\r
1063 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r
1064 EFI_NOT_FOUND :\r
1065 EFI_UNSUPPORTED);\r
1066 }\r
1067\r
1068 return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);\r
1069}\r
1070\r
1071/**\r
1072 Writes an SMM Save State register on the target processor. If this function\r
1073 returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
1074 SMM Save Sate register.\r
1075\r
1076 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r
1077 value must be between 0 and the NumberOfCpus field in\r
1078 the System Management System Table (SMST).\r
1079 @param[in] Register The SMM Save State register to write.\r
1080 @param[in] Width The number of bytes to write to the CPU save state.\r
1081 @param[in] Buffer Upon entry, this holds the new CPU register value.\r
1082\r
1083 @retval EFI_SUCCESS The register was written to Save State.\r
1084 @retval EFI_INVALID_PARAMTER Buffer is NULL.\r
1085 @retval EFI_UNSUPPORTED This function does not support writing\r
1086 Register.\r
1087**/\r
1088EFI_STATUS\r
1089EFIAPI\r
1090SmmCpuFeaturesWriteSaveStateRegister (\r
1091 IN UINTN CpuIndex,\r
1092 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
1093 IN UINTN Width,\r
1094 IN CONST VOID *Buffer\r
1095 )\r
1096{\r
1097 UINTN RegisterIndex;\r
1098 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
1099\r
1100 //\r
1101 // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored\r
1102 //\r
1103 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
1104 return EFI_SUCCESS;\r
1105 }\r
1106\r
1107 //\r
1108 // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported\r
1109 //\r
1110 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
1111 return EFI_NOT_FOUND;\r
1112 }\r
1113\r
1114 //\r
1115 // Convert Register to a register lookup table index. Let\r
1116 // PiSmmCpuDxeSmm implement other special registers (currently\r
1117 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r
1118 //\r
1119 RegisterIndex = GetRegisterIndex (Register);\r
1120 if (RegisterIndex == 0) {\r
1121 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r
1122 EFI_NOT_FOUND :\r
1123 EFI_UNSUPPORTED);\r
1124 }\r
1125\r
1126 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
1127\r
1128 //\r
1129 // Do not write non-writable SaveState, because it will cause exception.\r
1130 //\r
1131 if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {\r
1132 return EFI_UNSUPPORTED;\r
1133 }\r
1134\r
1135 //\r
1136 // Check CPU mode\r
1137 //\r
1138 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
1139 //\r
1140 // If 32-bit mode width is zero, then the specified register can not be\r
1141 // accessed\r
1142 //\r
1143 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
1144 return EFI_NOT_FOUND;\r
1145 }\r
1146\r
1147 //\r
1148 // If Width is bigger than the 32-bit mode width, then the specified\r
1149 // register can not be accessed\r
1150 //\r
1151 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
1152 return EFI_INVALID_PARAMETER;\r
1153 }\r
1154 //\r
1155 // Write SMM State register\r
1156 //\r
1157 ASSERT (CpuSaveState != NULL);\r
1158 CopyMem (\r
1159 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r
1160 Buffer,\r
1161 Width\r
1162 );\r
1163 } else {\r
1164 //\r
1165 // If 64-bit mode width is zero, then the specified register can not be\r
1166 // accessed\r
1167 //\r
1168 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
1169 return EFI_NOT_FOUND;\r
1170 }\r
1171\r
1172 //\r
1173 // If Width is bigger than the 64-bit mode width, then the specified\r
1174 // register can not be accessed\r
1175 //\r
1176 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
1177 return EFI_INVALID_PARAMETER;\r
1178 }\r
1179\r
1180 //\r
1181 // Write lower 32-bits of SMM State register\r
1182 //\r
1183 CopyMem (\r
1184 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r
1185 Buffer,\r
1186 MIN (4, Width)\r
1187 );\r
1188 if (Width >= 4) {\r
1189 //\r
1190 // Write upper 32-bits of SMM State register\r
1191 //\r
1192 CopyMem (\r
1193 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r
1194 (UINT8 *)Buffer + 4,\r
1195 Width - 4\r
1196 );\r
1197 }\r
1198 }\r
1199 return EFI_SUCCESS;\r
1200}\r
1201\r
1202/**\r
1203 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
1204 notification is completely processed.\r
1205**/\r
1206VOID\r
1207EFIAPI\r
1208SmmCpuFeaturesCompleteSmmReadyToLock (\r
1209 VOID\r
1210 )\r
1211{\r
1212}\r
1213\r
1214/**\r
1215 This API provides a method for a CPU to allocate a specific region for\r
1216 storing page tables.\r
1217\r
1218 This API can be called more once to allocate memory for page tables.\r
1219\r
1220 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns\r
1221 a pointer to the allocated buffer. The buffer returned is aligned on a 4KB\r
1222 boundary. If Pages is 0, then NULL is returned. If there is not enough\r
1223 memory remaining to satisfy the request, then NULL is returned.\r
1224\r
1225 This function can also return NULL if there is no preference on where the\r
1226 page tables are allocated in SMRAM.\r
1227\r
1228 @param Pages The number of 4 KB pages to allocate.\r
1229\r
1230 @return A pointer to the allocated buffer for page tables.\r
1231 @retval NULL Fail to allocate a specific region for storing page tables,\r
1232 Or there is no preference on where the page tables are\r
1233 allocated in SMRAM.\r
1234\r
1235**/\r
1236VOID *\r
1237EFIAPI\r
1238SmmCpuFeaturesAllocatePageTableMemory (\r
1239 IN UINTN Pages\r
1240 )\r
1241{\r
1242 return NULL;\r
1243}\r
1244\r
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