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OvmfPkg/PlatformPei: don't allocate reserved mem varstore if SMM_REQUIRE
[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c
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1/**@file\r
2 Platform PEI driver\r
3\r
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
6\r
7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17//\r
18// The package level header files this module uses\r
19//\r
20#include <PiPei.h>\r
21\r
22//\r
23// The Library classes this module consumes\r
24//\r
25#include <Library/BaseLib.h>\r
26#include <Library/DebugLib.h>\r
27#include <Library/HobLib.h>\r
28#include <Library/IoLib.h>\r
29#include <Library/MemoryAllocationLib.h>\r
30#include <Library/PcdLib.h>\r
31#include <Library/PciLib.h>\r
32#include <Library/PeimEntryPoint.h>\r
33#include <Library/PeiServicesLib.h>\r
34#include <Library/QemuFwCfgLib.h>\r
35#include <Library/QemuFwCfgS3Lib.h>\r
36#include <Library/ResourcePublicationLib.h>\r
37#include <Guid/MemoryTypeInformation.h>\r
38#include <Ppi/MasterBootMode.h>\r
39#include <IndustryStandard/Pci22.h>\r
40#include <OvmfPlatforms.h>\r
41\r
42#include "Platform.h"\r
43#include "Cmos.h"\r
44\r
45EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
46 { EfiACPIMemoryNVS, 0x004 },\r
47 { EfiACPIReclaimMemory, 0x008 },\r
48 { EfiReservedMemoryType, 0x004 },\r
49 { EfiRuntimeServicesData, 0x024 },\r
50 { EfiRuntimeServicesCode, 0x030 },\r
51 { EfiBootServicesCode, 0x180 },\r
52 { EfiBootServicesData, 0xF00 },\r
53 { EfiMaxMemoryType, 0x000 }\r
54};\r
55\r
56\r
57EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
58 {\r
59 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
60 &gEfiPeiMasterBootModePpiGuid,\r
61 NULL\r
62 }\r
63};\r
64\r
65\r
66UINT16 mHostBridgeDevId;\r
67\r
68EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
69\r
70BOOLEAN mS3Supported = FALSE;\r
71\r
72UINT32 mMaxCpuCount;\r
73\r
74VOID\r
75AddIoMemoryBaseSizeHob (\r
76 EFI_PHYSICAL_ADDRESS MemoryBase,\r
77 UINT64 MemorySize\r
78 )\r
79{\r
80 BuildResourceDescriptorHob (\r
81 EFI_RESOURCE_MEMORY_MAPPED_IO,\r
82 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
83 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
84 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
85 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
86 MemoryBase,\r
87 MemorySize\r
88 );\r
89}\r
90\r
91VOID\r
92AddReservedMemoryBaseSizeHob (\r
93 EFI_PHYSICAL_ADDRESS MemoryBase,\r
94 UINT64 MemorySize,\r
95 BOOLEAN Cacheable\r
96 )\r
97{\r
98 BuildResourceDescriptorHob (\r
99 EFI_RESOURCE_MEMORY_RESERVED,\r
100 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
101 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
102 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
103 (Cacheable ?\r
104 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
105 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
106 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
107 0\r
108 ) |\r
109 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
110 MemoryBase,\r
111 MemorySize\r
112 );\r
113}\r
114\r
115VOID\r
116AddIoMemoryRangeHob (\r
117 EFI_PHYSICAL_ADDRESS MemoryBase,\r
118 EFI_PHYSICAL_ADDRESS MemoryLimit\r
119 )\r
120{\r
121 AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
122}\r
123\r
124\r
125VOID\r
126AddMemoryBaseSizeHob (\r
127 EFI_PHYSICAL_ADDRESS MemoryBase,\r
128 UINT64 MemorySize\r
129 )\r
130{\r
131 BuildResourceDescriptorHob (\r
132 EFI_RESOURCE_SYSTEM_MEMORY,\r
133 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
134 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
135 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
136 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
137 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
138 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
139 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
140 MemoryBase,\r
141 MemorySize\r
142 );\r
143}\r
144\r
145\r
146VOID\r
147AddMemoryRangeHob (\r
148 EFI_PHYSICAL_ADDRESS MemoryBase,\r
149 EFI_PHYSICAL_ADDRESS MemoryLimit\r
150 )\r
151{\r
152 AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
153}\r
154\r
155\r
156VOID\r
157MemMapInitialization (\r
158 VOID\r
159 )\r
160{\r
161 UINT64 PciIoBase;\r
162 UINT64 PciIoSize;\r
163 RETURN_STATUS PcdStatus;\r
164\r
165 PciIoBase = 0xC000;\r
166 PciIoSize = 0x4000;\r
167\r
168 //\r
169 // Create Memory Type Information HOB\r
170 //\r
171 BuildGuidDataHob (\r
172 &gEfiMemoryTypeInformationGuid,\r
173 mDefaultMemoryTypeInformation,\r
174 sizeof(mDefaultMemoryTypeInformation)\r
175 );\r
176\r
177 //\r
178 // Video memory + Legacy BIOS region\r
179 //\r
180 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
181\r
182 if (!mXen) {\r
183 UINT32 TopOfLowRam;\r
184 UINT64 PciExBarBase;\r
185 UINT32 PciBase;\r
186 UINT32 PciSize;\r
187\r
188 TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
189 PciExBarBase = 0;\r
190 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
191 //\r
192 // The MMCONFIG area is expected to fall between the top of low RAM and\r
193 // the base of the 32-bit PCI host aperture.\r
194 //\r
195 PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
196 ASSERT (TopOfLowRam <= PciExBarBase);\r
197 ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
198 PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
199 } else {\r
200 PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
201 }\r
202\r
203 //\r
204 // address purpose size\r
205 // ------------ -------- -------------------------\r
206 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
207 // 0xFC000000 gap 44 MB\r
208 // 0xFEC00000 IO-APIC 4 KB\r
209 // 0xFEC01000 gap 1020 KB\r
210 // 0xFED00000 HPET 1 KB\r
211 // 0xFED00400 gap 111 KB\r
212 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
213 // 0xFED20000 gap 896 KB\r
214 // 0xFEE00000 LAPIC 1 MB\r
215 //\r
216 PciSize = 0xFC000000 - PciBase;\r
217 AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
218 PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
219 ASSERT_RETURN_ERROR (PcdStatus);\r
220 PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r
221 ASSERT_RETURN_ERROR (PcdStatus);\r
222\r
223 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
224 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
225 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
226 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
227 //\r
228 // Note: there should be an\r
229 //\r
230 // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
231 //\r
232 // call below, just like the one above for RCBA. However, Linux insists\r
233 // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r
234 // "reserved memory" -- Linux does not content itself with a simple gap\r
235 // in the memory map wherever the MCFG ACPI table points to.\r
236 //\r
237 // This appears to be a safety measure. The PCI Firmware Specification\r
238 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r
239 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r
240 // [...]". (Emphasis added here.)\r
241 //\r
242 // Normally we add memory resource descriptor HOBs in\r
243 // QemuInitializeRam(), and pre-allocate from those with memory\r
244 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r
245 // is most definitely not RAM; so, as an exception, cover it with\r
246 // uncacheable reserved memory right here.\r
247 //\r
248 AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
249 BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r
250 EfiReservedMemoryType);\r
251 }\r
252 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
253\r
254 //\r
255 // On Q35, the IO Port space is available for PCI resource allocations from\r
256 // 0x6000 up.\r
257 //\r
258 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
259 PciIoBase = 0x6000;\r
260 PciIoSize = 0xA000;\r
261 ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
262 }\r
263 }\r
264\r
265 //\r
266 // Add PCI IO Port space available for PCI resource allocations.\r
267 //\r
268 BuildResourceDescriptorHob (\r
269 EFI_RESOURCE_IO,\r
270 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
271 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
272 PciIoBase,\r
273 PciIoSize\r
274 );\r
275 PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r
276 ASSERT_RETURN_ERROR (PcdStatus);\r
277 PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r
278 ASSERT_RETURN_ERROR (PcdStatus);\r
279}\r
280\r
281EFI_STATUS\r
282GetNamedFwCfgBoolean (\r
283 IN CHAR8 *FwCfgFileName,\r
284 OUT BOOLEAN *Setting\r
285 )\r
286{\r
287 EFI_STATUS Status;\r
288 FIRMWARE_CONFIG_ITEM FwCfgItem;\r
289 UINTN FwCfgSize;\r
290 UINT8 Value[3];\r
291\r
292 Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
293 if (EFI_ERROR (Status)) {\r
294 return Status;\r
295 }\r
296 if (FwCfgSize > sizeof Value) {\r
297 return EFI_BAD_BUFFER_SIZE;\r
298 }\r
299 QemuFwCfgSelectItem (FwCfgItem);\r
300 QemuFwCfgReadBytes (FwCfgSize, Value);\r
301\r
302 if ((FwCfgSize == 1) ||\r
303 (FwCfgSize == 2 && Value[1] == '\n') ||\r
304 (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
305 switch (Value[0]) {\r
306 case '0':\r
307 case 'n':\r
308 case 'N':\r
309 *Setting = FALSE;\r
310 return EFI_SUCCESS;\r
311\r
312 case '1':\r
313 case 'y':\r
314 case 'Y':\r
315 *Setting = TRUE;\r
316 return EFI_SUCCESS;\r
317\r
318 default:\r
319 break;\r
320 }\r
321 }\r
322 return EFI_PROTOCOL_ERROR;\r
323}\r
324\r
325#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
326 do { \\r
327 BOOLEAN Setting; \\r
328 RETURN_STATUS PcdStatus; \\r
329 \\r
330 if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r
331 "opt/ovmf/" #TokenName, &Setting))) { \\r
332 PcdStatus = PcdSetBoolS (TokenName, Setting); \\r
333 ASSERT_RETURN_ERROR (PcdStatus); \\r
334 } \\r
335 } while (0)\r
336\r
337VOID\r
338NoexecDxeInitialization (\r
339 VOID\r
340 )\r
341{\r
342 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
343 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
344}\r
345\r
346VOID\r
347PciExBarInitialization (\r
348 VOID\r
349 )\r
350{\r
351 union {\r
352 UINT64 Uint64;\r
353 UINT32 Uint32[2];\r
354 } PciExBarBase;\r
355\r
356 //\r
357 // We only support the 256MB size for the MMCONFIG area:\r
358 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r
359 //\r
360 // The masks used below enforce the Q35 requirements that the MMCONFIG area\r
361 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r
362 //\r
363 // Note that (b) also ensures that the minimum address width we have\r
364 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r
365 // for DXE's page tables to cover the MMCONFIG area.\r
366 //\r
367 PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
368 ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r
369 ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r
370\r
371 //\r
372 // Clear the PCIEXBAREN bit first, before programming the high register.\r
373 //\r
374 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r
375\r
376 //\r
377 // Program the high register. Then program the low register, setting the\r
378 // MMCONFIG area size and enabling decoding at once.\r
379 //\r
380 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r
381 PciWrite32 (\r
382 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r
383 PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r
384 );\r
385}\r
386\r
387VOID\r
388MiscInitialization (\r
389 VOID\r
390 )\r
391{\r
392 UINTN PmCmd;\r
393 UINTN Pmba;\r
394 UINT32 PmbaAndVal;\r
395 UINT32 PmbaOrVal;\r
396 UINTN AcpiCtlReg;\r
397 UINT8 AcpiEnBit;\r
398 RETURN_STATUS PcdStatus;\r
399\r
400 //\r
401 // Disable A20 Mask\r
402 //\r
403 IoOr8 (0x92, BIT1);\r
404\r
405 //\r
406 // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
407 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
408 // S3 resume as well, so we build it unconditionally.)\r
409 //\r
410 BuildCpuHob (mPhysMemAddressWidth, 16);\r
411\r
412 //\r
413 // Determine platform type and save Host Bridge DID to PCD\r
414 //\r
415 switch (mHostBridgeDevId) {\r
416 case INTEL_82441_DEVICE_ID:\r
417 PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
418 Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
419 PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
420 PmbaOrVal = PIIX4_PMBA_VALUE;\r
421 AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
422 AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
423 break;\r
424 case INTEL_Q35_MCH_DEVICE_ID:\r
425 PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
426 Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
427 PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
428 PmbaOrVal = ICH9_PMBASE_VALUE;\r
429 AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
430 AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
431 break;\r
432 default:\r
433 DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
434 __FUNCTION__, mHostBridgeDevId));\r
435 ASSERT (FALSE);\r
436 return;\r
437 }\r
438 PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
439 ASSERT_RETURN_ERROR (PcdStatus);\r
440\r
441 //\r
442 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
443 // has been configured (e.g., by Xen) and skip the setup here.\r
444 // This matches the logic in AcpiTimerLibConstructor ().\r
445 //\r
446 if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
447 //\r
448 // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
449 // 1. set PMBA\r
450 //\r
451 PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
452\r
453 //\r
454 // 2. set PCICMD/IOSE\r
455 //\r
456 PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
457\r
458 //\r
459 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
460 //\r
461 PciOr8 (AcpiCtlReg, AcpiEnBit);\r
462 }\r
463\r
464 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
465 //\r
466 // Set Root Complex Register Block BAR\r
467 //\r
468 PciWrite32 (\r
469 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
470 ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
471 );\r
472\r
473 //\r
474 // Set PCI Express Register Range Base Address\r
475 //\r
476 PciExBarInitialization ();\r
477 }\r
478}\r
479\r
480\r
481VOID\r
482BootModeInitialization (\r
483 VOID\r
484 )\r
485{\r
486 EFI_STATUS Status;\r
487\r
488 if (CmosRead8 (0xF) == 0xFE) {\r
489 mBootMode = BOOT_ON_S3_RESUME;\r
490 }\r
491 CmosWrite8 (0xF, 0x00);\r
492\r
493 Status = PeiServicesSetBootMode (mBootMode);\r
494 ASSERT_EFI_ERROR (Status);\r
495\r
496 Status = PeiServicesInstallPpi (mPpiBootMode);\r
497 ASSERT_EFI_ERROR (Status);\r
498}\r
499\r
500\r
501VOID\r
502ReserveEmuVariableNvStore (\r
503 )\r
504{\r
505 EFI_PHYSICAL_ADDRESS VariableStore;\r
506 RETURN_STATUS PcdStatus;\r
507 UINT32 Alignment;\r
508\r
509 //\r
510 // Allocate storage for NV variables early on so it will be\r
511 // at a consistent address. Since VM memory is preserved\r
512 // across reboots, this allows the NV variable storage to survive\r
513 // a VM reboot.\r
514 //\r
515 Alignment = PcdGet32 (PcdFlashNvStorageFtwSpareSize);\r
516 if ((Alignment & (Alignment - 1)) != 0) {\r
517 //\r
518 // Round up Alignment to the next power of two.\r
519 //\r
520 Alignment = GetPowerOfTwo32 (Alignment) << 1;\r
521 }\r
522\r
523 VariableStore =\r
524 (EFI_PHYSICAL_ADDRESS)(UINTN)\r
525 AllocateAlignedRuntimePages (\r
526 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
527 Alignment\r
528 );\r
529 DEBUG ((EFI_D_INFO,\r
530 "Reserved variable store memory: 0x%lX; size: %dkb, "\r
531 "alignment: 0x%x\n",\r
532 VariableStore,\r
533 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024,\r
534 Alignment\r
535 ));\r
536 PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
537 ASSERT_RETURN_ERROR (PcdStatus);\r
538}\r
539\r
540\r
541VOID\r
542DebugDumpCmos (\r
543 VOID\r
544 )\r
545{\r
546 UINT32 Loop;\r
547\r
548 DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
549\r
550 for (Loop = 0; Loop < 0x80; Loop++) {\r
551 if ((Loop % 0x10) == 0) {\r
552 DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
553 }\r
554 DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
555 if ((Loop % 0x10) == 0xf) {\r
556 DEBUG ((EFI_D_INFO, "\n"));\r
557 }\r
558 }\r
559}\r
560\r
561\r
562VOID\r
563S3Verification (\r
564 VOID\r
565 )\r
566{\r
567#if defined (MDE_CPU_X64)\r
568 if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
569 DEBUG ((EFI_D_ERROR,\r
570 "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r
571 DEBUG ((EFI_D_ERROR,\r
572 "%a: Please disable S3 on the QEMU command line (see the README),\n",\r
573 __FUNCTION__));\r
574 DEBUG ((EFI_D_ERROR,\r
575 "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r
576 ASSERT (FALSE);\r
577 CpuDeadLoop ();\r
578 }\r
579#endif\r
580}\r
581\r
582\r
583/**\r
584 Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.\r
585 Set the mMaxCpuCount variable.\r
586**/\r
587VOID\r
588MaxCpuCountInitialization (\r
589 VOID\r
590 )\r
591{\r
592 UINT16 ProcessorCount;\r
593 RETURN_STATUS PcdStatus;\r
594\r
595 QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r
596 ProcessorCount = QemuFwCfgRead16 ();\r
597 //\r
598 // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount\r
599 // from the PCD default. No change to PCDs.\r
600 //\r
601 if (ProcessorCount == 0) {\r
602 mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
603 return;\r
604 }\r
605 //\r
606 // Otherwise, set mMaxCpuCount to the value reported by QEMU.\r
607 //\r
608 mMaxCpuCount = ProcessorCount;\r
609 //\r
610 // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)\r
611 // to wait, in the initial AP bringup, exactly as long as it takes for all of\r
612 // the APs to report in. For this, we set the longest representable timeout\r
613 // (approx. 71 minutes).\r
614 //\r
615 PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);\r
616 ASSERT_RETURN_ERROR (PcdStatus);\r
617 PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);\r
618 ASSERT_RETURN_ERROR (PcdStatus);\r
619 DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,\r
620 ProcessorCount));\r
621}\r
622\r
623\r
624/**\r
625 Perform Platform PEI initialization.\r
626\r
627 @param FileHandle Handle of the file being invoked.\r
628 @param PeiServices Describes the list of possible PEI Services.\r
629\r
630 @return EFI_SUCCESS The PEIM initialized successfully.\r
631\r
632**/\r
633EFI_STATUS\r
634EFIAPI\r
635InitializePlatform (\r
636 IN EFI_PEI_FILE_HANDLE FileHandle,\r
637 IN CONST EFI_PEI_SERVICES **PeiServices\r
638 )\r
639{\r
640 EFI_STATUS Status;\r
641\r
642 DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
643\r
644 DebugDumpCmos ();\r
645\r
646 XenDetect ();\r
647\r
648 if (QemuFwCfgS3Enabled ()) {\r
649 DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
650 mS3Supported = TRUE;\r
651 Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
652 ASSERT_EFI_ERROR (Status);\r
653 }\r
654\r
655 S3Verification ();\r
656 BootModeInitialization ();\r
657 AddressWidthInitialization ();\r
658 MaxCpuCountInitialization ();\r
659\r
660 PublishPeiMemory ();\r
661\r
662 InitializeRamRegions ();\r
663\r
664 if (mXen) {\r
665 DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
666 InitializeXen ();\r
667 }\r
668\r
669 //\r
670 // Query Host Bridge DID\r
671 //\r
672 mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
673\r
674 if (mBootMode != BOOT_ON_S3_RESUME) {\r
675 if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
676 ReserveEmuVariableNvStore ();\r
677 }\r
678 PeiFvInitialization ();\r
679 MemMapInitialization ();\r
680 NoexecDxeInitialization ();\r
681 }\r
682\r
683 MiscInitialization ();\r
684 InstallFeatureControlCallback ();\r
685\r
686 return EFI_SUCCESS;\r
687}\r
EFI Development Kit II mirror for PVE