[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Spi / Common / SpiCommon.c

/** @file\r
PCH SPI Common Driver implements the SPI Host Controller Compatibility Interface.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "PchSpi.h"\r
\r
VOID\r
FillOutPublicInfoStruct (\r
  SPI_INSTANCE          *SpiInstance\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Fillout SpiInstance->InitInfo;\r
\r
Arguments:\r
\r
  SpiInstance   - Pointer to SpiInstance to initialize\r
\r
Returns:\r
\r
  NONE\r
\r
--*/\r
{\r
  UINT8         Index;\r
\r
  SpiInstance->InitInfo.InitTable = &SpiInstance->SpiInitTable;\r
\r
  //\r
  // Give invalid index in case operation not supported.\r
  //\r
  SpiInstance->InitInfo.JedecIdOpcodeIndex = 0xff;\r
  SpiInstance->InitInfo.OtherOpcodeIndex = 0xff;\r
  SpiInstance->InitInfo.WriteStatusOpcodeIndex = 0xff;\r
  SpiInstance->InitInfo.ProgramOpcodeIndex = 0xff;\r
  SpiInstance->InitInfo.ReadOpcodeIndex = 0xff;\r
  SpiInstance->InitInfo.EraseOpcodeIndex = 0xff;\r
  SpiInstance->InitInfo.ReadStatusOpcodeIndex = 0xff;\r
  SpiInstance->InitInfo.FullChipEraseOpcodeIndex = 0xff;\r
  for (Index = 0; Index < SPI_NUM_OPCODE; Index++) {\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationJedecId) {\r
      SpiInstance->InitInfo.JedecIdOpcodeIndex = Index;\r
    }\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationOther) {\r
      SpiInstance->InitInfo.OtherOpcodeIndex = Index;\r
    }\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationWriteStatus) {\r
      SpiInstance->InitInfo.WriteStatusOpcodeIndex = Index;\r
    }\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationProgramData_1_Byte ||\r
        SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationProgramData_64_Byte) {\r
      SpiInstance->InitInfo.ProgramOpcodeIndex = Index;\r
    }\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationReadData ||\r
        SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationFastRead ||\r
        SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationDualOutputFastRead) {\r
      SpiInstance->InitInfo.ReadOpcodeIndex = Index;\r
    }\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationErase_256_Byte ||\r
        SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationErase_4K_Byte ||\r
        SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationErase_8K_Byte ||\r
        SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationErase_64K_Byte) {\r
      SpiInstance->InitInfo.EraseOpcodeIndex = Index;\r
    }\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationReadStatus) {\r
      SpiInstance->InitInfo.ReadStatusOpcodeIndex = Index;\r
    }\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationFullChipErase) {\r
      SpiInstance->InitInfo.FullChipEraseOpcodeIndex = Index;\r
    }\r
  }\r
}\r
\r
EFI_STATUS\r
SpiProtocolConstructor (\r
  SPI_INSTANCE          *SpiInstance\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Initialize an SPI protocol instance.\r
  The function will assert in debug if PCH RCBA has not been initialized\r
\r
Arguments:\r
\r
  SpiInstance   - Pointer to SpiInstance to initialize\r
\r
Returns:\r
\r
  EFI_SUCCESS     The protocol instance was properly initialized\r
  EFI_UNSUPPORTED The PCH is not supported by this module\r
\r
--*/\r
{\r
  SpiInstance->InitDone = FALSE;  // Indicate NOT READY.\r
\r
  //\r
  // Check if the current PCH is known and supported by this code\r
  //\r
  if (!IsQncSupported ()) {\r
    DEBUG ((DEBUG_ERROR, "PCH SPI Protocol not supported due to no proper QNC LPC found!\n"));\r
    return EFI_UNSUPPORTED;\r
  }\r
  //\r
  // Initialize the SPI protocol instance\r
  //\r
  SpiInstance->Signature            = PCH_SPI_PRIVATE_DATA_SIGNATURE;\r
  SpiInstance->Handle               = NULL;\r
  SpiInstance->SpiProtocol.Init     = SpiProtocolInit;\r
  SpiInstance->SpiProtocol.Lock     = SpiProtocolLock;\r
  SpiInstance->SpiProtocol.Execute  = SpiProtocolExecute;\r
  SpiInstance->SpiProtocol.Info     = SpiProtocolInfo;\r
\r
  //\r
  // Sanity check to ensure PCH RCBA initialization has occurred previously.\r
  //\r
  SpiInstance->PchRootComplexBar = MmioRead32 (\r
                                    PciDeviceMmBase (PCI_BUS_NUMBER_QNC,\r
                                    PCI_DEVICE_NUMBER_QNC_LPC,\r
                                    PCI_FUNCTION_NUMBER_QNC_LPC) + R_QNC_LPC_RCBA\r
                                    ) & B_QNC_LPC_RCBA_MASK;\r
  ASSERT (SpiInstance->PchRootComplexBar != 0);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
UnlockFlashComponents (\r
  IN      EFI_SPI_PROTOCOL      *This,\r
  IN      UINT8                 UnlockCmdOpcodeIndex\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Issue unlock command to disable block protection, this only needs to be done once per SPI power on\r
\r
Arguments:\r
\r
  This                      A pointer to "EFI_SPI_PROTOCOL" for issuing commands\r
  UnlockCmdOpcodeIndex      The index of the Unlock command\r
\r
Returns:\r
\r
  EFI_SUCCESS               UnLock operation succeed.\r
  EFI_DEVICE_ERROR          Device error, operation failed.\r
\r
--*/\r
{\r
  EFI_STATUS    Status;\r
  SPI_INSTANCE  *SpiInstance;\r
  UINT8         SpiStatus;\r
  UINTN         PchRootComplexBar;\r
\r
  if (UnlockCmdOpcodeIndex >= SPI_NUM_OPCODE) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);\r
  PchRootComplexBar = SpiInstance->PchRootComplexBar;\r
\r
  //\r
  // Issue unlock command to disable block protection, this only needs to be done once per SPI power on\r
  //\r
  SpiStatus = 0;\r
  //\r
  // Issue unlock command to the flash component 1 at first\r
  //\r
  Status = SpiProtocolExecute (\r
            This,\r
            UnlockCmdOpcodeIndex,\r
            SpiInstance->SpiInitTable.PrefixOpcode[0] == PCH_SPI_COMMAND_WRITE_ENABLE ? 0 : 1,\r
            TRUE,\r
            TRUE,\r
            TRUE,\r
            (UINTN) 0,\r
            sizeof (SpiStatus),\r
            &SpiStatus,\r
            EnumSpiRegionAll\r
            );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "Unlock flash component 1 fail!\n"));\r
    return Status;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
SpiProtocolInit (\r
  IN EFI_SPI_PROTOCOL       *This,\r
  IN SPI_INIT_TABLE         *InitTable\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Initialize the host controller to execute SPI command.\r
\r
Arguments:\r
\r
  This                    Pointer to the EFI_SPI_PROTOCOL instance.\r
  InitTable               Initialization data to be programmed into the SPI host controller.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Initialization completed.\r
  EFI_ACCESS_DENIED       The SPI static configuration interface has been locked-down.\r
  EFI_INVALID_PARAMETER   Bad input parameters.\r
  EFI_UNSUPPORTED         Can't get Descriptor mode VSCC values\r
--*/\r
{\r
  EFI_STATUS    Status;\r
  UINT8         Index;\r
  UINT16        OpcodeType;\r
  SPI_INSTANCE  *SpiInstance;\r
  BOOLEAN       MultiPartitionIsSupported;\r
  UINTN         PchRootComplexBar;\r
  UINT8         SFDPCmdOpcodeIndex;\r
  UINT8         UnlockCmdOpcodeIndex;\r
  UINT8         ReadDataCmdOpcodeIndex;\r
  UINT8         FlashPartId[3];\r
\r
  SpiInstance       = SPI_INSTANCE_FROM_SPIPROTOCOL (This);\r
  PchRootComplexBar = SpiInstance->PchRootComplexBar;\r
\r
  if (InitTable != NULL) {\r
    //\r
    // Copy table into SPI driver Private data structure\r
    //\r
    CopyMem (\r
      &SpiInstance->SpiInitTable,\r
      InitTable,\r
      sizeof (SPI_INIT_TABLE)\r
      );\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  //\r
  // Check if the SPI interface has been locked-down.\r
  //\r
  if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) {\r
    ASSERT_EFI_ERROR (EFI_ACCESS_DENIED);\r
    return EFI_ACCESS_DENIED;\r
  }\r
  //\r
  // Clear all the status bits for status regs.\r
  //\r
  MmioOr16 (\r
    (UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS),\r
    (UINT16) ((B_QNC_RCRB_SPIS_CDS | B_QNC_RCRB_SPIS_BAS))\r
    );\r
  MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS);\r
\r
  //\r
  // Set the Prefix Opcode registers.\r
  //\r
  MmioWrite16 (\r
    PchRootComplexBar + R_QNC_RCRB_SPIPREOP,\r
    (SpiInstance->SpiInitTable.PrefixOpcode[1] << 8) | InitTable->PrefixOpcode[0]\r
    );\r
  MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIPREOP);\r
\r
  //\r
  // Set Opcode Type Configuration registers.\r
  //\r
  for (Index = 0, OpcodeType = 0; Index < SPI_NUM_OPCODE; Index++) {\r
    switch (SpiInstance->SpiInitTable.OpcodeMenu[Index].Type) {\r
    case EnumSpiOpcodeRead:\r
      OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_ADD_READ << (Index * 2));\r
      break;\r
    case EnumSpiOpcodeWrite:\r
      OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_ADD_WRITE << (Index * 2));\r
      break;\r
    case EnumSpiOpcodeWriteNoAddr:\r
      OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE << (Index * 2));\r
      break;\r
    default:\r
      OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_NOADD_READ << (Index * 2));\r
      break;\r
    }\r
  }\r
  MmioWrite16 (PchRootComplexBar + R_QNC_RCRB_SPIOPTYPE, OpcodeType);\r
  MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIOPTYPE);\r
\r
  //\r
  // Setup the Opcode Menu registers.\r
  //\r
  ReadDataCmdOpcodeIndex = SPI_NUM_OPCODE;\r
  SFDPCmdOpcodeIndex = SPI_NUM_OPCODE;\r
  UnlockCmdOpcodeIndex = SPI_NUM_OPCODE;\r
  for (Index = 0; Index < SPI_NUM_OPCODE; Index++) {\r
    MmioWrite8 (\r
      PchRootComplexBar + R_QNC_RCRB_SPIOPMENU + Index,\r
      SpiInstance->SpiInitTable.OpcodeMenu[Index].Code\r
      );\r
    MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPIOPMENU + Index);\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationJedecId) {\r
      Status = SpiProtocolExecute (\r
                This,\r
                Index,\r
                0,\r
                TRUE,\r
                TRUE,\r
                FALSE,\r
                (UINTN) 0,\r
                3,\r
                FlashPartId,\r
                EnumSpiRegionDescriptor\r
                );\r
      if (EFI_ERROR (Status)) {\r
        return Status;\r
      }\r
      if (FlashPartId[0] != SpiInstance->SpiInitTable.VendorId  ||\r
          FlashPartId[1] != SpiInstance->SpiInitTable.DeviceId0 ||\r
          FlashPartId[2] != SpiInstance->SpiInitTable.DeviceId1) {\r
        return EFI_INVALID_PARAMETER;\r
      }\r
    }\r
\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationReadData ||\r
        SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationFastRead ||\r
        SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationDualOutputFastRead) {\r
      ReadDataCmdOpcodeIndex = Index;\r
    }\r
\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationDiscoveryParameters) {\r
      SFDPCmdOpcodeIndex = Index;\r
    }\r
\r
    if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationWriteStatus) {\r
      UnlockCmdOpcodeIndex = Index;\r
    }\r
  }\r
\r
  MultiPartitionIsSupported = FALSE;\r
\r
  Status = UnlockFlashComponents (\r
            This,\r
            UnlockCmdOpcodeIndex\r
            );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "Unlock flash components fail!\n"));\r
  }\r
\r
  SpiPhaseInit ();\r
  FillOutPublicInfoStruct (SpiInstance);\r
  SpiInstance->InitDone = TRUE;\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
SpiProtocolLock (\r
  IN EFI_SPI_PROTOCOL     *This\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Lock the SPI Static Configuration Interface.\r
  Once locked, the interface can not be changed and can only be clear by system reset.\r
\r
Arguments:\r
\r
  This      Pointer to the EFI_SPI_PROTOCOL instance.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Lock operation succeed.\r
  EFI_DEVICE_ERROR        Device error, operation failed.\r
  EFI_ACCESS_DENIED       The interface has already been locked.\r
\r
--*/\r
{\r
  SPI_INSTANCE  *SpiInstance;\r
  UINTN         PchRootComplexBar;\r
\r
  SpiInstance       = SPI_INSTANCE_FROM_SPIPROTOCOL (This);\r
  PchRootComplexBar = SpiInstance->PchRootComplexBar;\r
\r
  //\r
  // Check if the SPI interface has been locked-down.\r
  //\r
  if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) {\r
    return EFI_ACCESS_DENIED;\r
  }\r
\r
  //\r
  // Lock-down the configuration interface.\r
  //\r
  MmioOr16 ((UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS), (UINT16) (B_QNC_RCRB_SPIS_SCL));\r
\r
  //\r
  // Verify if it's really locked.\r
  //\r
  if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) == 0) {\r
    return EFI_DEVICE_ERROR;\r
  } else {\r
    //\r
    // Save updated register in S3 Boot script.\r
    //\r
    S3BootScriptSaveMemWrite (\r
      S3BootScriptWidthUint16,\r
        (UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS),\r
        1,\r
        (VOID *) (UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS)\r
        );\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
SpiProtocolExecute (\r
  IN     EFI_SPI_PROTOCOL   *This,\r
  IN     UINT8              OpcodeIndex,\r
  IN     UINT8              PrefixOpcodeIndex,\r
  IN     BOOLEAN            DataCycle,\r
  IN     BOOLEAN            Atomic,\r
  IN     BOOLEAN            ShiftOut,\r
  IN     UINTN              Address,\r
  IN     UINT32             DataByteCount,\r
  IN OUT UINT8              *Buffer,\r
  IN     SPI_REGION_TYPE    SpiRegionType\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Execute SPI commands from the host controller.\r
  This function would be called by runtime driver, please do not use any MMIO marco here\r
\r
Arguments:\r
\r
  This              Pointer to the EFI_SPI_PROTOCOL instance.\r
  OpcodeIndex       Index of the command in the OpCode Menu.\r
  PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
  DataCycle         TRUE if the SPI cycle contains data\r
  Atomic            TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
  ShiftOut          If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
  Address           In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
                    Region, this value specifies the offset from the Region Base; for BIOS Region,\r
                    this value specifies the offset from the start of the BIOS Image. In Non\r
                    Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
                    Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
                    Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
                    supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
                    the flash (in Non Descriptor Mode)\r
  DataByteCount     Number of bytes in the data portion of the SPI cycle. This function may break the\r
                    data transfer into multiple operations. This function ensures each operation does\r
                    not cross 256 byte flash address boundary.\r
                    *NOTE: if there is some SPI chip that has a stricter address boundary requirement\r
                    (e.g., its write page size is < 256 byte), then the caller cannot rely on this\r
                    function to cut the data transfer at proper address boundaries, and it's the\r
                    caller's reponsibility to pass in a properly cut DataByteCount parameter.\r
  Buffer            Pointer to caller-allocated buffer containing the dada received or sent during the\r
                    SPI cycle.\r
  SpiRegionType     SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
                    EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
                    Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
                    and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
                    to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
\r
Returns:\r
\r
  EFI_SUCCESS             Command succeed.\r
  EFI_INVALID_PARAMETER   The parameters specified are not valid.\r
  EFI_UNSUPPORTED         Command not supported.\r
  EFI_DEVICE_ERROR        Device error, command aborts abnormally.\r
\r
--*/\r
{\r
  EFI_STATUS  Status;\r
  UINT16      BiosCtlSave;\r
  UINT32      SmiEnSave;\r
\r
  BiosCtlSave = 0;\r
  SmiEnSave   = 0;\r
\r
  //\r
  // Check if the parameters are valid.\r
  //\r
  if ((OpcodeIndex >= SPI_NUM_OPCODE) || (PrefixOpcodeIndex >= SPI_NUM_PREFIX_OPCODE)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  //\r
  // Make sure it's safe to program the command.\r
  //\r
  if (!WaitForSpiCycleComplete (This, FALSE)) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  //\r
  // Acquire access to the SPI interface is not required any more.\r
  //\r
  //\r
  // Disable SMIs to make sure normal mode flash access is not interrupted by an SMI\r
  // whose SMI handler accesses flash (e.g. for error logging)\r
  //\r
  SmiEnSave = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);\r
  QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, (SmiEnSave & ~SMI_EN));\r
\r
  //\r
  // Save BIOS Ctrl register\r
  //\r
  BiosCtlSave = PciRead16 (\r
                  PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC,\r
                  PCI_DEVICE_NUMBER_QNC_LPC,\r
                  PCI_FUNCTION_NUMBER_QNC_LPC,\r
                  R_QNC_LPC_BIOS_CNTL)\r
                  ) & (B_QNC_LPC_BIOS_CNTL_BCD | B_QNC_LPC_BIOS_CNTL_PFE | B_QNC_LPC_BIOS_CNTL_BIOSWE | B_QNC_LPC_BIOS_CNTL_SMM_BWP);\r
\r
  //\r
  // Enable flash writing\r
  //\r
  PciOr16 (\r
    PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC,\r
    PCI_DEVICE_NUMBER_QNC_LPC,\r
    PCI_FUNCTION_NUMBER_QNC_LPC,\r
    R_QNC_LPC_BIOS_CNTL),\r
    (UINT16) (B_QNC_LPC_BIOS_CNTL_BIOSWE | B_QNC_LPC_BIOS_CNTL_SMM_BWP)\r
    );\r
\r
  //\r
  // If shifts the data out, disable Prefetching and Caching.\r
  //\r
  if (ShiftOut) {\r
    PciAndThenOr16 (\r
      PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC,\r
      PCI_DEVICE_NUMBER_QNC_LPC,\r
      PCI_FUNCTION_NUMBER_QNC_LPC,\r
      R_QNC_LPC_BIOS_CNTL),\r
      (UINT16) (~(B_QNC_LPC_BIOS_CNTL_BCD | B_QNC_LPC_BIOS_CNTL_PFE)),\r
      (UINT16) ((B_QNC_LPC_BIOS_CNTL_BCD))\r
      );\r
  }\r
  //\r
  // Sends the command to the SPI interface to execute.\r
  //\r
  Status = SendSpiCmd (\r
            This,\r
            OpcodeIndex,\r
            PrefixOpcodeIndex,\r
            DataCycle,\r
            Atomic,\r
            ShiftOut,\r
            Address,\r
            DataByteCount,\r
            Buffer,\r
            SpiRegionType\r
            );\r
\r
  //\r
  // Restore BIOS Ctrl register\r
  //\r
  PciAndThenOr16 (\r
    PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC,\r
    PCI_DEVICE_NUMBER_QNC_LPC,\r
    PCI_FUNCTION_NUMBER_QNC_LPC,\r
    R_QNC_LPC_BIOS_CNTL),\r
    (UINT16) (~(B_QNC_LPC_BIOS_CNTL_BCD | B_QNC_LPC_BIOS_CNTL_PFE | B_QNC_LPC_BIOS_CNTL_BIOSWE | B_QNC_LPC_BIOS_CNTL_SMM_BWP)),\r
    (UINT16) (BiosCtlSave)\r
      );\r
  //\r
  // Restore SMIs.\r
  //\r
  QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, SmiEnSave);\r
\r
  return Status;\r
}\r
\r
VOID\r
SpiOffset2Physical (\r
  IN      EFI_SPI_PROTOCOL  *This,\r
  IN      UINTN             SpiRegionOffset,\r
  IN      SPI_REGION_TYPE   SpiRegionType,\r
  OUT     UINTN             *HardwareSpiAddress,\r
  OUT     UINTN             *BaseAddress,\r
  OUT     UINTN             *LimitAddress\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Convert SPI offset to Physical address of SPI hardware\r
\r
Arguments:\r
\r
  This               Pointer to the EFI_SPI_PROTOCOL instance.\r
  SpiRegionOffset    In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
                     Region, this value specifies the offset from the Region Base; for BIOS Region,\r
                     this value specifies the offset from the start of the BIOS Image. In Non\r
                     Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
                     Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
                     Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
                     supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
                     the flash (in Non Descriptor Mode)\r
  BaseAddress        Base Address of the region.\r
  SpiRegionType      SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
                     EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
                     Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
                     and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
                     to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
  HardwareSpiAddress Return absolution SPI address (i.e., Flash Linear Address)\r
  BaseAddress        Return base address of the region type\r
  LimitAddress       Return limit address of the region type\r
\r
Returns:\r
\r
  EFI_SUCCESS             Command succeed.\r
\r
--*/\r
{\r
  SPI_INSTANCE  *SpiInstance;\r
  UINTN         PchRootComplexBar;\r
\r
  SpiInstance       = SPI_INSTANCE_FROM_SPIPROTOCOL (This);\r
  PchRootComplexBar = SpiInstance->PchRootComplexBar;\r
\r
  if (SpiRegionType == EnumSpiRegionAll) {\r
    //\r
    // EnumSpiRegionAll indicates address is relative to flash device (i.e., address is Flash\r
    // Linear Address)\r
    //\r
    *HardwareSpiAddress = SpiRegionOffset;\r
  } else {\r
    //\r
    // Otherwise address is relative to BIOS image\r
    //\r
    *HardwareSpiAddress = SpiRegionOffset + SpiInstance->SpiInitTable.BiosStartOffset;\r
  }\r
}\r
\r
EFI_STATUS\r
SendSpiCmd (\r
  IN     EFI_SPI_PROTOCOL   *This,\r
  IN     UINT8              OpcodeIndex,\r
  IN     UINT8              PrefixOpcodeIndex,\r
  IN     BOOLEAN            DataCycle,\r
  IN     BOOLEAN            Atomic,\r
  IN     BOOLEAN            ShiftOut,\r
  IN     UINTN              Address,\r
  IN     UINT32             DataByteCount,\r
  IN OUT UINT8              *Buffer,\r
  IN     SPI_REGION_TYPE    SpiRegionType\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  This function sends the programmed SPI command to the slave device.\r
\r
Arguments:\r
\r
  OpcodeIndex       Index of the command in the OpCode Menu.\r
  PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
  DataCycle         TRUE if the SPI cycle contains data\r
  Atomic            TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
  ShiftOut          If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
  Address           In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
                    Region, this value specifies the offset from the Region Base; for BIOS Region,\r
                    this value specifies the offset from the start of the BIOS Image. In Non\r
                    Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
                    Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
                    Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
                    supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
                    the flash (in Non Descriptor Mode)\r
  DataByteCount     Number of bytes in the data portion of the SPI cycle. This function may break the\r
                    data transfer into multiple operations. This function ensures each operation does\r
                    not cross 256 byte flash address boundary.\r
                    *NOTE: if there is some SPI chip that has a stricter address boundary requirement\r
                    (e.g., its write page size is < 256 byte), then the caller cannot rely on this\r
                    function to cut the data transfer at proper address boundaries, and it's the\r
                    caller's reponsibility to pass in a properly cut DataByteCount parameter.\r
  Buffer            Data received or sent during the SPI cycle.\r
  SpiRegionType     SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
                    EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
                    Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
                    and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
                    to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
\r
Returns:\r
\r
  EFI_SUCCESS             SPI command completes successfully.\r
  EFI_DEVICE_ERROR        Device error, the command aborts abnormally.\r
  EFI_ACCESS_DENIED       Some unrecognized command encountered in hardware sequencing mode\r
  EFI_INVALID_PARAMETER   The parameters specified are not valid.\r
\r
--*/\r
{\r
  UINT32        Index;\r
  SPI_INSTANCE  *SpiInstance;\r
  UINTN         HardwareSpiAddr;\r
  UINTN         SpiBiosSize;\r
  UINTN         BaseAddress;\r
  UINTN         LimitAddress;\r
  UINT32        SpiDataCount;\r
  UINT8         OpCode;\r
  SPI_OPERATION Operation;\r
  UINTN         PchRootComplexBar;\r
\r
  SpiInstance       = SPI_INSTANCE_FROM_SPIPROTOCOL (This);\r
  PchRootComplexBar = SpiInstance->PchRootComplexBar;\r
  SpiBiosSize       = SpiInstance->SpiInitTable.BiosSize;\r
  Operation         = SpiInstance->SpiInitTable.OpcodeMenu[OpcodeIndex].Operation;\r
  OpCode            = MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPIOPMENU + OpcodeIndex);\r
\r
  //\r
  // Check if the value of opcode register is 0 or the BIOS Size of SpiInitTable is 0\r
  //\r
  if (OpCode == 0 || SpiBiosSize == 0) {\r
    ASSERT (FALSE);\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  SpiOffset2Physical (This, Address, SpiRegionType, &HardwareSpiAddr, &BaseAddress, &LimitAddress);\r
  //\r
  // Have direct access to BIOS region in Descriptor mode,\r
  //\r
  if (SpiInstance->SpiInitTable.OpcodeMenu[OpcodeIndex].Type == EnumSpiOpcodeRead &&\r
      SpiRegionType == EnumSpiRegionBios) {\r
    CopyMem (\r
      Buffer,\r
      (UINT8 *) ((HardwareSpiAddr - BaseAddress) + (UINT32) (~(SpiBiosSize - 1))),\r
      DataByteCount\r
      );\r
    return EFI_SUCCESS;\r
  }\r
  //\r
  // DEBUG((EFI_D_ERROR, "SPIADDR %x, %x, %x, %x\n", Address, HardwareSpiAddr, BaseAddress,\r
  // LimitAddress));\r
  //\r
  if ((DataCycle == FALSE) && (DataByteCount > 0)) {\r
    DataByteCount = 0;\r
  }\r
\r
  do {\r
    //\r
    // Trim at 256 byte boundary per operation,\r
    // - PCH SPI controller requires trimming at 4KB boundary\r
    // - Some SPI chips require trimming at 256 byte boundary for write operation\r
    // - Trimming has limited performance impact as we can read / write atmost 64 byte\r
    //   per operation\r
    //\r
    if (HardwareSpiAddr + DataByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {\r
      SpiDataCount = (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32) (HardwareSpiAddr);\r
    } else {\r
      SpiDataCount = DataByteCount;\r
    }\r
    //\r
    // Calculate the number of bytes to shift in/out during the SPI data cycle.\r
    // Valid settings for the number of bytes duing each data portion of the\r
    // PCH SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48, 56, 64\r
    //\r
    if (SpiDataCount >= 64) {\r
      SpiDataCount = 64;\r
    } else if ((SpiDataCount &~0x07) != 0) {\r
      SpiDataCount = SpiDataCount &~0x07;\r
    }\r
    //\r
    // If shifts data out, load data into the SPI data buffer.\r
    //\r
    if (ShiftOut) {\r
      for (Index = 0; Index < SpiDataCount; Index++) {\r
        MmioWrite8 (PchRootComplexBar + R_QNC_RCRB_SPID0 + Index, Buffer[Index]);\r
        MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPID0 + Index);\r
      }\r
    }\r
\r
    MmioWrite32 (\r
      (PchRootComplexBar + R_QNC_RCRB_SPIA),\r
      (UINT32) (HardwareSpiAddr & B_QNC_RCRB_SPIA_MASK)\r
      );\r
    MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIA);\r
\r
    //\r
    // Execute the command on the SPI compatible mode\r
    //\r
\r
    //\r
    // Clear error flags\r
    //\r
    MmioOr16 ((PchRootComplexBar + R_QNC_RCRB_SPIS), B_QNC_RCRB_SPIS_BAS);\r
\r
    //\r
    // Initialte the SPI cycle\r
    //\r
    if (DataCycle) {\r
      MmioWrite16 (\r
        (PchRootComplexBar + R_QNC_RCRB_SPIC),\r
        ( (UINT16) (B_QNC_RCRB_SPIC_DC) | (UINT16) (((SpiDataCount - 1) << 8) & B_QNC_RCRB_SPIC_DBC) |\r
          (UINT16) ((OpcodeIndex << 4) & B_QNC_RCRB_SPIC_COP) |\r
          (UINT16) ((PrefixOpcodeIndex << 3) & B_QNC_RCRB_SPIC_SPOP) |\r
          (UINT16) (Atomic ? B_QNC_RCRB_SPIC_ACS : 0) |\r
          (UINT16) (B_QNC_RCRB_SPIC_SCGO)));\r
    } else {\r
      MmioWrite16 (\r
        (PchRootComplexBar + R_QNC_RCRB_SPIC),\r
        ( (UINT16) ((OpcodeIndex << 4) & B_QNC_RCRB_SPIC_COP) |\r
          (UINT16) ((PrefixOpcodeIndex << 3) & B_QNC_RCRB_SPIC_SPOP) |\r
          (UINT16) (Atomic ? B_QNC_RCRB_SPIC_ACS : 0) |\r
          (UINT16) (B_QNC_RCRB_SPIC_SCGO)));\r
    }\r
\r
    MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIC);\r
\r
    //\r
    // end of command execution\r
    //\r
    // Wait the SPI cycle to complete.\r
    //\r
    if (!WaitForSpiCycleComplete (This, TRUE)) {\r
      return EFI_DEVICE_ERROR;\r
    }\r
    //\r
    // If shifts data in, get data from the SPI data buffer.\r
    //\r
    if (!ShiftOut) {\r
      for (Index = 0; Index < SpiDataCount; Index++) {\r
        Buffer[Index] = MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPID0 + Index);\r
      }\r
    }\r
\r
    HardwareSpiAddr += SpiDataCount;\r
    Buffer += SpiDataCount;\r
    DataByteCount -= SpiDataCount;\r
  } while (DataByteCount > 0);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
BOOLEAN\r
WaitForSpiCycleComplete (\r
  IN     EFI_SPI_PROTOCOL   *This,\r
  IN     BOOLEAN            ErrorCheck\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Wait execution cycle to complete on the SPI interface. Check both Hardware\r
  and Software Sequencing status registers\r
\r
Arguments:\r
\r
  This                - The SPI protocol instance\r
  UseSoftwareSequence - TRUE if this is a Hardware Sequencing operation\r
  ErrorCheck          - TRUE if the SpiCycle needs to do the error check\r
\r
Returns:\r
\r
  TRUE       SPI cycle completed on the interface.\r
  FALSE      Time out while waiting the SPI cycle to complete.\r
             It's not safe to program the next command on the SPI interface.\r
\r
--*/\r
{\r
  UINT64        WaitTicks;\r
  UINT64        WaitCount;\r
  UINT16        Data16;\r
  SPI_INSTANCE  *SpiInstance;\r
  UINTN         PchRootComplexBar;\r
\r
  SpiInstance       = SPI_INSTANCE_FROM_SPIPROTOCOL (This);\r
  PchRootComplexBar = SpiInstance->PchRootComplexBar;\r
\r
  //\r
  // Convert the wait period allowed into to tick count\r
  //\r
  WaitCount = WAIT_TIME / WAIT_PERIOD;\r
\r
  //\r
  // Wait for the SPI cycle to complete.\r
  //\r
  for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {\r
    Data16 = MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS);\r
    if ((Data16 & B_QNC_RCRB_SPIS_SCIP) == 0) {\r
      MmioWrite16 (PchRootComplexBar + R_QNC_RCRB_SPIS, (B_QNC_RCRB_SPIS_BAS | B_QNC_RCRB_SPIS_CDS));\r
      if ((Data16 & B_QNC_RCRB_SPIS_BAS) && (ErrorCheck == TRUE)) {\r
        return FALSE;\r
      } else {\r
        return TRUE;\r
      }\r
    }\r
\r
    MicroSecondDelay (WAIT_PERIOD);\r
  }\r
\r
  return FALSE;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
SpiProtocolInfo (\r
  IN EFI_SPI_PROTOCOL     *This,\r
  OUT SPI_INIT_INFO      **InitInfoPtr\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Return info about SPI host controller, to help callers usage of Execute\r
  service.\r
\r
  If 0xff is returned as an opcode index in init info struct\r
  then device does not support the operation.\r
\r
Arguments:\r
\r
  This                    Pointer to the EFI_SPI_PROTOCOL instance.\r
  InitInfoPtr             Pointer to init info written to this memory location.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Information returned.\r
  EFI_INVALID_PARAMETER   Invalid parameter.\r
  EFI_NOT_READY           Required resources not setup.\r
  Others                  Unexpected error happened.\r
\r
--*/\r
{\r
  SPI_INSTANCE  *SpiInstance;\r
\r
  if (This == NULL || InitInfoPtr == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  SpiInstance       = SPI_INSTANCE_FROM_SPIPROTOCOL (This);\r
  if (SpiInstance->Signature != PCH_SPI_PRIVATE_DATA_SIGNATURE) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (!SpiInstance->InitDone) {\r
    *InitInfoPtr = NULL;\r
    return EFI_NOT_READY;\r
  }\r
  *InitInfoPtr = &SpiInstance->InitInfo;\r
  return EFI_SUCCESS;\r
}\r