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1/** @file\r
2 Main file for Pci shell Debug1 function.\r
3\r
4 Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r
5 Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>\r
6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "UefiShellDebug1CommandsLib.h"\r
17#include <Protocol/PciRootBridgeIo.h>\r
18#include <Library/ShellLib.h>\r
19#include <IndustryStandard/Pci.h>\r
20#include <IndustryStandard/Acpi.h>\r
21#include "Pci.h"\r
22\r
23#define PCI_CLASS_STRING_LIMIT 54\r
24//\r
25// Printable strings for Pci class code\r
26//\r
27typedef struct {\r
28 CHAR16 *BaseClass; // Pointer to the PCI base class string\r
29 CHAR16 *SubClass; // Pointer to the PCI sub class string\r
30 CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
31} PCI_CLASS_STRINGS;\r
32\r
33//\r
34// a structure holding a single entry, which also points to its lower level\r
35// class\r
36//\r
37typedef struct PCI_CLASS_ENTRY_TAG {\r
38 UINT8 Code; // Class, subclass or I/F code\r
39 CHAR16 *DescText; // Description string\r
40 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
41} PCI_CLASS_ENTRY;\r
42\r
43//\r
44// Declarations of entries which contain printable strings for class codes\r
45// in PCI configuration space\r
46//\r
47PCI_CLASS_ENTRY PCIBlankEntry[];\r
48PCI_CLASS_ENTRY PCISubClass_00[];\r
49PCI_CLASS_ENTRY PCISubClass_01[];\r
50PCI_CLASS_ENTRY PCISubClass_02[];\r
51PCI_CLASS_ENTRY PCISubClass_03[];\r
52PCI_CLASS_ENTRY PCISubClass_04[];\r
53PCI_CLASS_ENTRY PCISubClass_05[];\r
54PCI_CLASS_ENTRY PCISubClass_06[];\r
55PCI_CLASS_ENTRY PCISubClass_07[];\r
56PCI_CLASS_ENTRY PCISubClass_08[];\r
57PCI_CLASS_ENTRY PCISubClass_09[];\r
58PCI_CLASS_ENTRY PCISubClass_0a[];\r
59PCI_CLASS_ENTRY PCISubClass_0b[];\r
60PCI_CLASS_ENTRY PCISubClass_0c[];\r
61PCI_CLASS_ENTRY PCISubClass_0d[];\r
62PCI_CLASS_ENTRY PCISubClass_0e[];\r
63PCI_CLASS_ENTRY PCISubClass_0f[];\r
64PCI_CLASS_ENTRY PCISubClass_10[];\r
65PCI_CLASS_ENTRY PCISubClass_11[];\r
66PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
67PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
68PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
69PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
70PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
71PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
72PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
73PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
74PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
75PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
76PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
77PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
78PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
79PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
80\r
81//\r
82// Base class strings entries\r
83//\r
84PCI_CLASS_ENTRY gClassStringList[] = {\r
85 {\r
86 0x00,\r
87 L"Pre 2.0 device",\r
88 PCISubClass_00\r
89 },\r
90 {\r
91 0x01,\r
92 L"Mass Storage Controller",\r
93 PCISubClass_01\r
94 },\r
95 {\r
96 0x02,\r
97 L"Network Controller",\r
98 PCISubClass_02\r
99 },\r
100 {\r
101 0x03,\r
102 L"Display Controller",\r
103 PCISubClass_03\r
104 },\r
105 {\r
106 0x04,\r
107 L"Multimedia Device",\r
108 PCISubClass_04\r
109 },\r
110 {\r
111 0x05,\r
112 L"Memory Controller",\r
113 PCISubClass_05\r
114 },\r
115 {\r
116 0x06,\r
117 L"Bridge Device",\r
118 PCISubClass_06\r
119 },\r
120 {\r
121 0x07,\r
122 L"Simple Communications Controllers",\r
123 PCISubClass_07\r
124 },\r
125 {\r
126 0x08,\r
127 L"Base System Peripherals",\r
128 PCISubClass_08\r
129 },\r
130 {\r
131 0x09,\r
132 L"Input Devices",\r
133 PCISubClass_09\r
134 },\r
135 {\r
136 0x0a,\r
137 L"Docking Stations",\r
138 PCISubClass_0a\r
139 },\r
140 {\r
141 0x0b,\r
142 L"Processors",\r
143 PCISubClass_0b\r
144 },\r
145 {\r
146 0x0c,\r
147 L"Serial Bus Controllers",\r
148 PCISubClass_0c\r
149 },\r
150 {\r
151 0x0d,\r
152 L"Wireless Controllers",\r
153 PCISubClass_0d\r
154 },\r
155 {\r
156 0x0e,\r
157 L"Intelligent IO Controllers",\r
158 PCISubClass_0e\r
159 },\r
160 {\r
161 0x0f,\r
162 L"Satellite Communications Controllers",\r
163 PCISubClass_0f\r
164 },\r
165 {\r
166 0x10,\r
167 L"Encryption/Decryption Controllers",\r
168 PCISubClass_10\r
169 },\r
170 {\r
171 0x11,\r
172 L"Data Acquisition & Signal Processing Controllers",\r
173 PCISubClass_11\r
174 },\r
175 {\r
176 0xff,\r
177 L"Device does not fit in any defined classes",\r
178 PCIBlankEntry\r
179 },\r
180 {\r
181 0x00,\r
182 NULL,\r
183 /* null string ends the list */NULL\r
184 }\r
185};\r
186\r
187//\r
188// Subclass strings entries\r
189//\r
190PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
191 {\r
192 0x00,\r
193 L"",\r
194 PCIBlankEntry\r
195 },\r
196 {\r
197 0x00,\r
198 NULL,\r
199 /* null string ends the list */NULL\r
200 }\r
201};\r
202\r
203PCI_CLASS_ENTRY PCISubClass_00[] = {\r
204 {\r
205 0x00,\r
206 L"All devices other than VGA",\r
207 PCIBlankEntry\r
208 },\r
209 {\r
210 0x01,\r
211 L"VGA-compatible devices",\r
212 PCIBlankEntry\r
213 },\r
214 {\r
215 0x00,\r
216 NULL,\r
217 /* null string ends the list */NULL\r
218 }\r
219};\r
220\r
221PCI_CLASS_ENTRY PCISubClass_01[] = {\r
222 {\r
223 0x00,\r
224 L"SCSI controller",\r
225 PCIBlankEntry\r
226 },\r
227 {\r
228 0x01,\r
229 L"IDE controller",\r
230 PCIPIFClass_0101\r
231 },\r
232 {\r
233 0x02,\r
234 L"Floppy disk controller",\r
235 PCIBlankEntry\r
236 },\r
237 {\r
238 0x03,\r
239 L"IPI controller",\r
240 PCIBlankEntry\r
241 },\r
242 {\r
243 0x04,\r
244 L"RAID controller",\r
245 PCIBlankEntry\r
246 },\r
247 {\r
248 0x80,\r
249 L"Other mass storage controller",\r
250 PCIBlankEntry\r
251 },\r
252 {\r
253 0x00,\r
254 NULL,\r
255 /* null string ends the list */NULL\r
256 }\r
257};\r
258\r
259PCI_CLASS_ENTRY PCISubClass_02[] = {\r
260 {\r
261 0x00,\r
262 L"Ethernet controller",\r
263 PCIBlankEntry\r
264 },\r
265 {\r
266 0x01,\r
267 L"Token ring controller",\r
268 PCIBlankEntry\r
269 },\r
270 {\r
271 0x02,\r
272 L"FDDI controller",\r
273 PCIBlankEntry\r
274 },\r
275 {\r
276 0x03,\r
277 L"ATM controller",\r
278 PCIBlankEntry\r
279 },\r
280 {\r
281 0x04,\r
282 L"ISDN controller",\r
283 PCIBlankEntry\r
284 },\r
285 {\r
286 0x80,\r
287 L"Other network controller",\r
288 PCIBlankEntry\r
289 },\r
290 {\r
291 0x00,\r
292 NULL,\r
293 /* null string ends the list */NULL\r
294 }\r
295};\r
296\r
297PCI_CLASS_ENTRY PCISubClass_03[] = {\r
298 {\r
299 0x00,\r
300 L"VGA/8514 controller",\r
301 PCIPIFClass_0300\r
302 },\r
303 {\r
304 0x01,\r
305 L"XGA controller",\r
306 PCIBlankEntry\r
307 },\r
308 {\r
309 0x02,\r
310 L"3D controller",\r
311 PCIBlankEntry\r
312 },\r
313 {\r
314 0x80,\r
315 L"Other display controller",\r
316 PCIBlankEntry\r
317 },\r
318 {\r
319 0x00,\r
320 NULL,\r
321 /* null string ends the list */PCIBlankEntry\r
322 }\r
323};\r
324\r
325PCI_CLASS_ENTRY PCISubClass_04[] = {\r
326 {\r
327 0x00,\r
328 L"Video device",\r
329 PCIBlankEntry\r
330 },\r
331 {\r
332 0x01,\r
333 L"Audio device",\r
334 PCIBlankEntry\r
335 },\r
336 {\r
337 0x02,\r
338 L"Computer Telephony device",\r
339 PCIBlankEntry\r
340 },\r
341 {\r
342 0x80,\r
343 L"Other multimedia device",\r
344 PCIBlankEntry\r
345 },\r
346 {\r
347 0x00,\r
348 NULL,\r
349 /* null string ends the list */NULL\r
350 }\r
351};\r
352\r
353PCI_CLASS_ENTRY PCISubClass_05[] = {\r
354 {\r
355 0x00,\r
356 L"RAM memory controller",\r
357 PCIBlankEntry\r
358 },\r
359 {\r
360 0x01,\r
361 L"Flash memory controller",\r
362 PCIBlankEntry\r
363 },\r
364 {\r
365 0x80,\r
366 L"Other memory controller",\r
367 PCIBlankEntry\r
368 },\r
369 {\r
370 0x00,\r
371 NULL,\r
372 /* null string ends the list */NULL\r
373 }\r
374};\r
375\r
376PCI_CLASS_ENTRY PCISubClass_06[] = {\r
377 {\r
378 0x00,\r
379 L"Host/PCI bridge",\r
380 PCIBlankEntry\r
381 },\r
382 {\r
383 0x01,\r
384 L"PCI/ISA bridge",\r
385 PCIBlankEntry\r
386 },\r
387 {\r
388 0x02,\r
389 L"PCI/EISA bridge",\r
390 PCIBlankEntry\r
391 },\r
392 {\r
393 0x03,\r
394 L"PCI/Micro Channel bridge",\r
395 PCIBlankEntry\r
396 },\r
397 {\r
398 0x04,\r
399 L"PCI/PCI bridge",\r
400 PCIPIFClass_0604\r
401 },\r
402 {\r
403 0x05,\r
404 L"PCI/PCMCIA bridge",\r
405 PCIBlankEntry\r
406 },\r
407 {\r
408 0x06,\r
409 L"NuBus bridge",\r
410 PCIBlankEntry\r
411 },\r
412 {\r
413 0x07,\r
414 L"CardBus bridge",\r
415 PCIBlankEntry\r
416 },\r
417 {\r
418 0x08,\r
419 L"RACEway bridge",\r
420 PCIBlankEntry\r
421 },\r
422 {\r
423 0x80,\r
424 L"Other bridge type",\r
425 PCIBlankEntry\r
426 },\r
427 {\r
428 0x00,\r
429 NULL,\r
430 /* null string ends the list */NULL\r
431 }\r
432};\r
433\r
434PCI_CLASS_ENTRY PCISubClass_07[] = {\r
435 {\r
436 0x00,\r
437 L"Serial controller",\r
438 PCIPIFClass_0700\r
439 },\r
440 {\r
441 0x01,\r
442 L"Parallel port",\r
443 PCIPIFClass_0701\r
444 },\r
445 {\r
446 0x02,\r
447 L"Multiport serial controller",\r
448 PCIBlankEntry\r
449 },\r
450 {\r
451 0x03,\r
452 L"Modem",\r
453 PCIPIFClass_0703\r
454 },\r
455 {\r
456 0x80,\r
457 L"Other communication device",\r
458 PCIBlankEntry\r
459 },\r
460 {\r
461 0x00,\r
462 NULL,\r
463 /* null string ends the list */NULL\r
464 }\r
465};\r
466\r
467PCI_CLASS_ENTRY PCISubClass_08[] = {\r
468 {\r
469 0x00,\r
470 L"PIC",\r
471 PCIPIFClass_0800\r
472 },\r
473 {\r
474 0x01,\r
475 L"DMA controller",\r
476 PCIPIFClass_0801\r
477 },\r
478 {\r
479 0x02,\r
480 L"System timer",\r
481 PCIPIFClass_0802\r
482 },\r
483 {\r
484 0x03,\r
485 L"RTC controller",\r
486 PCIPIFClass_0803\r
487 },\r
488 {\r
489 0x04,\r
490 L"Generic PCI Hot-Plug controller",\r
491 PCIBlankEntry\r
492 },\r
493 {\r
494 0x80,\r
495 L"Other system peripheral",\r
496 PCIBlankEntry\r
497 },\r
498 {\r
499 0x00,\r
500 NULL,\r
501 /* null string ends the list */NULL\r
502 }\r
503};\r
504\r
505PCI_CLASS_ENTRY PCISubClass_09[] = {\r
506 {\r
507 0x00,\r
508 L"Keyboard controller",\r
509 PCIBlankEntry\r
510 },\r
511 {\r
512 0x01,\r
513 L"Digitizer (pen)",\r
514 PCIBlankEntry\r
515 },\r
516 {\r
517 0x02,\r
518 L"Mouse controller",\r
519 PCIBlankEntry\r
520 },\r
521 {\r
522 0x03,\r
523 L"Scanner controller",\r
524 PCIBlankEntry\r
525 },\r
526 {\r
527 0x04,\r
528 L"Gameport controller",\r
529 PCIPIFClass_0904\r
530 },\r
531 {\r
532 0x80,\r
533 L"Other input controller",\r
534 PCIBlankEntry\r
535 },\r
536 {\r
537 0x00,\r
538 NULL,\r
539 /* null string ends the list */NULL\r
540 }\r
541};\r
542\r
543PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
544 {\r
545 0x00,\r
546 L"Generic docking station",\r
547 PCIBlankEntry\r
548 },\r
549 {\r
550 0x80,\r
551 L"Other type of docking station",\r
552 PCIBlankEntry\r
553 },\r
554 {\r
555 0x00,\r
556 NULL,\r
557 /* null string ends the list */NULL\r
558 }\r
559};\r
560\r
561PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
562 {\r
563 0x00,\r
564 L"386",\r
565 PCIBlankEntry\r
566 },\r
567 {\r
568 0x01,\r
569 L"486",\r
570 PCIBlankEntry\r
571 },\r
572 {\r
573 0x02,\r
574 L"Pentium",\r
575 PCIBlankEntry\r
576 },\r
577 {\r
578 0x10,\r
579 L"Alpha",\r
580 PCIBlankEntry\r
581 },\r
582 {\r
583 0x20,\r
584 L"PowerPC",\r
585 PCIBlankEntry\r
586 },\r
587 {\r
588 0x30,\r
589 L"MIPS",\r
590 PCIBlankEntry\r
591 },\r
592 {\r
593 0x40,\r
594 L"Co-processor",\r
595 PCIBlankEntry\r
596 },\r
597 {\r
598 0x80,\r
599 L"Other processor",\r
600 PCIBlankEntry\r
601 },\r
602 {\r
603 0x00,\r
604 NULL,\r
605 /* null string ends the list */NULL\r
606 }\r
607};\r
608\r
609PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
610 {\r
611 0x00,\r
612 L"Firewire(IEEE 1394)",\r
613 PCIPIFClass_0c03\r
614 },\r
615 {\r
616 0x01,\r
617 L"ACCESS.bus",\r
618 PCIBlankEntry\r
619 },\r
620 {\r
621 0x02,\r
622 L"SSA",\r
623 PCIBlankEntry\r
624 },\r
625 {\r
626 0x03,\r
627 L"USB",\r
628 PCIPIFClass_0c00\r
629 },\r
630 {\r
631 0x04,\r
632 L"Fibre Channel",\r
633 PCIBlankEntry\r
634 },\r
635 {\r
636 0x05,\r
637 L"System Management Bus",\r
638 PCIBlankEntry\r
639 },\r
640 {\r
641 0x80,\r
642 L"Other bus type",\r
643 PCIBlankEntry\r
644 },\r
645 {\r
646 0x00,\r
647 NULL,\r
648 /* null string ends the list */NULL\r
649 }\r
650};\r
651\r
652PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
653 {\r
654 0x00,\r
655 L"iRDA compatible controller",\r
656 PCIBlankEntry\r
657 },\r
658 {\r
659 0x01,\r
660 L"Consumer IR controller",\r
661 PCIBlankEntry\r
662 },\r
663 {\r
664 0x10,\r
665 L"RF controller",\r
666 PCIBlankEntry\r
667 },\r
668 {\r
669 0x80,\r
670 L"Other type of wireless controller",\r
671 PCIBlankEntry\r
672 },\r
673 {\r
674 0x00,\r
675 NULL,\r
676 /* null string ends the list */NULL\r
677 }\r
678};\r
679\r
680PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
681 {\r
682 0x00,\r
683 L"I2O Architecture",\r
684 PCIPIFClass_0e00\r
685 },\r
686 {\r
687 0x00,\r
688 NULL,\r
689 /* null string ends the list */NULL\r
690 }\r
691};\r
692\r
693PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
694 {\r
695 0x00,\r
696 L"TV",\r
697 PCIBlankEntry\r
698 },\r
699 {\r
700 0x01,\r
701 L"Audio",\r
702 PCIBlankEntry\r
703 },\r
704 {\r
705 0x02,\r
706 L"Voice",\r
707 PCIBlankEntry\r
708 },\r
709 {\r
710 0x03,\r
711 L"Data",\r
712 PCIBlankEntry\r
713 },\r
714 {\r
715 0x00,\r
716 NULL,\r
717 /* null string ends the list */NULL\r
718 }\r
719};\r
720\r
721PCI_CLASS_ENTRY PCISubClass_10[] = {\r
722 {\r
723 0x00,\r
724 L"Network & computing Encrypt/Decrypt",\r
725 PCIBlankEntry\r
726 },\r
727 {\r
728 0x01,\r
729 L"Entertainment Encrypt/Decrypt",\r
730 PCIBlankEntry\r
731 },\r
732 {\r
733 0x80,\r
734 L"Other Encrypt/Decrypt",\r
735 PCIBlankEntry\r
736 },\r
737 {\r
738 0x00,\r
739 NULL,\r
740 /* null string ends the list */NULL\r
741 }\r
742};\r
743\r
744PCI_CLASS_ENTRY PCISubClass_11[] = {\r
745 {\r
746 0x00,\r
747 L"DPIO modules",\r
748 PCIBlankEntry\r
749 },\r
750 {\r
751 0x80,\r
752 L"Other DAQ & SP controllers",\r
753 PCIBlankEntry\r
754 },\r
755 {\r
756 0x00,\r
757 NULL,\r
758 /* null string ends the list */NULL\r
759 }\r
760};\r
761\r
762//\r
763// Programming Interface entries\r
764//\r
765PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
766 {\r
767 0x00,\r
768 L"",\r
769 PCIBlankEntry\r
770 },\r
771 {\r
772 0x01,\r
773 L"OM-primary",\r
774 PCIBlankEntry\r
775 },\r
776 {\r
777 0x02,\r
778 L"PI-primary",\r
779 PCIBlankEntry\r
780 },\r
781 {\r
782 0x03,\r
783 L"OM/PI-primary",\r
784 PCIBlankEntry\r
785 },\r
786 {\r
787 0x04,\r
788 L"OM-secondary",\r
789 PCIBlankEntry\r
790 },\r
791 {\r
792 0x05,\r
793 L"OM-primary, OM-secondary",\r
794 PCIBlankEntry\r
795 },\r
796 {\r
797 0x06,\r
798 L"PI-primary, OM-secondary",\r
799 PCIBlankEntry\r
800 },\r
801 {\r
802 0x07,\r
803 L"OM/PI-primary, OM-secondary",\r
804 PCIBlankEntry\r
805 },\r
806 {\r
807 0x08,\r
808 L"OM-secondary",\r
809 PCIBlankEntry\r
810 },\r
811 {\r
812 0x09,\r
813 L"OM-primary, PI-secondary",\r
814 PCIBlankEntry\r
815 },\r
816 {\r
817 0x0a,\r
818 L"PI-primary, PI-secondary",\r
819 PCIBlankEntry\r
820 },\r
821 {\r
822 0x0b,\r
823 L"OM/PI-primary, PI-secondary",\r
824 PCIBlankEntry\r
825 },\r
826 {\r
827 0x0c,\r
828 L"OM-secondary",\r
829 PCIBlankEntry\r
830 },\r
831 {\r
832 0x0d,\r
833 L"OM-primary, OM/PI-secondary",\r
834 PCIBlankEntry\r
835 },\r
836 {\r
837 0x0e,\r
838 L"PI-primary, OM/PI-secondary",\r
839 PCIBlankEntry\r
840 },\r
841 {\r
842 0x0f,\r
843 L"OM/PI-primary, OM/PI-secondary",\r
844 PCIBlankEntry\r
845 },\r
846 {\r
847 0x80,\r
848 L"Master",\r
849 PCIBlankEntry\r
850 },\r
851 {\r
852 0x81,\r
853 L"Master, OM-primary",\r
854 PCIBlankEntry\r
855 },\r
856 {\r
857 0x82,\r
858 L"Master, PI-primary",\r
859 PCIBlankEntry\r
860 },\r
861 {\r
862 0x83,\r
863 L"Master, OM/PI-primary",\r
864 PCIBlankEntry\r
865 },\r
866 {\r
867 0x84,\r
868 L"Master, OM-secondary",\r
869 PCIBlankEntry\r
870 },\r
871 {\r
872 0x85,\r
873 L"Master, OM-primary, OM-secondary",\r
874 PCIBlankEntry\r
875 },\r
876 {\r
877 0x86,\r
878 L"Master, PI-primary, OM-secondary",\r
879 PCIBlankEntry\r
880 },\r
881 {\r
882 0x87,\r
883 L"Master, OM/PI-primary, OM-secondary",\r
884 PCIBlankEntry\r
885 },\r
886 {\r
887 0x88,\r
888 L"Master, OM-secondary",\r
889 PCIBlankEntry\r
890 },\r
891 {\r
892 0x89,\r
893 L"Master, OM-primary, PI-secondary",\r
894 PCIBlankEntry\r
895 },\r
896 {\r
897 0x8a,\r
898 L"Master, PI-primary, PI-secondary",\r
899 PCIBlankEntry\r
900 },\r
901 {\r
902 0x8b,\r
903 L"Master, OM/PI-primary, PI-secondary",\r
904 PCIBlankEntry\r
905 },\r
906 {\r
907 0x8c,\r
908 L"Master, OM-secondary",\r
909 PCIBlankEntry\r
910 },\r
911 {\r
912 0x8d,\r
913 L"Master, OM-primary, OM/PI-secondary",\r
914 PCIBlankEntry\r
915 },\r
916 {\r
917 0x8e,\r
918 L"Master, PI-primary, OM/PI-secondary",\r
919 PCIBlankEntry\r
920 },\r
921 {\r
922 0x8f,\r
923 L"Master, OM/PI-primary, OM/PI-secondary",\r
924 PCIBlankEntry\r
925 },\r
926 {\r
927 0x00,\r
928 NULL,\r
929 /* null string ends the list */NULL\r
930 }\r
931};\r
932\r
933PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
934 {\r
935 0x00,\r
936 L"VGA compatible",\r
937 PCIBlankEntry\r
938 },\r
939 {\r
940 0x01,\r
941 L"8514 compatible",\r
942 PCIBlankEntry\r
943 },\r
944 {\r
945 0x00,\r
946 NULL,\r
947 /* null string ends the list */NULL\r
948 }\r
949};\r
950\r
951PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
952 {\r
953 0x00,\r
954 L"",\r
955 PCIBlankEntry\r
956 },\r
957 {\r
958 0x01,\r
959 L"Subtractive decode",\r
960 PCIBlankEntry\r
961 },\r
962 {\r
963 0x00,\r
964 NULL,\r
965 /* null string ends the list */NULL\r
966 }\r
967};\r
968\r
969PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
970 {\r
971 0x00,\r
972 L"Generic XT-compatible",\r
973 PCIBlankEntry\r
974 },\r
975 {\r
976 0x01,\r
977 L"16450-compatible",\r
978 PCIBlankEntry\r
979 },\r
980 {\r
981 0x02,\r
982 L"16550-compatible",\r
983 PCIBlankEntry\r
984 },\r
985 {\r
986 0x03,\r
987 L"16650-compatible",\r
988 PCIBlankEntry\r
989 },\r
990 {\r
991 0x04,\r
992 L"16750-compatible",\r
993 PCIBlankEntry\r
994 },\r
995 {\r
996 0x05,\r
997 L"16850-compatible",\r
998 PCIBlankEntry\r
999 },\r
1000 {\r
1001 0x06,\r
1002 L"16950-compatible",\r
1003 PCIBlankEntry\r
1004 },\r
1005 {\r
1006 0x00,\r
1007 NULL,\r
1008 /* null string ends the list */NULL\r
1009 }\r
1010};\r
1011\r
1012PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
1013 {\r
1014 0x00,\r
1015 L"",\r
1016 PCIBlankEntry\r
1017 },\r
1018 {\r
1019 0x01,\r
1020 L"Bi-directional",\r
1021 PCIBlankEntry\r
1022 },\r
1023 {\r
1024 0x02,\r
1025 L"ECP 1.X-compliant",\r
1026 PCIBlankEntry\r
1027 },\r
1028 {\r
1029 0x03,\r
1030 L"IEEE 1284",\r
1031 PCIBlankEntry\r
1032 },\r
1033 {\r
1034 0xfe,\r
1035 L"IEEE 1284 target (not a controller)",\r
1036 PCIBlankEntry\r
1037 },\r
1038 {\r
1039 0x00,\r
1040 NULL,\r
1041 /* null string ends the list */NULL\r
1042 }\r
1043};\r
1044\r
1045PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
1046 {\r
1047 0x00,\r
1048 L"Generic",\r
1049 PCIBlankEntry\r
1050 },\r
1051 {\r
1052 0x01,\r
1053 L"Hayes-compatible 16450",\r
1054 PCIBlankEntry\r
1055 },\r
1056 {\r
1057 0x02,\r
1058 L"Hayes-compatible 16550",\r
1059 PCIBlankEntry\r
1060 },\r
1061 {\r
1062 0x03,\r
1063 L"Hayes-compatible 16650",\r
1064 PCIBlankEntry\r
1065 },\r
1066 {\r
1067 0x04,\r
1068 L"Hayes-compatible 16750",\r
1069 PCIBlankEntry\r
1070 },\r
1071 {\r
1072 0x00,\r
1073 NULL,\r
1074 /* null string ends the list */NULL\r
1075 }\r
1076};\r
1077\r
1078PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
1079 {\r
1080 0x00,\r
1081 L"Generic 8259",\r
1082 PCIBlankEntry\r
1083 },\r
1084 {\r
1085 0x01,\r
1086 L"ISA",\r
1087 PCIBlankEntry\r
1088 },\r
1089 {\r
1090 0x02,\r
1091 L"EISA",\r
1092 PCIBlankEntry\r
1093 },\r
1094 {\r
1095 0x10,\r
1096 L"IO APIC",\r
1097 PCIBlankEntry\r
1098 },\r
1099 {\r
1100 0x20,\r
1101 L"IO(x) APIC interrupt controller",\r
1102 PCIBlankEntry\r
1103 },\r
1104 {\r
1105 0x00,\r
1106 NULL,\r
1107 /* null string ends the list */NULL\r
1108 }\r
1109};\r
1110\r
1111PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
1112 {\r
1113 0x00,\r
1114 L"Generic 8237",\r
1115 PCIBlankEntry\r
1116 },\r
1117 {\r
1118 0x01,\r
1119 L"ISA",\r
1120 PCIBlankEntry\r
1121 },\r
1122 {\r
1123 0x02,\r
1124 L"EISA",\r
1125 PCIBlankEntry\r
1126 },\r
1127 {\r
1128 0x00,\r
1129 NULL,\r
1130 /* null string ends the list */NULL\r
1131 }\r
1132};\r
1133\r
1134PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
1135 {\r
1136 0x00,\r
1137 L"Generic 8254",\r
1138 PCIBlankEntry\r
1139 },\r
1140 {\r
1141 0x01,\r
1142 L"ISA",\r
1143 PCIBlankEntry\r
1144 },\r
1145 {\r
1146 0x02,\r
1147 L"EISA",\r
1148 PCIBlankEntry\r
1149 },\r
1150 {\r
1151 0x00,\r
1152 NULL,\r
1153 /* null string ends the list */NULL\r
1154 }\r
1155};\r
1156\r
1157PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
1158 {\r
1159 0x00,\r
1160 L"Generic",\r
1161 PCIBlankEntry\r
1162 },\r
1163 {\r
1164 0x01,\r
1165 L"ISA",\r
1166 PCIBlankEntry\r
1167 },\r
1168 {\r
1169 0x02,\r
1170 L"EISA",\r
1171 PCIBlankEntry\r
1172 },\r
1173 {\r
1174 0x00,\r
1175 NULL,\r
1176 /* null string ends the list */NULL\r
1177 }\r
1178};\r
1179\r
1180PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
1181 {\r
1182 0x00,\r
1183 L"Generic",\r
1184 PCIBlankEntry\r
1185 },\r
1186 {\r
1187 0x10,\r
1188 L"",\r
1189 PCIBlankEntry\r
1190 },\r
1191 {\r
1192 0x00,\r
1193 NULL,\r
1194 /* null string ends the list */NULL\r
1195 }\r
1196};\r
1197\r
1198PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
1199 {\r
1200 0x00,\r
1201 L"Universal Host Controller spec",\r
1202 PCIBlankEntry\r
1203 },\r
1204 {\r
1205 0x10,\r
1206 L"Open Host Controller spec",\r
1207 PCIBlankEntry\r
1208 },\r
1209 {\r
1210 0x80,\r
1211 L"No specific programming interface",\r
1212 PCIBlankEntry\r
1213 },\r
1214 {\r
1215 0xfe,\r
1216 L"(Not Host Controller)",\r
1217 PCIBlankEntry\r
1218 },\r
1219 {\r
1220 0x00,\r
1221 NULL,\r
1222 /* null string ends the list */NULL\r
1223 }\r
1224};\r
1225\r
1226PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
1227 {\r
1228 0x00,\r
1229 L"",\r
1230 PCIBlankEntry\r
1231 },\r
1232 {\r
1233 0x10,\r
1234 L"Using 1394 OpenHCI spec",\r
1235 PCIBlankEntry\r
1236 },\r
1237 {\r
1238 0x00,\r
1239 NULL,\r
1240 /* null string ends the list */NULL\r
1241 }\r
1242};\r
1243\r
1244PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
1245 {\r
1246 0x00,\r
1247 L"Message FIFO at offset 40h",\r
1248 PCIBlankEntry\r
1249 },\r
1250 {\r
1251 0x01,\r
1252 L"",\r
1253 PCIBlankEntry\r
1254 },\r
1255 {\r
1256 0x00,\r
1257 NULL,\r
1258 /* null string ends the list */NULL\r
1259 }\r
1260};\r
1261\r
1262\r
1263/**\r
1264 Generates printable Unicode strings that represent PCI device class,\r
1265 subclass and programmed I/F based on a value passed to the function.\r
1266\r
1267 @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r
1268 PCI device. The encodings are:\r
1269 bits 23:16 - Base Class Code\r
1270 bits 15:8 - Sub-Class Code\r
1271 bits 7:0 - Programming Interface\r
1272 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
1273 printable class strings corresponding to ClassCode. The\r
1274 caller must not modify the strings that are pointed by\r
1275 the fields in ClassStrings.\r
1276**/\r
1277VOID\r
1278PciGetClassStrings (\r
1279 IN UINT32 ClassCode,\r
1280 IN OUT PCI_CLASS_STRINGS *ClassStrings\r
1281 )\r
1282{\r
1283 INTN Index;\r
1284 UINT8 Code;\r
1285 PCI_CLASS_ENTRY *CurrentClass;\r
1286\r
1287 //\r
1288 // Assume no strings found\r
1289 //\r
1290 ClassStrings->BaseClass = L"UNDEFINED";\r
1291 ClassStrings->SubClass = L"UNDEFINED";\r
1292 ClassStrings->PIFClass = L"UNDEFINED";\r
1293\r
1294 CurrentClass = gClassStringList;\r
1295 Code = (UINT8) (ClassCode >> 16);\r
1296 Index = 0;\r
1297\r
1298 //\r
1299 // Go through all entries of the base class, until the entry with a matching\r
1300 // base class code is found. If reaches an entry with a null description\r
1301 // text, the last entry is met, which means no text for the base class was\r
1302 // found, so no more action is needed.\r
1303 //\r
1304 while (Code != CurrentClass[Index].Code) {\r
1305 if (NULL == CurrentClass[Index].DescText) {\r
1306 return ;\r
1307 }\r
1308\r
1309 Index++;\r
1310 }\r
1311 //\r
1312 // A base class was found. Assign description, and check if this class has\r
1313 // sub-class defined. If sub-class defined, no more action is needed,\r
1314 // otherwise, continue to find description for the sub-class code.\r
1315 //\r
1316 ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
1317 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1318 return ;\r
1319 }\r
1320 //\r
1321 // find Subclass entry\r
1322 //\r
1323 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1324 Code = (UINT8) (ClassCode >> 8);\r
1325 Index = 0;\r
1326\r
1327 //\r
1328 // Go through all entries of the sub-class, until the entry with a matching\r
1329 // sub-class code is found. If reaches an entry with a null description\r
1330 // text, the last entry is met, which means no text for the sub-class was\r
1331 // found, so no more action is needed.\r
1332 //\r
1333 while (Code != CurrentClass[Index].Code) {\r
1334 if (NULL == CurrentClass[Index].DescText) {\r
1335 return ;\r
1336 }\r
1337\r
1338 Index++;\r
1339 }\r
1340 //\r
1341 // A class was found for the sub-class code. Assign description, and check if\r
1342 // this sub-class has programming interface defined. If no, no more action is\r
1343 // needed, otherwise, continue to find description for the programming\r
1344 // interface.\r
1345 //\r
1346 ClassStrings->SubClass = CurrentClass[Index].DescText;\r
1347 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1348 return ;\r
1349 }\r
1350 //\r
1351 // Find programming interface entry\r
1352 //\r
1353 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1354 Code = (UINT8) ClassCode;\r
1355 Index = 0;\r
1356\r
1357 //\r
1358 // Go through all entries of the I/F entries, until the entry with a\r
1359 // matching I/F code is found. If reaches an entry with a null description\r
1360 // text, the last entry is met, which means no text was found, so no more\r
1361 // action is needed.\r
1362 //\r
1363 while (Code != CurrentClass[Index].Code) {\r
1364 if (NULL == CurrentClass[Index].DescText) {\r
1365 return ;\r
1366 }\r
1367\r
1368 Index++;\r
1369 }\r
1370 //\r
1371 // A class was found for the I/F code. Assign description, done!\r
1372 //\r
1373 ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
1374 return ;\r
1375}\r
1376\r
1377/**\r
1378 Print strings that represent PCI device class, subclass and programmed I/F.\r
1379\r
1380 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
1381 configuation space.\r
1382 @param[in] IncludePIF If the printed string should include the programming I/F part\r
1383**/\r
1384VOID\r
1385PciPrintClassCode (\r
1386 IN UINT8 *ClassCodePtr,\r
1387 IN BOOLEAN IncludePIF\r
1388 )\r
1389{\r
1390 UINT32 ClassCode;\r
1391 PCI_CLASS_STRINGS ClassStrings;\r
1392\r
1393 ClassCode = 0;\r
1394 ClassCode |= ClassCodePtr[0];\r
1395 ClassCode |= (ClassCodePtr[1] << 8);\r
1396 ClassCode |= (ClassCodePtr[2] << 16);\r
1397\r
1398 //\r
1399 // Get name from class code\r
1400 //\r
1401 PciGetClassStrings (ClassCode, &ClassStrings);\r
1402\r
1403 if (IncludePIF) {\r
1404 //\r
1405 // Print base class, sub class, and programming inferface name\r
1406 //\r
1407 ShellPrintEx (-1, -1, L"%s - %s - %s",\r
1408 ClassStrings.BaseClass,\r
1409 ClassStrings.SubClass,\r
1410 ClassStrings.PIFClass\r
1411 );\r
1412\r
1413 } else {\r
1414 //\r
1415 // Only print base class and sub class name\r
1416 //\r
1417 ShellPrintEx (-1, -1, L"%s - %s",\r
1418 ClassStrings.BaseClass,\r
1419 ClassStrings.SubClass\r
1420 );\r
1421 }\r
1422}\r
1423\r
1424/**\r
1425 This function finds out the protocol which is in charge of the given\r
1426 segment, and its bus range covers the current bus number. It lookes\r
1427 each instances of RootBridgeIoProtocol handle, until the one meets the\r
1428 criteria is found.\r
1429\r
1430 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1431 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1432 @param[in] Segment Segment number of device we are dealing with.\r
1433 @param[in] Bus Bus number of device we are dealing with.\r
1434 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1435\r
1436 @retval EFI_SUCCESS The command completed successfully.\r
1437 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
1438\r
1439**/\r
1440EFI_STATUS\r
1441PciFindProtocolInterface (\r
1442 IN EFI_HANDLE *HandleBuf,\r
1443 IN UINTN HandleCount,\r
1444 IN UINT16 Segment,\r
1445 IN UINT16 Bus,\r
1446 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
1447 );\r
1448\r
1449/**\r
1450 This function gets the protocol interface from the given handle, and\r
1451 obtains its address space descriptors.\r
1452\r
1453 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
1454 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1455 @param[out] Descriptors Points to the address space descriptors.\r
1456\r
1457 @retval EFI_SUCCESS The command completed successfully\r
1458**/\r
1459EFI_STATUS\r
1460PciGetProtocolAndResource (\r
1461 IN EFI_HANDLE Handle,\r
1462 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
1463 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
1464 );\r
1465\r
1466/**\r
1467 This function get the next bus range of given address space descriptors.\r
1468 It also moves the pointer backward a node, to get prepared to be called\r
1469 again.\r
1470\r
1471 @param[in, out] Descriptors Points to current position of a serial of address space\r
1472 descriptors.\r
1473 @param[out] MinBus The lower range of bus number.\r
1474 @param[out] MaxBus The upper range of bus number.\r
1475 @param[out] IsEnd Meet end of the serial of descriptors.\r
1476\r
1477 @retval EFI_SUCCESS The command completed successfully.\r
1478**/\r
1479EFI_STATUS\r
1480PciGetNextBusRange (\r
1481 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
1482 OUT UINT16 *MinBus,\r
1483 OUT UINT16 *MaxBus,\r
1484 OUT BOOLEAN *IsEnd\r
1485 );\r
1486\r
1487/**\r
1488 Explain the data in PCI configuration space. The part which is common for\r
1489 PCI device and bridge is interpreted in this function. It calls other\r
1490 functions to interpret data unique for device or bridge.\r
1491\r
1492 @param[in] ConfigSpace Data in PCI configuration space.\r
1493 @param[in] Address Address used to access configuration space of this PCI device.\r
1494 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1495\r
1496 @retval EFI_SUCCESS The command completed successfully.\r
1497**/\r
1498EFI_STATUS\r
1499PciExplainData (\r
1500 IN PCI_CONFIG_SPACE *ConfigSpace,\r
1501 IN UINT64 Address,\r
1502 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1503 );\r
1504\r
1505/**\r
1506 Explain the device specific part of data in PCI configuration space.\r
1507\r
1508 @param[in] Device Data in PCI configuration space.\r
1509 @param[in] Address Address used to access configuration space of this PCI device.\r
1510 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1511\r
1512 @retval EFI_SUCCESS The command completed successfully.\r
1513**/\r
1514EFI_STATUS\r
1515PciExplainDeviceData (\r
1516 IN PCI_DEVICE_HEADER *Device,\r
1517 IN UINT64 Address,\r
1518 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1519 );\r
1520\r
1521/**\r
1522 Explain the bridge specific part of data in PCI configuration space.\r
1523\r
1524 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
1525 @param[in] Address Address used to access configuration space of this PCI device.\r
1526 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1527\r
1528 @retval EFI_SUCCESS The command completed successfully.\r
1529**/\r
1530EFI_STATUS\r
1531PciExplainBridgeData (\r
1532 IN PCI_BRIDGE_HEADER *Bridge,\r
1533 IN UINT64 Address,\r
1534 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1535 );\r
1536\r
1537/**\r
1538 Explain the Base Address Register(Bar) in PCI configuration space.\r
1539\r
1540 @param[in] Bar Points to the Base Address Register intended to interpret.\r
1541 @param[in] Command Points to the register Command.\r
1542 @param[in] Address Address used to access configuration space of this PCI device.\r
1543 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1544 @param[in, out] Index The Index.\r
1545\r
1546 @retval EFI_SUCCESS The command completed successfully.\r
1547**/\r
1548EFI_STATUS\r
1549PciExplainBar (\r
1550 IN UINT32 *Bar,\r
1551 IN UINT16 *Command,\r
1552 IN UINT64 Address,\r
1553 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1554 IN OUT UINTN *Index\r
1555 );\r
1556\r
1557/**\r
1558 Explain the cardbus specific part of data in PCI configuration space.\r
1559\r
1560 @param[in] CardBus CardBus specific region of PCI configuration space.\r
1561 @param[in] Address Address used to access configuration space of this PCI device.\r
1562 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1563\r
1564 @retval EFI_SUCCESS The command completed successfully.\r
1565**/\r
1566EFI_STATUS\r
1567PciExplainCardBusData (\r
1568 IN PCI_CARDBUS_HEADER *CardBus,\r
1569 IN UINT64 Address,\r
1570 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1571 );\r
1572\r
1573/**\r
1574 Explain each meaningful bit of register Status. The definition of Status is\r
1575 slightly different depending on the PCI header type.\r
1576\r
1577 @param[in] Status Points to the content of register Status.\r
1578 @param[in] MainStatus Indicates if this register is main status(not secondary\r
1579 status).\r
1580 @param[in] HeaderType Header type of this PCI device.\r
1581\r
1582 @retval EFI_SUCCESS The command completed successfully.\r
1583**/\r
1584EFI_STATUS\r
1585PciExplainStatus (\r
1586 IN UINT16 *Status,\r
1587 IN BOOLEAN MainStatus,\r
1588 IN PCI_HEADER_TYPE HeaderType\r
1589 );\r
1590\r
1591/**\r
1592 Explain each meaningful bit of register Command.\r
1593\r
1594 @param[in] Command Points to the content of register Command.\r
1595\r
1596 @retval EFI_SUCCESS The command completed successfully.\r
1597**/\r
1598EFI_STATUS\r
1599PciExplainCommand (\r
1600 IN UINT16 *Command\r
1601 );\r
1602\r
1603/**\r
1604 Explain each meaningful bit of register Bridge Control.\r
1605\r
1606 @param[in] BridgeControl Points to the content of register Bridge Control.\r
1607 @param[in] HeaderType The headertype.\r
1608\r
1609 @retval EFI_SUCCESS The command completed successfully.\r
1610**/\r
1611EFI_STATUS\r
1612PciExplainBridgeControl (\r
1613 IN UINT16 *BridgeControl,\r
1614 IN PCI_HEADER_TYPE HeaderType\r
1615 );\r
1616\r
1617/**\r
1618 Print each capability structure.\r
1619\r
1620 @param[in] IoDev The pointer to the deivce.\r
1621 @param[in] Address The address to start at.\r
1622 @param[in] CapPtr The offset from the address.\r
1623\r
1624 @retval EFI_SUCCESS The operation was successful.\r
1625**/\r
1626EFI_STATUS\r
1627PciExplainCapabilityStruct (\r
1628 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1629 IN UINT64 Address,\r
1630 IN UINT8 CapPtr\r
1631 );\r
1632\r
1633/**\r
1634 Display Pcie device structure.\r
1635\r
1636 @param[in] IoDev The pointer to the root pci protocol.\r
1637 @param[in] Address The Address to start at.\r
1638 @param[in] CapabilityPtr The offset from the address to start.\r
1639**/\r
1640EFI_STATUS\r
1641PciExplainPciExpress (\r
1642 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1643 IN UINT64 Address,\r
1644 IN UINT8 CapabilityPtr\r
1645 );\r
1646\r
1647/**\r
1648 Print out information of the capability information.\r
1649\r
1650 @param[in] PciExpressCap The pointer to the structure about the device.\r
1651\r
1652 @retval EFI_SUCCESS The operation was successful.\r
1653**/\r
1654EFI_STATUS\r
1655ExplainPcieCapReg (\r
1656 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1657 );\r
1658\r
1659/**\r
1660 Print out information of the device capability information.\r
1661\r
1662 @param[in] PciExpressCap The pointer to the structure about the device.\r
1663\r
1664 @retval EFI_SUCCESS The operation was successful.\r
1665**/\r
1666EFI_STATUS\r
1667ExplainPcieDeviceCap (\r
1668 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1669 );\r
1670\r
1671/**\r
1672 Print out information of the device control information.\r
1673\r
1674 @param[in] PciExpressCap The pointer to the structure about the device.\r
1675\r
1676 @retval EFI_SUCCESS The operation was successful.\r
1677**/\r
1678EFI_STATUS\r
1679ExplainPcieDeviceControl (\r
1680 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1681 );\r
1682\r
1683/**\r
1684 Print out information of the device status information.\r
1685\r
1686 @param[in] PciExpressCap The pointer to the structure about the device.\r
1687\r
1688 @retval EFI_SUCCESS The operation was successful.\r
1689**/\r
1690EFI_STATUS\r
1691ExplainPcieDeviceStatus (\r
1692 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1693 );\r
1694\r
1695/**\r
1696 Print out information of the device link information.\r
1697\r
1698 @param[in] PciExpressCap The pointer to the structure about the device.\r
1699\r
1700 @retval EFI_SUCCESS The operation was successful.\r
1701**/\r
1702EFI_STATUS\r
1703ExplainPcieLinkCap (\r
1704 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1705 );\r
1706\r
1707/**\r
1708 Print out information of the device link control information.\r
1709\r
1710 @param[in] PciExpressCap The pointer to the structure about the device.\r
1711\r
1712 @retval EFI_SUCCESS The operation was successful.\r
1713**/\r
1714EFI_STATUS\r
1715ExplainPcieLinkControl (\r
1716 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1717 );\r
1718\r
1719/**\r
1720 Print out information of the device link status information.\r
1721\r
1722 @param[in] PciExpressCap The pointer to the structure about the device.\r
1723\r
1724 @retval EFI_SUCCESS The operation was successful.\r
1725**/\r
1726EFI_STATUS\r
1727ExplainPcieLinkStatus (\r
1728 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1729 );\r
1730\r
1731/**\r
1732 Print out information of the device slot information.\r
1733\r
1734 @param[in] PciExpressCap The pointer to the structure about the device.\r
1735\r
1736 @retval EFI_SUCCESS The operation was successful.\r
1737**/\r
1738EFI_STATUS\r
1739ExplainPcieSlotCap (\r
1740 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1741 );\r
1742\r
1743/**\r
1744 Print out information of the device slot control information.\r
1745\r
1746 @param[in] PciExpressCap The pointer to the structure about the device.\r
1747\r
1748 @retval EFI_SUCCESS The operation was successful.\r
1749**/\r
1750EFI_STATUS\r
1751ExplainPcieSlotControl (\r
1752 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1753 );\r
1754\r
1755/**\r
1756 Print out information of the device slot status information.\r
1757\r
1758 @param[in] PciExpressCap The pointer to the structure about the device.\r
1759\r
1760 @retval EFI_SUCCESS The operation was successful.\r
1761**/\r
1762EFI_STATUS\r
1763ExplainPcieSlotStatus (\r
1764 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1765 );\r
1766\r
1767/**\r
1768 Print out information of the device root information.\r
1769\r
1770 @param[in] PciExpressCap The pointer to the structure about the device.\r
1771\r
1772 @retval EFI_SUCCESS The operation was successful.\r
1773**/\r
1774EFI_STATUS\r
1775ExplainPcieRootControl (\r
1776 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1777 );\r
1778\r
1779/**\r
1780 Print out information of the device root capability information.\r
1781\r
1782 @param[in] PciExpressCap The pointer to the structure about the device.\r
1783\r
1784 @retval EFI_SUCCESS The operation was successful.\r
1785**/\r
1786EFI_STATUS\r
1787ExplainPcieRootCap (\r
1788 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1789 );\r
1790\r
1791/**\r
1792 Print out information of the device root status information.\r
1793\r
1794 @param[in] PciExpressCap The pointer to the structure about the device.\r
1795\r
1796 @retval EFI_SUCCESS The operation was successful.\r
1797**/\r
1798EFI_STATUS\r
1799ExplainPcieRootStatus (\r
1800 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1801 );\r
1802\r
1803typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
1804\r
1805typedef enum {\r
1806 FieldWidthUINT8,\r
1807 FieldWidthUINT16,\r
1808 FieldWidthUINT32\r
1809} PCIE_CAPREG_FIELD_WIDTH;\r
1810\r
1811typedef enum {\r
1812 PcieExplainTypeCommon,\r
1813 PcieExplainTypeDevice,\r
1814 PcieExplainTypeLink,\r
1815 PcieExplainTypeSlot,\r
1816 PcieExplainTypeRoot,\r
1817 PcieExplainTypeMax\r
1818} PCIE_EXPLAIN_TYPE;\r
1819\r
1820typedef struct\r
1821{\r
1822 UINT16 Token;\r
1823 UINTN Offset;\r
1824 PCIE_CAPREG_FIELD_WIDTH Width;\r
1825 PCIE_EXPLAIN_FUNCTION Func;\r
1826 PCIE_EXPLAIN_TYPE Type;\r
1827} PCIE_EXPLAIN_STRUCT;\r
1828\r
1829PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
1830 {\r
1831 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
1832 0x00,\r
1833 FieldWidthUINT8,\r
1834 NULL,\r
1835 PcieExplainTypeCommon\r
1836 },\r
1837 {\r
1838 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r
1839 0x01,\r
1840 FieldWidthUINT8,\r
1841 NULL,\r
1842 PcieExplainTypeCommon\r
1843 },\r
1844 {\r
1845 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r
1846 0x02,\r
1847 FieldWidthUINT16,\r
1848 ExplainPcieCapReg,\r
1849 PcieExplainTypeCommon\r
1850 },\r
1851 {\r
1852 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r
1853 0x04,\r
1854 FieldWidthUINT32,\r
1855 ExplainPcieDeviceCap,\r
1856 PcieExplainTypeDevice\r
1857 },\r
1858 {\r
1859 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r
1860 0x08,\r
1861 FieldWidthUINT16,\r
1862 ExplainPcieDeviceControl,\r
1863 PcieExplainTypeDevice\r
1864 },\r
1865 {\r
1866 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r
1867 0x0a,\r
1868 FieldWidthUINT16,\r
1869 ExplainPcieDeviceStatus,\r
1870 PcieExplainTypeDevice\r
1871 },\r
1872 {\r
1873 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r
1874 0x0c,\r
1875 FieldWidthUINT32,\r
1876 ExplainPcieLinkCap,\r
1877 PcieExplainTypeLink\r
1878 },\r
1879 {\r
1880 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r
1881 0x10,\r
1882 FieldWidthUINT16,\r
1883 ExplainPcieLinkControl,\r
1884 PcieExplainTypeLink\r
1885 },\r
1886 {\r
1887 STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r
1888 0x12,\r
1889 FieldWidthUINT16,\r
1890 ExplainPcieLinkStatus,\r
1891 PcieExplainTypeLink\r
1892 },\r
1893 {\r
1894 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r
1895 0x14,\r
1896 FieldWidthUINT32,\r
1897 ExplainPcieSlotCap,\r
1898 PcieExplainTypeSlot\r
1899 },\r
1900 {\r
1901 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r
1902 0x18,\r
1903 FieldWidthUINT16,\r
1904 ExplainPcieSlotControl,\r
1905 PcieExplainTypeSlot\r
1906 },\r
1907 {\r
1908 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r
1909 0x1a,\r
1910 FieldWidthUINT16,\r
1911 ExplainPcieSlotStatus,\r
1912 PcieExplainTypeSlot\r
1913 },\r
1914 {\r
1915 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r
1916 0x1c,\r
1917 FieldWidthUINT16,\r
1918 ExplainPcieRootControl,\r
1919 PcieExplainTypeRoot\r
1920 },\r
1921 {\r
1922 STRING_TOKEN (STR_PCIEX_RSVDP),\r
1923 0x1e,\r
1924 FieldWidthUINT16,\r
1925 ExplainPcieRootCap,\r
1926 PcieExplainTypeRoot\r
1927 },\r
1928 {\r
1929 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r
1930 0x20,\r
1931 FieldWidthUINT32,\r
1932 ExplainPcieRootStatus,\r
1933 PcieExplainTypeRoot\r
1934 },\r
1935 {\r
1936 0,\r
1937 0,\r
1938 (PCIE_CAPREG_FIELD_WIDTH)0,\r
1939 NULL,\r
1940 PcieExplainTypeMax\r
1941 }\r
1942};\r
1943\r
1944//\r
1945// Global Variables\r
1946//\r
1947PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
1948STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
1949 {L"-s", TypeValue},\r
1950 {L"-i", TypeFlag},\r
1951 {NULL, TypeMax}\r
1952 };\r
1953\r
1954CHAR16 *DevicePortTypeTable[] = {\r
1955 L"PCI Express Endpoint",\r
1956 L"Legacy PCI Express Endpoint",\r
1957 L"Unknown Type",\r
1958 L"Unknonw Type",\r
1959 L"Root Port of PCI Express Root Complex",\r
1960 L"Upstream Port of PCI Express Switch",\r
1961 L"Downstream Port of PCI Express Switch",\r
1962 L"PCI Express to PCI/PCI-X Bridge",\r
1963 L"PCI/PCI-X to PCI Express Bridge",\r
1964 L"Root Complex Integrated Endpoint",\r
1965 L"Root Complex Event Collector"\r
1966};\r
1967\r
1968CHAR16 *L0sLatencyStrTable[] = {\r
1969 L"Less than 64ns",\r
1970 L"64ns to less than 128ns",\r
1971 L"128ns to less than 256ns",\r
1972 L"256ns to less than 512ns",\r
1973 L"512ns to less than 1us",\r
1974 L"1us to less than 2us",\r
1975 L"2us-4us",\r
1976 L"More than 4us"\r
1977};\r
1978\r
1979CHAR16 *L1LatencyStrTable[] = {\r
1980 L"Less than 1us",\r
1981 L"1us to less than 2us",\r
1982 L"2us to less than 4us",\r
1983 L"4us to less than 8us",\r
1984 L"8us to less than 16us",\r
1985 L"16us to less than 32us",\r
1986 L"32us-64us",\r
1987 L"More than 64us"\r
1988};\r
1989\r
1990CHAR16 *ASPMCtrlStrTable[] = {\r
1991 L"Disabled",\r
1992 L"L0s Entry Enabled",\r
1993 L"L1 Entry Enabled",\r
1994 L"L0s and L1 Entry Enabled"\r
1995};\r
1996\r
1997CHAR16 *SlotPwrLmtScaleTable[] = {\r
1998 L"1.0x",\r
1999 L"0.1x",\r
2000 L"0.01x",\r
2001 L"0.001x"\r
2002};\r
2003\r
2004CHAR16 *IndicatorTable[] = {\r
2005 L"Reserved",\r
2006 L"On",\r
2007 L"Blink",\r
2008 L"Off"\r
2009};\r
2010\r
2011\r
2012/**\r
2013 Function for 'pci' command.\r
2014\r
2015 @param[in] ImageHandle Handle to the Image (NULL if Internal).\r
2016 @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r
2017**/\r
2018SHELL_STATUS\r
2019EFIAPI\r
2020ShellCommandRunPci (\r
2021 IN EFI_HANDLE ImageHandle,\r
2022 IN EFI_SYSTEM_TABLE *SystemTable\r
2023 )\r
2024{\r
2025 UINT16 Segment;\r
2026 UINT16 Bus;\r
2027 UINT16 Device;\r
2028 UINT16 Func;\r
2029 UINT64 Address;\r
2030 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
2031 EFI_STATUS Status;\r
2032 PCI_COMMON_HEADER PciHeader;\r
2033 PCI_CONFIG_SPACE ConfigSpace;\r
2034 UINTN ScreenCount;\r
2035 UINTN TempColumn;\r
2036 UINTN ScreenSize;\r
2037 BOOLEAN ExplainData;\r
2038 UINTN Index;\r
2039 UINTN SizeOfHeader;\r
2040 BOOLEAN PrintTitle;\r
2041 UINTN HandleBufSize;\r
2042 EFI_HANDLE *HandleBuf;\r
2043 UINTN HandleCount;\r
2044 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2045 UINT16 MinBus;\r
2046 UINT16 MaxBus;\r
2047 BOOLEAN IsEnd;\r
2048 LIST_ENTRY *Package;\r
2049 CHAR16 *ProblemParam;\r
2050 SHELL_STATUS ShellStatus;\r
2051 CONST CHAR16 *Temp;\r
2052 UINT64 RetVal;\r
2053\r
2054 ShellStatus = SHELL_SUCCESS;\r
2055 Status = EFI_SUCCESS;\r
2056 Address = 0;\r
2057 IoDev = NULL;\r
2058 HandleBuf = NULL;\r
2059 Package = NULL;\r
2060\r
2061 //\r
2062 // initialize the shell lib (we must be in non-auto-init...)\r
2063 //\r
2064 Status = ShellInitialize();\r
2065 ASSERT_EFI_ERROR(Status);\r
2066\r
2067 Status = CommandInit();\r
2068 ASSERT_EFI_ERROR(Status);\r
2069\r
2070 //\r
2071 // parse the command line\r
2072 //\r
2073 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
2074 if (EFI_ERROR(Status)) {\r
2075 if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
2076 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
2077 FreePool(ProblemParam);\r
2078 ShellStatus = SHELL_INVALID_PARAMETER;\r
2079 } else {\r
2080 ASSERT(FALSE);\r
2081 }\r
2082 } else {\r
2083\r
2084 if (ShellCommandLineGetCount(Package) == 2) {\r
2085 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
2086 ShellStatus = SHELL_INVALID_PARAMETER;\r
2087 goto Done;\r
2088 }\r
2089\r
2090 if (ShellCommandLineGetCount(Package) > 4) {\r
2091 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
2092 ShellStatus = SHELL_INVALID_PARAMETER;\r
2093 goto Done;\r
2094 }\r
2095 if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
2096 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
2097 ShellStatus = SHELL_INVALID_PARAMETER;\r
2098 goto Done;\r
2099 }\r
2100 //\r
2101 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
2102 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
2103 // space for handles and call it again.\r
2104 //\r
2105 HandleBufSize = sizeof (EFI_HANDLE);\r
2106 HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
2107 if (HandleBuf == NULL) {\r
2108 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2109 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2110 goto Done;\r
2111 }\r
2112\r
2113 Status = gBS->LocateHandle (\r
2114 ByProtocol,\r
2115 &gEfiPciRootBridgeIoProtocolGuid,\r
2116 NULL,\r
2117 &HandleBufSize,\r
2118 HandleBuf\r
2119 );\r
2120\r
2121 if (Status == EFI_BUFFER_TOO_SMALL) {\r
2122 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
2123 if (HandleBuf == NULL) {\r
2124 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2125 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2126 goto Done;\r
2127 }\r
2128\r
2129 Status = gBS->LocateHandle (\r
2130 ByProtocol,\r
2131 &gEfiPciRootBridgeIoProtocolGuid,\r
2132 NULL,\r
2133 &HandleBufSize,\r
2134 HandleBuf\r
2135 );\r
2136 }\r
2137\r
2138 if (EFI_ERROR (Status)) {\r
2139 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
2140 ShellStatus = SHELL_NOT_FOUND;\r
2141 goto Done;\r
2142 }\r
2143\r
2144 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r
2145 //\r
2146 // Argument Count == 1(no other argument): enumerate all pci functions\r
2147 //\r
2148 if (ShellCommandLineGetCount(Package) == 1) {\r
2149 gST->ConOut->QueryMode (\r
2150 gST->ConOut,\r
2151 gST->ConOut->Mode->Mode,\r
2152 &TempColumn,\r
2153 &ScreenSize\r
2154 );\r
2155\r
2156 ScreenCount = 0;\r
2157 ScreenSize -= 4;\r
2158 if ((ScreenSize & 1) == 1) {\r
2159 ScreenSize -= 1;\r
2160 }\r
2161\r
2162 PrintTitle = TRUE;\r
2163\r
2164 //\r
2165 // For each handle, which decides a segment and a bus number range,\r
2166 // enumerate all devices on it.\r
2167 //\r
2168 for (Index = 0; Index < HandleCount; Index++) {\r
2169 Status = PciGetProtocolAndResource (\r
2170 HandleBuf[Index],\r
2171 &IoDev,\r
2172 &Descriptors\r
2173 );\r
2174 if (EFI_ERROR (Status)) {\r
2175 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
2176 ShellStatus = SHELL_NOT_FOUND;\r
2177 goto Done;\r
2178 }\r
2179 //\r
2180 // No document say it's impossible for a RootBridgeIo protocol handle\r
2181 // to have more than one address space descriptors, so find out every\r
2182 // bus range and for each of them do device enumeration.\r
2183 //\r
2184 while (TRUE) {\r
2185 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2186\r
2187 if (EFI_ERROR (Status)) {\r
2188 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
2189 ShellStatus = SHELL_NOT_FOUND;\r
2190 goto Done;\r
2191 }\r
2192\r
2193 if (IsEnd) {\r
2194 break;\r
2195 }\r
2196\r
2197 for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r
2198 //\r
2199 // For each devices, enumerate all functions it contains\r
2200 //\r
2201 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
2202 //\r
2203 // For each function, read its configuration space and print summary\r
2204 //\r
2205 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
2206 if (ShellGetExecutionBreakFlag ()) {\r
2207 ShellStatus = SHELL_ABORTED;\r
2208 goto Done;\r
2209 }\r
2210 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2211 IoDev->Pci.Read (\r
2212 IoDev,\r
2213 EfiPciWidthUint16,\r
2214 Address,\r
2215 1,\r
2216 &PciHeader.VendorId\r
2217 );\r
2218\r
2219 //\r
2220 // If VendorId = 0xffff, there does not exist a device at this\r
2221 // location. For each device, if there is any function on it,\r
2222 // there must be 1 function at Function 0. So if Func = 0, there\r
2223 // will be no more functions in the same device, so we can break\r
2224 // loop to deal with the next device.\r
2225 //\r
2226 if (PciHeader.VendorId == 0xffff && Func == 0) {\r
2227 break;\r
2228 }\r
2229\r
2230 if (PciHeader.VendorId != 0xffff) {\r
2231\r
2232 if (PrintTitle) {\r
2233 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
2234 PrintTitle = FALSE;\r
2235 }\r
2236\r
2237 IoDev->Pci.Read (\r
2238 IoDev,\r
2239 EfiPciWidthUint32,\r
2240 Address,\r
2241 sizeof (PciHeader) / sizeof (UINT32),\r
2242 &PciHeader\r
2243 );\r
2244\r
2245 ShellPrintHiiEx(\r
2246 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
2247 IoDev->SegmentNumber,\r
2248 Bus,\r
2249 Device,\r
2250 Func\r
2251 );\r
2252\r
2253 PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
2254 ShellPrintHiiEx(\r
2255 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
2256 PciHeader.VendorId,\r
2257 PciHeader.DeviceId,\r
2258 PciHeader.ClassCode[0]\r
2259 );\r
2260\r
2261 ScreenCount += 2;\r
2262 if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
2263 //\r
2264 // If ScreenSize == 0 we have the console redirected so don't\r
2265 // block updates\r
2266 //\r
2267 ScreenCount = 0;\r
2268 }\r
2269 //\r
2270 // If this is not a multi-function device, we can leave the loop\r
2271 // to deal with the next device.\r
2272 //\r
2273 if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
2274 break;\r
2275 }\r
2276 }\r
2277 }\r
2278 }\r
2279 }\r
2280 //\r
2281 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
2282 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
2283 // devices on all bus, we can leave loop.\r
2284 //\r
2285 if (Descriptors == NULL) {\r
2286 break;\r
2287 }\r
2288 }\r
2289 }\r
2290\r
2291 Status = EFI_SUCCESS;\r
2292 goto Done;\r
2293 }\r
2294\r
2295 ExplainData = FALSE;\r
2296 Segment = 0;\r
2297 Bus = 0;\r
2298 Device = 0;\r
2299 Func = 0;\r
2300 if (ShellCommandLineGetFlag(Package, L"-i")) {\r
2301 ExplainData = TRUE;\r
2302 }\r
2303\r
2304 Temp = ShellCommandLineGetValue(Package, L"-s");\r
2305 if (Temp != NULL) {\r
2306 //\r
2307 // Input converted to hexadecimal number.\r
2308 //\r
2309 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2310 Segment = (UINT16) RetVal;\r
2311 } else {\r
2312 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2313 ShellStatus = SHELL_INVALID_PARAMETER;\r
2314 goto Done;\r
2315 }\r
2316 }\r
2317\r
2318 //\r
2319 // The first Argument(except "-i") is assumed to be Bus number, second\r
2320 // to be Device number, and third to be Func number.\r
2321 //\r
2322 Temp = ShellCommandLineGetRawValue(Package, 1);\r
2323 if (Temp != NULL) {\r
2324 //\r
2325 // Input converted to hexadecimal number.\r
2326 //\r
2327 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2328 Bus = (UINT16) RetVal;\r
2329 } else {\r
2330 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2331 ShellStatus = SHELL_INVALID_PARAMETER;\r
2332 goto Done;\r
2333 }\r
2334\r
2335 if (Bus > MAX_BUS_NUMBER) {\r
2336 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2337 ShellStatus = SHELL_INVALID_PARAMETER;\r
2338 goto Done;\r
2339 }\r
2340 }\r
2341 Temp = ShellCommandLineGetRawValue(Package, 2);\r
2342 if (Temp != NULL) {\r
2343 //\r
2344 // Input converted to hexadecimal number.\r
2345 //\r
2346 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2347 Device = (UINT16) RetVal;\r
2348 } else {\r
2349 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2350 ShellStatus = SHELL_INVALID_PARAMETER;\r
2351 goto Done;\r
2352 }\r
2353\r
2354 if (Device > MAX_DEVICE_NUMBER){\r
2355 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2356 ShellStatus = SHELL_INVALID_PARAMETER;\r
2357 goto Done;\r
2358 }\r
2359 }\r
2360\r
2361 Temp = ShellCommandLineGetRawValue(Package, 3);\r
2362 if (Temp != NULL) {\r
2363 //\r
2364 // Input converted to hexadecimal number.\r
2365 //\r
2366 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2367 Func = (UINT16) RetVal;\r
2368 } else {\r
2369 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2370 ShellStatus = SHELL_INVALID_PARAMETER;\r
2371 goto Done;\r
2372 }\r
2373\r
2374 if (Func > MAX_FUNCTION_NUMBER){\r
2375 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2376 ShellStatus = SHELL_INVALID_PARAMETER;\r
2377 goto Done;\r
2378 }\r
2379 }\r
2380\r
2381 //\r
2382 // Find the protocol interface who's in charge of current segment, and its\r
2383 // bus range covers the current bus\r
2384 //\r
2385 Status = PciFindProtocolInterface (\r
2386 HandleBuf,\r
2387 HandleCount,\r
2388 Segment,\r
2389 Bus,\r
2390 &IoDev\r
2391 );\r
2392\r
2393 if (EFI_ERROR (Status)) {\r
2394 ShellPrintHiiEx(\r
2395 -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
2396 Segment,\r
2397 Bus\r
2398 );\r
2399 ShellStatus = SHELL_NOT_FOUND;\r
2400 goto Done;\r
2401 }\r
2402\r
2403 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2404 Status = IoDev->Pci.Read (\r
2405 IoDev,\r
2406 EfiPciWidthUint8,\r
2407 Address,\r
2408 sizeof (ConfigSpace),\r
2409 &ConfigSpace\r
2410 );\r
2411\r
2412 if (EFI_ERROR (Status)) {\r
2413 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
2414 ShellStatus = SHELL_ACCESS_DENIED;\r
2415 goto Done;\r
2416 }\r
2417\r
2418 mConfigSpace = &ConfigSpace;\r
2419 ShellPrintHiiEx(\r
2420 -1,\r
2421 -1,\r
2422 NULL,\r
2423 STRING_TOKEN (STR_PCI_INFO),\r
2424 gShellDebug1HiiHandle,\r
2425 Segment,\r
2426 Bus,\r
2427 Device,\r
2428 Func,\r
2429 Segment,\r
2430 Bus,\r
2431 Device,\r
2432 Func\r
2433 );\r
2434\r
2435 //\r
2436 // Dump standard header of configuration space\r
2437 //\r
2438 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
2439\r
2440 DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
2441 ShellPrintEx(-1,-1, L"\r\n");\r
2442\r
2443 //\r
2444 // Dump device dependent Part of configuration space\r
2445 //\r
2446 DumpHex (\r
2447 2,\r
2448 SizeOfHeader,\r
2449 sizeof (ConfigSpace) - SizeOfHeader,\r
2450 ConfigSpace.Data\r
2451 );\r
2452\r
2453 //\r
2454 // If "-i" appears in command line, interpret data in configuration space\r
2455 //\r
2456 if (ExplainData) {\r
2457 Status = PciExplainData (&ConfigSpace, Address, IoDev);\r
2458 }\r
2459 }\r
2460Done:\r
2461 if (HandleBuf != NULL) {\r
2462 FreePool (HandleBuf);\r
2463 }\r
2464 if (Package != NULL) {\r
2465 ShellCommandLineFreeVarList (Package);\r
2466 }\r
2467 mConfigSpace = NULL;\r
2468 return ShellStatus;\r
2469}\r
2470\r
2471/**\r
2472 This function finds out the protocol which is in charge of the given\r
2473 segment, and its bus range covers the current bus number. It lookes\r
2474 each instances of RootBridgeIoProtocol handle, until the one meets the\r
2475 criteria is found.\r
2476\r
2477 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2478 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2479 @param[in] Segment Segment number of device we are dealing with.\r
2480 @param[in] Bus Bus number of device we are dealing with.\r
2481 @param[out] IoDev Handle used to access configuration space of PCI device.\r
2482\r
2483 @retval EFI_SUCCESS The command completed successfully.\r
2484 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
2485\r
2486**/\r
2487EFI_STATUS\r
2488PciFindProtocolInterface (\r
2489 IN EFI_HANDLE *HandleBuf,\r
2490 IN UINTN HandleCount,\r
2491 IN UINT16 Segment,\r
2492 IN UINT16 Bus,\r
2493 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
2494 )\r
2495{\r
2496 UINTN Index;\r
2497 EFI_STATUS Status;\r
2498 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2499 UINT16 MinBus;\r
2500 UINT16 MaxBus;\r
2501 BOOLEAN IsEnd;\r
2502\r
2503 //\r
2504 // Go through all handles, until the one meets the criteria is found\r
2505 //\r
2506 for (Index = 0; Index < HandleCount; Index++) {\r
2507 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r
2508 if (EFI_ERROR (Status)) {\r
2509 return Status;\r
2510 }\r
2511 //\r
2512 // When Descriptors == NULL, the Configuration() is not implemented,\r
2513 // so we only check the Segment number\r
2514 //\r
2515 if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
2516 return EFI_SUCCESS;\r
2517 }\r
2518\r
2519 if ((*IoDev)->SegmentNumber != Segment) {\r
2520 continue;\r
2521 }\r
2522\r
2523 while (TRUE) {\r
2524 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2525 if (EFI_ERROR (Status)) {\r
2526 return Status;\r
2527 }\r
2528\r
2529 if (IsEnd) {\r
2530 break;\r
2531 }\r
2532\r
2533 if (MinBus <= Bus && MaxBus >= Bus) {\r
2534 return EFI_SUCCESS;\r
2535 }\r
2536 }\r
2537 }\r
2538\r
2539 return EFI_NOT_FOUND;\r
2540}\r
2541\r
2542/**\r
2543 This function gets the protocol interface from the given handle, and\r
2544 obtains its address space descriptors.\r
2545\r
2546 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
2547 @param[out] IoDev Handle used to access configuration space of PCI device.\r
2548 @param[out] Descriptors Points to the address space descriptors.\r
2549\r
2550 @retval EFI_SUCCESS The command completed successfully\r
2551**/\r
2552EFI_STATUS\r
2553PciGetProtocolAndResource (\r
2554 IN EFI_HANDLE Handle,\r
2555 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
2556 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
2557 )\r
2558{\r
2559 EFI_STATUS Status;\r
2560\r
2561 //\r
2562 // Get inferface from protocol\r
2563 //\r
2564 Status = gBS->HandleProtocol (\r
2565 Handle,\r
2566 &gEfiPciRootBridgeIoProtocolGuid,\r
2567 (VOID**)IoDev\r
2568 );\r
2569\r
2570 if (EFI_ERROR (Status)) {\r
2571 return Status;\r
2572 }\r
2573 //\r
2574 // Call Configuration() to get address space descriptors\r
2575 //\r
2576 Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
2577 if (Status == EFI_UNSUPPORTED) {\r
2578 *Descriptors = NULL;\r
2579 return EFI_SUCCESS;\r
2580\r
2581 } else {\r
2582 return Status;\r
2583 }\r
2584}\r
2585\r
2586/**\r
2587 This function get the next bus range of given address space descriptors.\r
2588 It also moves the pointer backward a node, to get prepared to be called\r
2589 again.\r
2590\r
2591 @param[in, out] Descriptors Points to current position of a serial of address space\r
2592 descriptors.\r
2593 @param[out] MinBus The lower range of bus number.\r
2594 @param[out] MaxBus The upper range of bus number.\r
2595 @param[out] IsEnd Meet end of the serial of descriptors.\r
2596\r
2597 @retval EFI_SUCCESS The command completed successfully.\r
2598**/\r
2599EFI_STATUS\r
2600PciGetNextBusRange (\r
2601 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
2602 OUT UINT16 *MinBus,\r
2603 OUT UINT16 *MaxBus,\r
2604 OUT BOOLEAN *IsEnd\r
2605 )\r
2606{\r
2607 *IsEnd = FALSE;\r
2608\r
2609 //\r
2610 // When *Descriptors is NULL, Configuration() is not implemented, so assume\r
2611 // range is 0~PCI_MAX_BUS\r
2612 //\r
2613 if ((*Descriptors) == NULL) {\r
2614 *MinBus = 0;\r
2615 *MaxBus = PCI_MAX_BUS;\r
2616 return EFI_SUCCESS;\r
2617 }\r
2618 //\r
2619 // *Descriptors points to one or more address space descriptors, which\r
2620 // ends with a end tagged descriptor. Examine each of the descriptors,\r
2621 // if a bus typed one is found and its bus range covers bus, this handle\r
2622 // is the handle we are looking for.\r
2623 //\r
2624\r
2625 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
2626 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
2627 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
2628 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
2629 (*Descriptors)++;\r
2630 return (EFI_SUCCESS);\r
2631 }\r
2632\r
2633 (*Descriptors)++;\r
2634 }\r
2635\r
2636 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
2637 *IsEnd = TRUE;\r
2638 }\r
2639\r
2640 return EFI_SUCCESS;\r
2641}\r
2642\r
2643/**\r
2644 Explain the data in PCI configuration space. The part which is common for\r
2645 PCI device and bridge is interpreted in this function. It calls other\r
2646 functions to interpret data unique for device or bridge.\r
2647\r
2648 @param[in] ConfigSpace Data in PCI configuration space.\r
2649 @param[in] Address Address used to access configuration space of this PCI device.\r
2650 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2651\r
2652 @retval EFI_SUCCESS The command completed successfully.\r
2653**/\r
2654EFI_STATUS\r
2655PciExplainData (\r
2656 IN PCI_CONFIG_SPACE *ConfigSpace,\r
2657 IN UINT64 Address,\r
2658 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2659 )\r
2660{\r
2661 PCI_COMMON_HEADER *Common;\r
2662 PCI_HEADER_TYPE HeaderType;\r
2663 EFI_STATUS Status;\r
2664 UINT8 CapPtr;\r
2665\r
2666 Common = &(ConfigSpace->Common);\r
2667\r
2668 ShellPrintEx (-1, -1, L"\r\n");\r
2669\r
2670 //\r
2671 // Print Vendor Id and Device Id\r
2672 //\r
2673 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
2674 INDEX_OF (&(Common->VendorId)),\r
2675 Common->VendorId,\r
2676 INDEX_OF (&(Common->DeviceId)),\r
2677 Common->DeviceId\r
2678 );\r
2679\r
2680 //\r
2681 // Print register Command\r
2682 //\r
2683 PciExplainCommand (&(Common->Command));\r
2684\r
2685 //\r
2686 // Print register Status\r
2687 //\r
2688 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r
2689\r
2690 //\r
2691 // Print register Revision ID\r
2692 //\r
2693 ShellPrintEx(-1, -1, L"\r\n");\r
2694 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
2695 INDEX_OF (&(Common->RevisionId)),\r
2696 Common->RevisionId\r
2697 );\r
2698\r
2699 //\r
2700 // Print register BIST\r
2701 //\r
2702 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
2703 if ((Common->Bist & PCI_BIT_7) != 0) {\r
2704 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
2705 } else {\r
2706 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
2707 }\r
2708 //\r
2709 // Print register Cache Line Size\r
2710 //\r
2711 ShellPrintHiiEx(-1, -1, NULL,\r
2712 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
2713 gShellDebug1HiiHandle,\r
2714 INDEX_OF (&(Common->CacheLineSize)),\r
2715 Common->CacheLineSize\r
2716 );\r
2717\r
2718 //\r
2719 // Print register Latency Timer\r
2720 //\r
2721 ShellPrintHiiEx(-1, -1, NULL,\r
2722 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
2723 gShellDebug1HiiHandle,\r
2724 INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
2725 Common->PrimaryLatencyTimer\r
2726 );\r
2727\r
2728 //\r
2729 // Print register Header Type\r
2730 //\r
2731 ShellPrintHiiEx(-1, -1, NULL,\r
2732 STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
2733 gShellDebug1HiiHandle,\r
2734 INDEX_OF (&(Common->HeaderType)),\r
2735 Common->HeaderType\r
2736 );\r
2737\r
2738 if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
2739 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
2740\r
2741 } else {\r
2742 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
2743 }\r
2744\r
2745 HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
2746 switch (HeaderType) {\r
2747 case PciDevice:\r
2748 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
2749 break;\r
2750\r
2751 case PciP2pBridge:\r
2752 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
2753 break;\r
2754\r
2755 case PciCardBusBridge:\r
2756 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
2757 break;\r
2758\r
2759 default:\r
2760 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
2761 HeaderType = PciUndefined;\r
2762 }\r
2763\r
2764 //\r
2765 // Print register Class Code\r
2766 //\r
2767 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
2768 PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
2769 ShellPrintEx (-1, -1, L"\r\n");\r
2770\r
2771 if (ShellGetExecutionBreakFlag()) {\r
2772 return EFI_SUCCESS;\r
2773 }\r
2774\r
2775 //\r
2776 // Interpret remaining part of PCI configuration header depending on\r
2777 // HeaderType\r
2778 //\r
2779 CapPtr = 0;\r
2780 Status = EFI_SUCCESS;\r
2781 switch (HeaderType) {\r
2782 case PciDevice:\r
2783 Status = PciExplainDeviceData (\r
2784 &(ConfigSpace->NonCommon.Device),\r
2785 Address,\r
2786 IoDev\r
2787 );\r
2788 CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
2789 break;\r
2790\r
2791 case PciP2pBridge:\r
2792 Status = PciExplainBridgeData (\r
2793 &(ConfigSpace->NonCommon.Bridge),\r
2794 Address,\r
2795 IoDev\r
2796 );\r
2797 CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
2798 break;\r
2799\r
2800 case PciCardBusBridge:\r
2801 Status = PciExplainCardBusData (\r
2802 &(ConfigSpace->NonCommon.CardBus),\r
2803 Address,\r
2804 IoDev\r
2805 );\r
2806 CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
2807 break;\r
2808 case PciUndefined:\r
2809 default:\r
2810 break;\r
2811 }\r
2812 //\r
2813 // If Status bit4 is 1, dump or explain capability structure\r
2814 //\r
2815 if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
2816 PciExplainCapabilityStruct (IoDev, Address, CapPtr);\r
2817 }\r
2818\r
2819 return Status;\r
2820}\r
2821\r
2822/**\r
2823 Explain the device specific part of data in PCI configuration space.\r
2824\r
2825 @param[in] Device Data in PCI configuration space.\r
2826 @param[in] Address Address used to access configuration space of this PCI device.\r
2827 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2828\r
2829 @retval EFI_SUCCESS The command completed successfully.\r
2830**/\r
2831EFI_STATUS\r
2832PciExplainDeviceData (\r
2833 IN PCI_DEVICE_HEADER *Device,\r
2834 IN UINT64 Address,\r
2835 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2836 )\r
2837{\r
2838 UINTN Index;\r
2839 BOOLEAN BarExist;\r
2840 EFI_STATUS Status;\r
2841 UINTN BarCount;\r
2842\r
2843 //\r
2844 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r
2845 // exist. If these no Bar for this function, print "none", otherwise\r
2846 // list detail information about this Bar.\r
2847 //\r
2848 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
2849\r
2850 BarExist = FALSE;\r
2851 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
2852 for (Index = 0; Index < BarCount; Index++) {\r
2853 if (Device->Bar[Index] == 0) {\r
2854 continue;\r
2855 }\r
2856\r
2857 if (!BarExist) {\r
2858 BarExist = TRUE;\r
2859 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
2860 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
2861 }\r
2862\r
2863 Status = PciExplainBar (\r
2864 &(Device->Bar[Index]),\r
2865 &(mConfigSpace->Common.Command),\r
2866 Address,\r
2867 IoDev,\r
2868 &Index\r
2869 );\r
2870\r
2871 if (EFI_ERROR (Status)) {\r
2872 break;\r
2873 }\r
2874 }\r
2875\r
2876 if (!BarExist) {\r
2877 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2878\r
2879 } else {\r
2880 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
2881 }\r
2882\r
2883 //\r
2884 // Print register Expansion ROM Base Address\r
2885 //\r
2886 if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
2887 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
2888\r
2889 } else {\r
2890 ShellPrintHiiEx(-1, -1, NULL,\r
2891 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
2892 gShellDebug1HiiHandle,\r
2893 INDEX_OF (&(Device->ROMBar)),\r
2894 Device->ROMBar\r
2895 );\r
2896 }\r
2897 //\r
2898 // Print register Cardbus CIS ptr\r
2899 //\r
2900 ShellPrintHiiEx(-1, -1, NULL,\r
2901 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
2902 gShellDebug1HiiHandle,\r
2903 INDEX_OF (&(Device->CardBusCISPtr)),\r
2904 Device->CardBusCISPtr\r
2905 );\r
2906\r
2907 //\r
2908 // Print register Sub-vendor ID and subsystem ID\r
2909 //\r
2910 ShellPrintHiiEx(-1, -1, NULL,\r
2911 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
2912 gShellDebug1HiiHandle,\r
2913 INDEX_OF (&(Device->SubVendorId)),\r
2914 Device->SubVendorId\r
2915 );\r
2916\r
2917 ShellPrintHiiEx(-1, -1, NULL,\r
2918 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
2919 gShellDebug1HiiHandle,\r
2920 INDEX_OF (&(Device->SubSystemId)),\r
2921 Device->SubSystemId\r
2922 );\r
2923\r
2924 //\r
2925 // Print register Capabilities Ptr\r
2926 //\r
2927 ShellPrintHiiEx(-1, -1, NULL,\r
2928 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
2929 gShellDebug1HiiHandle,\r
2930 INDEX_OF (&(Device->CapabilitiesPtr)),\r
2931 Device->CapabilitiesPtr\r
2932 );\r
2933\r
2934 //\r
2935 // Print register Interrupt Line and interrupt pin\r
2936 //\r
2937 ShellPrintHiiEx(-1, -1, NULL,\r
2938 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
2939 gShellDebug1HiiHandle,\r
2940 INDEX_OF (&(Device->InterruptLine)),\r
2941 Device->InterruptLine\r
2942 );\r
2943\r
2944 ShellPrintHiiEx(-1, -1, NULL,\r
2945 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
2946 gShellDebug1HiiHandle,\r
2947 INDEX_OF (&(Device->InterruptPin)),\r
2948 Device->InterruptPin\r
2949 );\r
2950\r
2951 //\r
2952 // Print register Min_Gnt and Max_Lat\r
2953 //\r
2954 ShellPrintHiiEx(-1, -1, NULL,\r
2955 STRING_TOKEN (STR_PCI2_MIN_GNT),\r
2956 gShellDebug1HiiHandle,\r
2957 INDEX_OF (&(Device->MinGnt)),\r
2958 Device->MinGnt\r
2959 );\r
2960\r
2961 ShellPrintHiiEx(-1, -1, NULL,\r
2962 STRING_TOKEN (STR_PCI2_MAX_LAT),\r
2963 gShellDebug1HiiHandle,\r
2964 INDEX_OF (&(Device->MaxLat)),\r
2965 Device->MaxLat\r
2966 );\r
2967\r
2968 return EFI_SUCCESS;\r
2969}\r
2970\r
2971/**\r
2972 Explain the bridge specific part of data in PCI configuration space.\r
2973\r
2974 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
2975 @param[in] Address Address used to access configuration space of this PCI device.\r
2976 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2977\r
2978 @retval EFI_SUCCESS The command completed successfully.\r
2979**/\r
2980EFI_STATUS\r
2981PciExplainBridgeData (\r
2982 IN PCI_BRIDGE_HEADER *Bridge,\r
2983 IN UINT64 Address,\r
2984 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2985 )\r
2986{\r
2987 UINTN Index;\r
2988 BOOLEAN BarExist;\r
2989 UINTN BarCount;\r
2990 UINT32 IoAddress32;\r
2991 EFI_STATUS Status;\r
2992\r
2993 //\r
2994 // Print Base Address Registers. When Bar = 0, this Bar does not\r
2995 // exist. If these no Bar for this function, print "none", otherwise\r
2996 // list detail information about this Bar.\r
2997 //\r
2998 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
2999\r
3000 BarExist = FALSE;\r
3001 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
3002\r
3003 for (Index = 0; Index < BarCount; Index++) {\r
3004 if (Bridge->Bar[Index] == 0) {\r
3005 continue;\r
3006 }\r
3007\r
3008 if (!BarExist) {\r
3009 BarExist = TRUE;\r
3010 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
3011 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
3012 }\r
3013\r
3014 Status = PciExplainBar (\r
3015 &(Bridge->Bar[Index]),\r
3016 &(mConfigSpace->Common.Command),\r
3017 Address,\r
3018 IoDev,\r
3019 &Index\r
3020 );\r
3021\r
3022 if (EFI_ERROR (Status)) {\r
3023 break;\r
3024 }\r
3025 }\r
3026\r
3027 if (!BarExist) {\r
3028 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
3029 } else {\r
3030 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
3031 }\r
3032\r
3033 //\r
3034 // Expansion register ROM Base Address\r
3035 //\r
3036 if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
3037 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
3038\r
3039 } else {\r
3040 ShellPrintHiiEx(-1, -1, NULL,\r
3041 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
3042 gShellDebug1HiiHandle,\r
3043 INDEX_OF (&(Bridge->ROMBar)),\r
3044 Bridge->ROMBar\r
3045 );\r
3046 }\r
3047 //\r
3048 // Print Bus Numbers(Primary, Secondary, and Subordinate\r
3049 //\r
3050 ShellPrintHiiEx(-1, -1, NULL,\r
3051 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
3052 gShellDebug1HiiHandle,\r
3053 INDEX_OF (&(Bridge->PrimaryBus)),\r
3054 INDEX_OF (&(Bridge->SecondaryBus)),\r
3055 INDEX_OF (&(Bridge->SubordinateBus))\r
3056 );\r
3057\r
3058 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
3059\r
3060 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
3061 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
3062 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
3063\r
3064 //\r
3065 // Print register Secondary Latency Timer\r
3066 //\r
3067 ShellPrintHiiEx(-1, -1, NULL,\r
3068 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
3069 gShellDebug1HiiHandle,\r
3070 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
3071 Bridge->SecondaryLatencyTimer\r
3072 );\r
3073\r
3074 //\r
3075 // Print register Secondary Status\r
3076 //\r
3077 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r
3078\r
3079 //\r
3080 // Print I/O and memory ranges this bridge forwards. There are 3 resource\r
3081 // types: I/O, memory, and pre-fetchable memory. For each resource type,\r
3082 // base and limit address are listed.\r
3083 //\r
3084 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
3085 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
3086\r
3087 //\r
3088 // IO Base & Limit\r
3089 //\r
3090 IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
3091 IoAddress32 &= 0xfffff000;\r
3092 ShellPrintHiiEx(-1, -1, NULL,\r
3093 STRING_TOKEN (STR_PCI2_TWO_VARS),\r
3094 gShellDebug1HiiHandle,\r
3095 INDEX_OF (&(Bridge->IoBase)),\r
3096 IoAddress32\r
3097 );\r
3098\r
3099 IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
3100 IoAddress32 |= 0x00000fff;\r
3101 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
3102\r
3103 //\r
3104 // Memory Base & Limit\r
3105 //\r
3106 ShellPrintHiiEx(-1, -1, NULL,\r
3107 STRING_TOKEN (STR_PCI2_MEMORY),\r
3108 gShellDebug1HiiHandle,\r
3109 INDEX_OF (&(Bridge->MemoryBase)),\r
3110 (Bridge->MemoryBase << 16) & 0xfff00000\r
3111 );\r
3112\r
3113 ShellPrintHiiEx(-1, -1, NULL,\r
3114 STRING_TOKEN (STR_PCI2_ONE_VAR),\r
3115 gShellDebug1HiiHandle,\r
3116 (Bridge->MemoryLimit << 16) | 0x000fffff\r
3117 );\r
3118\r
3119 //\r
3120 // Pre-fetch-able Memory Base & Limit\r
3121 //\r
3122 ShellPrintHiiEx(-1, -1, NULL,\r
3123 STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
3124 gShellDebug1HiiHandle,\r
3125 INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
3126 Bridge->PrefetchableBaseUpper,\r
3127 (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
3128 );\r
3129\r
3130 ShellPrintHiiEx(-1, -1, NULL,\r
3131 STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
3132 gShellDebug1HiiHandle,\r
3133 Bridge->PrefetchableLimitUpper,\r
3134 (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
3135 );\r
3136\r
3137 //\r
3138 // Print register Capabilities Pointer\r
3139 //\r
3140 ShellPrintHiiEx(-1, -1, NULL,\r
3141 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
3142 gShellDebug1HiiHandle,\r
3143 INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
3144 Bridge->CapabilitiesPtr\r
3145 );\r
3146\r
3147 //\r
3148 // Print register Bridge Control\r
3149 //\r
3150 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r
3151\r
3152 //\r
3153 // Print register Interrupt Line & PIN\r
3154 //\r
3155 ShellPrintHiiEx(-1, -1, NULL,\r
3156 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
3157 gShellDebug1HiiHandle,\r
3158 INDEX_OF (&(Bridge->InterruptLine)),\r
3159 Bridge->InterruptLine\r
3160 );\r
3161\r
3162 ShellPrintHiiEx(-1, -1, NULL,\r
3163 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3164 gShellDebug1HiiHandle,\r
3165 INDEX_OF (&(Bridge->InterruptPin)),\r
3166 Bridge->InterruptPin\r
3167 );\r
3168\r
3169 return EFI_SUCCESS;\r
3170}\r
3171\r
3172/**\r
3173 Explain the Base Address Register(Bar) in PCI configuration space.\r
3174\r
3175 @param[in] Bar Points to the Base Address Register intended to interpret.\r
3176 @param[in] Command Points to the register Command.\r
3177 @param[in] Address Address used to access configuration space of this PCI device.\r
3178 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3179 @param[in, out] Index The Index.\r
3180\r
3181 @retval EFI_SUCCESS The command completed successfully.\r
3182**/\r
3183EFI_STATUS\r
3184PciExplainBar (\r
3185 IN UINT32 *Bar,\r
3186 IN UINT16 *Command,\r
3187 IN UINT64 Address,\r
3188 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3189 IN OUT UINTN *Index\r
3190 )\r
3191{\r
3192 UINT16 OldCommand;\r
3193 UINT16 NewCommand;\r
3194 UINT64 Bar64;\r
3195 UINT32 OldBar32;\r
3196 UINT32 NewBar32;\r
3197 UINT64 OldBar64;\r
3198 UINT64 NewBar64;\r
3199 BOOLEAN IsMem;\r
3200 BOOLEAN IsBar32;\r
3201 UINT64 RegAddress;\r
3202\r
3203 IsBar32 = TRUE;\r
3204 Bar64 = 0;\r
3205 NewBar32 = 0;\r
3206 NewBar64 = 0;\r
3207\r
3208 //\r
3209 // According the bar type, list detail about this bar, for example: 32 or\r
3210 // 64 bits; pre-fetchable or not.\r
3211 //\r
3212 if ((*Bar & PCI_BIT_0) == 0) {\r
3213 //\r
3214 // This bar is of memory type\r
3215 //\r
3216 IsMem = TRUE;\r
3217\r
3218 if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
3219 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3220 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3221 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
3222\r
3223 } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
3224 Bar64 = 0x0;\r
3225 CopyMem (&Bar64, Bar, sizeof (UINT64));\r
3226 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
3227 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
3228 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3229 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
3230 IsBar32 = FALSE;\r
3231 *Index += 1;\r
3232\r
3233 } else {\r
3234 //\r
3235 // Reserved\r
3236 //\r
3237 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3238 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
3239 }\r
3240\r
3241 if ((*Bar & PCI_BIT_3) == 0) {\r
3242 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
3243\r
3244 } else {\r
3245 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
3246 }\r
3247\r
3248 } else {\r
3249 //\r
3250 // This bar is of io type\r
3251 //\r
3252 IsMem = FALSE;\r
3253 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
3254 ShellPrintEx (-1, -1, L"I/O ");\r
3255 }\r
3256\r
3257 //\r
3258 // Get BAR length(or the amount of resource this bar demands for). To get\r
3259 // Bar length, first we should temporarily disable I/O and memory access\r
3260 // of this function(by set bits in the register Command), then write all\r
3261 // "1"s to this bar. The bar value read back is the amount of resource\r
3262 // this bar demands for.\r
3263 //\r
3264 //\r
3265 // Disable io & mem access\r
3266 //\r
3267 OldCommand = *Command;\r
3268 NewCommand = (UINT16) (OldCommand & 0xfffc);\r
3269 RegAddress = Address | INDEX_OF (Command);\r
3270 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
3271\r
3272 RegAddress = Address | INDEX_OF (Bar);\r
3273\r
3274 //\r
3275 // Read after write the BAR to get the size\r
3276 //\r
3277 if (IsBar32) {\r
3278 OldBar32 = *Bar;\r
3279 NewBar32 = 0xffffffff;\r
3280\r
3281 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3282 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3283 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
3284\r
3285 if (IsMem) {\r
3286 NewBar32 = NewBar32 & 0xfffffff0;\r
3287 NewBar32 = (~NewBar32) + 1;\r
3288\r
3289 } else {\r
3290 NewBar32 = NewBar32 & 0xfffffffc;\r
3291 NewBar32 = (~NewBar32) + 1;\r
3292 NewBar32 = NewBar32 & 0x0000ffff;\r
3293 }\r
3294 } else {\r
3295\r
3296 OldBar64 = 0x0;\r
3297 CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
3298 NewBar64 = 0xffffffffffffffffULL;\r
3299\r
3300 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3301 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3302 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
3303\r
3304 if (IsMem) {\r
3305 NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
3306 NewBar64 = (~NewBar64) + 1;\r
3307\r
3308 } else {\r
3309 NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
3310 NewBar64 = (~NewBar64) + 1;\r
3311 NewBar64 = NewBar64 & 0x000000000000ffff;\r
3312 }\r
3313 }\r
3314 //\r
3315 // Enable io & mem access\r
3316 //\r
3317 RegAddress = Address | INDEX_OF (Command);\r
3318 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r
3319\r
3320 if (IsMem) {\r
3321 if (IsBar32) {\r
3322 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
3323 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
3324\r
3325 } else {\r
3326 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
3327 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
3328 ShellPrintEx (-1, -1, L" ");\r
3329 ShellPrintHiiEx(-1, -1, NULL,\r
3330 STRING_TOKEN (STR_PCI2_RSHIFT),\r
3331 gShellDebug1HiiHandle,\r
3332 (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
3333 );\r
3334 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
3335\r
3336 }\r
3337 } else {\r
3338 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
3339 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
3340 }\r
3341\r
3342 return EFI_SUCCESS;\r
3343}\r
3344\r
3345/**\r
3346 Explain the cardbus specific part of data in PCI configuration space.\r
3347\r
3348 @param[in] CardBus CardBus specific region of PCI configuration space.\r
3349 @param[in] Address Address used to access configuration space of this PCI device.\r
3350 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3351\r
3352 @retval EFI_SUCCESS The command completed successfully.\r
3353**/\r
3354EFI_STATUS\r
3355PciExplainCardBusData (\r
3356 IN PCI_CARDBUS_HEADER *CardBus,\r
3357 IN UINT64 Address,\r
3358 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3359 )\r
3360{\r
3361 BOOLEAN Io32Bit;\r
3362 PCI_CARDBUS_DATA *CardBusData;\r
3363\r
3364 ShellPrintHiiEx(-1, -1, NULL,\r
3365 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
3366 gShellDebug1HiiHandle,\r
3367 INDEX_OF (&(CardBus->CardBusSocketReg)),\r
3368 CardBus->CardBusSocketReg\r
3369 );\r
3370\r
3371 //\r
3372 // Print Secondary Status\r
3373 //\r
3374 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r
3375\r
3376 //\r
3377 // Print Bus Numbers(Primary bus number, CardBus bus number, and\r
3378 // Subordinate bus number\r
3379 //\r
3380 ShellPrintHiiEx(-1, -1, NULL,\r
3381 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
3382 gShellDebug1HiiHandle,\r
3383 INDEX_OF (&(CardBus->PciBusNumber)),\r
3384 INDEX_OF (&(CardBus->CardBusBusNumber)),\r
3385 INDEX_OF (&(CardBus->SubordinateBusNumber))\r
3386 );\r
3387\r
3388 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
3389\r
3390 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
3391 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
3392 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
3393\r
3394 //\r
3395 // Print CardBus Latency Timer\r
3396 //\r
3397 ShellPrintHiiEx(-1, -1, NULL,\r
3398 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
3399 gShellDebug1HiiHandle,\r
3400 INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
3401 CardBus->CardBusLatencyTimer\r
3402 );\r
3403\r
3404 //\r
3405 // Print Memory/Io ranges this cardbus bridge forwards\r
3406 //\r
3407 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
3408 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
3409\r
3410 ShellPrintHiiEx(-1, -1, NULL,\r
3411 STRING_TOKEN (STR_PCI2_MEM_3),\r
3412 gShellDebug1HiiHandle,\r
3413 INDEX_OF (&(CardBus->MemoryBase0)),\r
3414 CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r
3415 CardBus->MemoryBase0 & 0xfffff000,\r
3416 CardBus->MemoryLimit0 | 0x00000fff\r
3417 );\r
3418\r
3419 ShellPrintHiiEx(-1, -1, NULL,\r
3420 STRING_TOKEN (STR_PCI2_MEM_3),\r
3421 gShellDebug1HiiHandle,\r
3422 INDEX_OF (&(CardBus->MemoryBase1)),\r
3423 CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r
3424 CardBus->MemoryBase1 & 0xfffff000,\r
3425 CardBus->MemoryLimit1 | 0x00000fff\r
3426 );\r
3427\r
3428 Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
3429 ShellPrintHiiEx(-1, -1, NULL,\r
3430 STRING_TOKEN (STR_PCI2_IO_2),\r
3431 gShellDebug1HiiHandle,\r
3432 INDEX_OF (&(CardBus->IoBase0)),\r
3433 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3434 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
3435 (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
3436 );\r
3437\r
3438 Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
3439 ShellPrintHiiEx(-1, -1, NULL,\r
3440 STRING_TOKEN (STR_PCI2_IO_2),\r
3441 gShellDebug1HiiHandle,\r
3442 INDEX_OF (&(CardBus->IoBase1)),\r
3443 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3444 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
3445 (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
3446 );\r
3447\r
3448 //\r
3449 // Print register Interrupt Line & PIN\r
3450 //\r
3451 ShellPrintHiiEx(-1, -1, NULL,\r
3452 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
3453 gShellDebug1HiiHandle,\r
3454 INDEX_OF (&(CardBus->InterruptLine)),\r
3455 CardBus->InterruptLine,\r
3456 INDEX_OF (&(CardBus->InterruptPin)),\r
3457 CardBus->InterruptPin\r
3458 );\r
3459\r
3460 //\r
3461 // Print register Bridge Control\r
3462 //\r
3463 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r
3464\r
3465 //\r
3466 // Print some registers in data region of PCI configuration space for cardbus\r
3467 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
3468 // Address.\r
3469 //\r
3470 CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
3471\r
3472 ShellPrintHiiEx(-1, -1, NULL,\r
3473 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
3474 gShellDebug1HiiHandle,\r
3475 INDEX_OF (&(CardBusData->SubVendorId)),\r
3476 CardBusData->SubVendorId,\r
3477 INDEX_OF (&(CardBusData->SubSystemId)),\r
3478 CardBusData->SubSystemId\r
3479 );\r
3480\r
3481 ShellPrintHiiEx(-1, -1, NULL,\r
3482 STRING_TOKEN (STR_PCI2_OPTIONAL),\r
3483 gShellDebug1HiiHandle,\r
3484 INDEX_OF (&(CardBusData->LegacyBase)),\r
3485 CardBusData->LegacyBase\r
3486 );\r
3487\r
3488 return EFI_SUCCESS;\r
3489}\r
3490\r
3491/**\r
3492 Explain each meaningful bit of register Status. The definition of Status is\r
3493 slightly different depending on the PCI header type.\r
3494\r
3495 @param[in] Status Points to the content of register Status.\r
3496 @param[in] MainStatus Indicates if this register is main status(not secondary\r
3497 status).\r
3498 @param[in] HeaderType Header type of this PCI device.\r
3499\r
3500 @retval EFI_SUCCESS The command completed successfully.\r
3501**/\r
3502EFI_STATUS\r
3503PciExplainStatus (\r
3504 IN UINT16 *Status,\r
3505 IN BOOLEAN MainStatus,\r
3506 IN PCI_HEADER_TYPE HeaderType\r
3507 )\r
3508{\r
3509 if (MainStatus) {\r
3510 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3511\r
3512 } else {\r
3513 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3514 }\r
3515\r
3516 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
3517\r
3518 //\r
3519 // Bit 5 is meaningless for CardBus Bridge\r
3520 //\r
3521 if (HeaderType == PciCardBusBridge) {\r
3522 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3523\r
3524 } else {\r
3525 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3526 }\r
3527\r
3528 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
3529\r
3530 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
3531 //\r
3532 // Bit 9 and bit 10 together decides the DEVSEL timing\r
3533 //\r
3534 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
3535 if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
3536 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
3537\r
3538 } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
3539 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
3540\r
3541 } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
3542 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
3543\r
3544 } else {\r
3545 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
3546 }\r
3547\r
3548 ShellPrintHiiEx(-1, -1, NULL,\r
3549 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
3550 gShellDebug1HiiHandle,\r
3551 (*Status & PCI_BIT_11) != 0\r
3552 );\r
3553\r
3554 ShellPrintHiiEx(-1, -1, NULL,\r
3555 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
3556 gShellDebug1HiiHandle,\r
3557 (*Status & PCI_BIT_12) != 0\r
3558 );\r
3559\r
3560 ShellPrintHiiEx(-1, -1, NULL,\r
3561 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
3562 gShellDebug1HiiHandle,\r
3563 (*Status & PCI_BIT_13) != 0\r
3564 );\r
3565\r
3566 if (MainStatus) {\r
3567 ShellPrintHiiEx(-1, -1, NULL,\r
3568 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
3569 gShellDebug1HiiHandle,\r
3570 (*Status & PCI_BIT_14) != 0\r
3571 );\r
3572\r
3573 } else {\r
3574 ShellPrintHiiEx(-1, -1, NULL,\r
3575 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
3576 gShellDebug1HiiHandle,\r
3577 (*Status & PCI_BIT_14) != 0\r
3578 );\r
3579 }\r
3580\r
3581 ShellPrintHiiEx(-1, -1, NULL,\r
3582 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
3583 gShellDebug1HiiHandle,\r
3584 (*Status & PCI_BIT_15) != 0\r
3585 );\r
3586\r
3587 return EFI_SUCCESS;\r
3588}\r
3589\r
3590/**\r
3591 Explain each meaningful bit of register Command.\r
3592\r
3593 @param[in] Command Points to the content of register Command.\r
3594\r
3595 @retval EFI_SUCCESS The command completed successfully.\r
3596**/\r
3597EFI_STATUS\r
3598PciExplainCommand (\r
3599 IN UINT16 *Command\r
3600 )\r
3601{\r
3602 //\r
3603 // Print the binary value of register Command\r
3604 //\r
3605 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
3606\r
3607 //\r
3608 // Explain register Command bit by bit\r
3609 //\r
3610 ShellPrintHiiEx(-1, -1, NULL,\r
3611 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
3612 gShellDebug1HiiHandle,\r
3613 (*Command & PCI_BIT_0) != 0\r
3614 );\r
3615\r
3616 ShellPrintHiiEx(-1, -1, NULL,\r
3617 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
3618 gShellDebug1HiiHandle,\r
3619 (*Command & PCI_BIT_1) != 0\r
3620 );\r
3621\r
3622 ShellPrintHiiEx(-1, -1, NULL,\r
3623 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
3624 gShellDebug1HiiHandle,\r
3625 (*Command & PCI_BIT_2) != 0\r
3626 );\r
3627\r
3628 ShellPrintHiiEx(-1, -1, NULL,\r
3629 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
3630 gShellDebug1HiiHandle,\r
3631 (*Command & PCI_BIT_3) != 0\r
3632 );\r
3633\r
3634 ShellPrintHiiEx(-1, -1, NULL,\r
3635 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
3636 gShellDebug1HiiHandle,\r
3637 (*Command & PCI_BIT_4) != 0\r
3638 );\r
3639\r
3640 ShellPrintHiiEx(-1, -1, NULL,\r
3641 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
3642 gShellDebug1HiiHandle,\r
3643 (*Command & PCI_BIT_5) != 0\r
3644 );\r
3645\r
3646 ShellPrintHiiEx(-1, -1, NULL,\r
3647 STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
3648 gShellDebug1HiiHandle,\r
3649 (*Command & PCI_BIT_6) != 0\r
3650 );\r
3651\r
3652 ShellPrintHiiEx(-1, -1, NULL,\r
3653 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
3654 gShellDebug1HiiHandle,\r
3655 (*Command & PCI_BIT_7) != 0\r
3656 );\r
3657\r
3658 ShellPrintHiiEx(-1, -1, NULL,\r
3659 STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
3660 gShellDebug1HiiHandle,\r
3661 (*Command & PCI_BIT_8) != 0\r
3662 );\r
3663\r
3664 ShellPrintHiiEx(-1, -1, NULL,\r
3665 STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
3666 gShellDebug1HiiHandle,\r
3667 (*Command & PCI_BIT_9) != 0\r
3668 );\r
3669\r
3670 return EFI_SUCCESS;\r
3671}\r
3672\r
3673/**\r
3674 Explain each meaningful bit of register Bridge Control.\r
3675\r
3676 @param[in] BridgeControl Points to the content of register Bridge Control.\r
3677 @param[in] HeaderType The headertype.\r
3678\r
3679 @retval EFI_SUCCESS The command completed successfully.\r
3680**/\r
3681EFI_STATUS\r
3682PciExplainBridgeControl (\r
3683 IN UINT16 *BridgeControl,\r
3684 IN PCI_HEADER_TYPE HeaderType\r
3685 )\r
3686{\r
3687 ShellPrintHiiEx(-1, -1, NULL,\r
3688 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
3689 gShellDebug1HiiHandle,\r
3690 INDEX_OF (BridgeControl),\r
3691 *BridgeControl\r
3692 );\r
3693\r
3694 ShellPrintHiiEx(-1, -1, NULL,\r
3695 STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
3696 gShellDebug1HiiHandle,\r
3697 (*BridgeControl & PCI_BIT_0) != 0\r
3698 );\r
3699 ShellPrintHiiEx(-1, -1, NULL,\r
3700 STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
3701 gShellDebug1HiiHandle,\r
3702 (*BridgeControl & PCI_BIT_1) != 0\r
3703 );\r
3704 ShellPrintHiiEx(-1, -1, NULL,\r
3705 STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
3706 gShellDebug1HiiHandle,\r
3707 (*BridgeControl & PCI_BIT_2) != 0\r
3708 );\r
3709 ShellPrintHiiEx(-1, -1, NULL,\r
3710 STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
3711 gShellDebug1HiiHandle,\r
3712 (*BridgeControl & PCI_BIT_3) != 0\r
3713 );\r
3714 ShellPrintHiiEx(-1, -1, NULL,\r
3715 STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
3716 gShellDebug1HiiHandle,\r
3717 (*BridgeControl & PCI_BIT_5) != 0\r
3718 );\r
3719\r
3720 //\r
3721 // Register Bridge Control has some slight differences between P2P bridge\r
3722 // and Cardbus bridge from bit 6 to bit 11.\r
3723 //\r
3724 if (HeaderType == PciP2pBridge) {\r
3725 ShellPrintHiiEx(-1, -1, NULL,\r
3726 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
3727 gShellDebug1HiiHandle,\r
3728 (*BridgeControl & PCI_BIT_6) != 0\r
3729 );\r
3730 ShellPrintHiiEx(-1, -1, NULL,\r
3731 STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
3732 gShellDebug1HiiHandle,\r
3733 (*BridgeControl & PCI_BIT_7) != 0\r
3734 );\r
3735 ShellPrintHiiEx(-1, -1, NULL,\r
3736 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
3737 gShellDebug1HiiHandle,\r
3738 (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
3739 );\r
3740 ShellPrintHiiEx(-1, -1, NULL,\r
3741 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
3742 gShellDebug1HiiHandle,\r
3743 (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
3744 );\r
3745 ShellPrintHiiEx(-1, -1, NULL,\r
3746 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
3747 gShellDebug1HiiHandle,\r
3748 (*BridgeControl & PCI_BIT_10) != 0\r
3749 );\r
3750 ShellPrintHiiEx(-1, -1, NULL,\r
3751 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
3752 gShellDebug1HiiHandle,\r
3753 (*BridgeControl & PCI_BIT_11) != 0\r
3754 );\r
3755\r
3756 } else {\r
3757 ShellPrintHiiEx(-1, -1, NULL,\r
3758 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
3759 gShellDebug1HiiHandle,\r
3760 (*BridgeControl & PCI_BIT_6) != 0\r
3761 );\r
3762 ShellPrintHiiEx(-1, -1, NULL,\r
3763 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
3764 gShellDebug1HiiHandle,\r
3765 (*BridgeControl & PCI_BIT_7) != 0\r
3766 );\r
3767 ShellPrintHiiEx(-1, -1, NULL,\r
3768 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
3769 gShellDebug1HiiHandle,\r
3770 (*BridgeControl & PCI_BIT_10) != 0\r
3771 );\r
3772 }\r
3773\r
3774 return EFI_SUCCESS;\r
3775}\r
3776\r
3777/**\r
3778 Print each capability structure.\r
3779\r
3780 @param[in] IoDev The pointer to the deivce.\r
3781 @param[in] Address The address to start at.\r
3782 @param[in] CapPtr The offset from the address.\r
3783\r
3784 @retval EFI_SUCCESS The operation was successful.\r
3785**/\r
3786EFI_STATUS\r
3787PciExplainCapabilityStruct (\r
3788 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3789 IN UINT64 Address,\r
3790 IN UINT8 CapPtr\r
3791 )\r
3792{\r
3793 UINT8 CapabilityPtr;\r
3794 UINT16 CapabilityEntry;\r
3795 UINT8 CapabilityID;\r
3796 UINT64 RegAddress;\r
3797\r
3798 CapabilityPtr = CapPtr;\r
3799\r
3800 //\r
3801 // Go through the Capability list\r
3802 //\r
3803 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
3804 RegAddress = Address + CapabilityPtr;\r
3805 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
3806\r
3807 CapabilityID = (UINT8) CapabilityEntry;\r
3808\r
3809 //\r
3810 // Explain PciExpress data\r
3811 //\r
3812 if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
3813 PciExplainPciExpress (IoDev, Address, CapabilityPtr);\r
3814 return EFI_SUCCESS;\r
3815 }\r
3816 //\r
3817 // Explain other capabilities here\r
3818 //\r
3819 CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
3820 }\r
3821\r
3822 return EFI_SUCCESS;\r
3823}\r
3824\r
3825/**\r
3826 Print out information of the capability information.\r
3827\r
3828 @param[in] PciExpressCap The pointer to the structure about the device.\r
3829\r
3830 @retval EFI_SUCCESS The operation was successful.\r
3831**/\r
3832EFI_STATUS\r
3833ExplainPcieCapReg (\r
3834 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3835 )\r
3836{\r
3837 UINT16 PcieCapReg;\r
3838 CHAR16 *DevicePortType;\r
3839\r
3840 PcieCapReg = PciExpressCap->PcieCapReg;\r
3841 ShellPrintEx (-1, -1,\r
3842 L" Capability Version(3:0): %E0x%04x%N\r\n",\r
3843 PCIE_CAP_VERSION (PcieCapReg)\r
3844 );\r
3845 if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
3846 DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
3847 } else {\r
3848 DevicePortType = L"Unknown Type";\r
3849 }\r
3850 ShellPrintEx (-1, -1,\r
3851 L" Device/PortType(7:4): %E%s%N\r\n",\r
3852 DevicePortType\r
3853 );\r
3854 //\r
3855 // 'Slot Implemented' is only valid for:\r
3856 // a) Root Port of PCI Express Root Complex, or\r
3857 // b) Downstream Port of PCI Express Switch\r
3858 //\r
3859 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
3860 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
3861 ShellPrintEx (-1, -1,\r
3862 L" Slot Implemented(8): %E%d%N\r\n",\r
3863 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
3864 );\r
3865 }\r
3866 ShellPrintEx (-1, -1,\r
3867 L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r
3868 PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
3869 );\r
3870 return EFI_SUCCESS;\r
3871}\r
3872\r
3873/**\r
3874 Print out information of the device capability information.\r
3875\r
3876 @param[in] PciExpressCap The pointer to the structure about the device.\r
3877\r
3878 @retval EFI_SUCCESS The operation was successful.\r
3879**/\r
3880EFI_STATUS\r
3881ExplainPcieDeviceCap (\r
3882 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3883 )\r
3884{\r
3885 UINT16 PcieCapReg;\r
3886 UINT32 PcieDeviceCap;\r
3887 UINT8 DevicePortType;\r
3888 UINT8 L0sLatency;\r
3889 UINT8 L1Latency;\r
3890\r
3891 PcieCapReg = PciExpressCap->PcieCapReg;\r
3892 PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
3893 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
3894 ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r
3895 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
3896 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
3897 } else {\r
3898 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
3899 }\r
3900 ShellPrintEx (-1, -1,\r
3901 L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r
3902 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
3903 );\r
3904 ShellPrintEx (-1, -1,\r
3905 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r
3906 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
3907 );\r
3908 //\r
3909 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
3910 //\r
3911 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
3912 L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
3913 L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
3914 ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r
3915 if (L0sLatency < 4) {\r
3916 ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r
3917 } else {\r
3918 if (L0sLatency < 7) {\r
3919 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r
3920 } else {\r
3921 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
3922 }\r
3923 }\r
3924 ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r
3925 if (L1Latency < 7) {\r
3926 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r
3927 } else {\r
3928 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
3929 }\r
3930 }\r
3931 ShellPrintEx (-1, -1,\r
3932 L" Role-based Error Reporting(15): %E%d%N\r\n",\r
3933 PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
3934 );\r
3935 //\r
3936 // Only valid for Upstream Port:\r
3937 // a) Captured Slot Power Limit Value\r
3938 // b) Captured Slot Power Scale\r
3939 //\r
3940 if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
3941 ShellPrintEx (-1, -1,\r
3942 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r
3943 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
3944 );\r
3945 ShellPrintEx (-1, -1,\r
3946 L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r
3947 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
3948 );\r
3949 }\r
3950 //\r
3951 // Function Level Reset Capability is only valid for Endpoint\r
3952 //\r
3953 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
3954 ShellPrintEx (-1, -1,\r
3955 L" Function Level Reset Capability(28): %E%d%N\r\n",\r
3956 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
3957 );\r
3958 }\r
3959 return EFI_SUCCESS;\r
3960}\r
3961\r
3962/**\r
3963 Print out information of the device control information.\r
3964\r
3965 @param[in] PciExpressCap The pointer to the structure about the device.\r
3966\r
3967 @retval EFI_SUCCESS The operation was successful.\r
3968**/\r
3969EFI_STATUS\r
3970ExplainPcieDeviceControl (\r
3971 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3972 )\r
3973{\r
3974 UINT16 PcieCapReg;\r
3975 UINT16 PcieDeviceControl;\r
3976\r
3977 PcieCapReg = PciExpressCap->PcieCapReg;\r
3978 PcieDeviceControl = PciExpressCap->DeviceControl;\r
3979 ShellPrintEx (-1, -1,\r
3980 L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r
3981 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3982 );\r
3983 ShellPrintEx (-1, -1,\r
3984 L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r
3985 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3986 );\r
3987 ShellPrintEx (-1, -1,\r
3988 L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r
3989 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3990 );\r
3991 ShellPrintEx (-1, -1,\r
3992 L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r
3993 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
3994 );\r
3995 ShellPrintEx (-1, -1,\r
3996 L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r
3997 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
3998 );\r
3999 ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r
4000 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
4001 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
4002 } else {\r
4003 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
4004 }\r
4005 ShellPrintEx (-1, -1,\r
4006 L" Extended Tag Field Enable(8): %E%d%N\r\n",\r
4007 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
4008 );\r
4009 ShellPrintEx (-1, -1,\r
4010 L" Phantom Functions Enable(9): %E%d%N\r\n",\r
4011 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
4012 );\r
4013 ShellPrintEx (-1, -1,\r
4014 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r
4015 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
4016 );\r
4017 ShellPrintEx (-1, -1,\r
4018 L" Enable No Snoop(11): %E%d%N\r\n",\r
4019 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
4020 );\r
4021 ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r
4022 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
4023 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
4024 } else {\r
4025 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
4026 }\r
4027 //\r
4028 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
4029 //\r
4030 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
4031 ShellPrintEx (-1, -1,\r
4032 L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r
4033 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
4034 );\r
4035 }\r
4036 return EFI_SUCCESS;\r
4037}\r
4038\r
4039/**\r
4040 Print out information of the device status information.\r
4041\r
4042 @param[in] PciExpressCap The pointer to the structure about the device.\r
4043\r
4044 @retval EFI_SUCCESS The operation was successful.\r
4045**/\r
4046EFI_STATUS\r
4047ExplainPcieDeviceStatus (\r
4048 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4049 )\r
4050{\r
4051 UINT16 PcieDeviceStatus;\r
4052\r
4053 PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
4054 ShellPrintEx (-1, -1,\r
4055 L" Correctable Error Detected(0): %E%d%N\r\n",\r
4056 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
4057 );\r
4058 ShellPrintEx (-1, -1,\r
4059 L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r
4060 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
4061 );\r
4062 ShellPrintEx (-1, -1,\r
4063 L" Fatal Error Detected(2): %E%d%N\r\n",\r
4064 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
4065 );\r
4066 ShellPrintEx (-1, -1,\r
4067 L" Unsupported Request Detected(3): %E%d%N\r\n",\r
4068 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
4069 );\r
4070 ShellPrintEx (-1, -1,\r
4071 L" AUX Power Detected(4): %E%d%N\r\n",\r
4072 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
4073 );\r
4074 ShellPrintEx (-1, -1,\r
4075 L" Transactions Pending(5): %E%d%N\r\n",\r
4076 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
4077 );\r
4078 return EFI_SUCCESS;\r
4079}\r
4080\r
4081/**\r
4082 Print out information of the device link information.\r
4083\r
4084 @param[in] PciExpressCap The pointer to the structure about the device.\r
4085\r
4086 @retval EFI_SUCCESS The operation was successful.\r
4087**/\r
4088EFI_STATUS\r
4089ExplainPcieLinkCap (\r
4090 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4091 )\r
4092{\r
4093 UINT32 PcieLinkCap;\r
4094 CHAR16 *MaxLinkSpeed;\r
4095 CHAR16 *AspmValue;\r
4096\r
4097 PcieLinkCap = PciExpressCap->LinkCap;\r
4098 switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r
4099 case 1:\r
4100 MaxLinkSpeed = L"2.5 GT/s";\r
4101 break;\r
4102 case 2:\r
4103 MaxLinkSpeed = L"5.0 GT/s";\r
4104 break;\r
4105 case 3:\r
4106 MaxLinkSpeed = L"8.0 GT/s";\r
4107 break;\r
4108 default:\r
4109 MaxLinkSpeed = L"Unknown";\r
4110 break;\r
4111 }\r
4112 ShellPrintEx (-1, -1,\r
4113 L" Maximum Link Speed(3:0): %E%s%N\r\n",\r
4114 MaxLinkSpeed\r
4115 );\r
4116 ShellPrintEx (-1, -1,\r
4117 L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r
4118 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
4119 );\r
4120 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
4121 case 0:\r
4122 AspmValue = L"Not";\r
4123 break;\r
4124 case 1:\r
4125 AspmValue = L"L0s";\r
4126 break;\r
4127 case 2:\r
4128 AspmValue = L"L1";\r
4129 break;\r
4130 case 3:\r
4131 AspmValue = L"L0s and L1";\r
4132 break;\r
4133 default:\r
4134 AspmValue = L"Reserved";\r
4135 break;\r
4136 }\r
4137 ShellPrintEx (-1, -1,\r
4138 L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r
4139 AspmValue\r
4140 );\r
4141 ShellPrintEx (-1, -1,\r
4142 L" L0s Exit Latency(14:12): %E%s%N\r\n",\r
4143 L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
4144 );\r
4145 ShellPrintEx (-1, -1,\r
4146 L" L1 Exit Latency(17:15): %E%s%N\r\n",\r
4147 L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
4148 );\r
4149 ShellPrintEx (-1, -1,\r
4150 L" Clock Power Management(18): %E%d%N\r\n",\r
4151 PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
4152 );\r
4153 ShellPrintEx (-1, -1,\r
4154 L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r
4155 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
4156 );\r
4157 ShellPrintEx (-1, -1,\r
4158 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r
4159 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
4160 );\r
4161 ShellPrintEx (-1, -1,\r
4162 L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r
4163 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
4164 );\r
4165 ShellPrintEx (-1, -1,\r
4166 L" Port Number(31:24): %E0x%02x%N\r\n",\r
4167 PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
4168 );\r
4169 return EFI_SUCCESS;\r
4170}\r
4171\r
4172/**\r
4173 Print out information of the device link control information.\r
4174\r
4175 @param[in] PciExpressCap The pointer to the structure about the device.\r
4176\r
4177 @retval EFI_SUCCESS The operation was successful.\r
4178**/\r
4179EFI_STATUS\r
4180ExplainPcieLinkControl (\r
4181 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4182 )\r
4183{\r
4184 UINT16 PcieLinkControl;\r
4185 UINT8 DevicePortType;\r
4186\r
4187 PcieLinkControl = PciExpressCap->LinkControl;\r
4188 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
4189 ShellPrintEx (-1, -1,\r
4190 L" Active State Power Management Control(1:0): %E%s%N\r\n",\r
4191 ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
4192 );\r
4193 //\r
4194 // RCB is not applicable to switches\r
4195 //\r
4196 if (!IS_PCIE_SWITCH(DevicePortType)) {\r
4197 ShellPrintEx (-1, -1,\r
4198 L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r
4199 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
4200 );\r
4201 }\r
4202 //\r
4203 // Link Disable is reserved on\r
4204 // a) Endpoints\r
4205 // b) PCI Express to PCI/PCI-X bridges\r
4206 // c) Upstream Ports of Switches\r
4207 //\r
4208 if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
4209 DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
4210 DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
4211 ShellPrintEx (-1, -1,\r
4212 L" Link Disable(4): %E%d%N\r\n",\r
4213 PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
4214 );\r
4215 }\r
4216 ShellPrintEx (-1, -1,\r
4217 L" Common Clock Configuration(6): %E%d%N\r\n",\r
4218 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
4219 );\r
4220 ShellPrintEx (-1, -1,\r
4221 L" Extended Synch(7): %E%d%N\r\n",\r
4222 PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
4223 );\r
4224 ShellPrintEx (-1, -1,\r
4225 L" Enable Clock Power Management(8): %E%d%N\r\n",\r
4226 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
4227 );\r
4228 ShellPrintEx (-1, -1,\r
4229 L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r
4230 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
4231 );\r
4232 ShellPrintEx (-1, -1,\r
4233 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r
4234 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
4235 );\r
4236 ShellPrintEx (-1, -1,\r
4237 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r
4238 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
4239 );\r
4240 return EFI_SUCCESS;\r
4241}\r
4242\r
4243/**\r
4244 Print out information of the device link status information.\r
4245\r
4246 @param[in] PciExpressCap The pointer to the structure about the device.\r
4247\r
4248 @retval EFI_SUCCESS The operation was successful.\r
4249**/\r
4250EFI_STATUS\r
4251ExplainPcieLinkStatus (\r
4252 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4253 )\r
4254{\r
4255 UINT16 PcieLinkStatus;\r
4256 CHAR16 *CurLinkSpeed;\r
4257\r
4258 PcieLinkStatus = PciExpressCap->LinkStatus;\r
4259 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
4260 case 1:\r
4261 CurLinkSpeed = L"2.5 GT/s";\r
4262 break;\r
4263 case 2:\r
4264 CurLinkSpeed = L"5.0 GT/s";\r
4265 break;\r
4266 case 3:\r
4267 CurLinkSpeed = L"8.0 GT/s";\r
4268 break;\r
4269 default:\r
4270 CurLinkSpeed = L"Reserved";\r
4271 break;\r
4272 }\r
4273 ShellPrintEx (-1, -1,\r
4274 L" Current Link Speed(3:0): %E%s%N\r\n",\r
4275 CurLinkSpeed\r
4276 );\r
4277 ShellPrintEx (-1, -1,\r
4278 L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r
4279 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
4280 );\r
4281 ShellPrintEx (-1, -1,\r
4282 L" Link Training(11): %E%d%N\r\n",\r
4283 PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
4284 );\r
4285 ShellPrintEx (-1, -1,\r
4286 L" Slot Clock Configuration(12): %E%d%N\r\n",\r
4287 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
4288 );\r
4289 ShellPrintEx (-1, -1,\r
4290 L" Data Link Layer Link Active(13): %E%d%N\r\n",\r
4291 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
4292 );\r
4293 ShellPrintEx (-1, -1,\r
4294 L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r
4295 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
4296 );\r
4297 ShellPrintEx (-1, -1,\r
4298 L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r
4299 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
4300 );\r
4301 return EFI_SUCCESS;\r
4302}\r
4303\r
4304/**\r
4305 Print out information of the device slot information.\r
4306\r
4307 @param[in] PciExpressCap The pointer to the structure about the device.\r
4308\r
4309 @retval EFI_SUCCESS The operation was successful.\r
4310**/\r
4311EFI_STATUS\r
4312ExplainPcieSlotCap (\r
4313 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4314 )\r
4315{\r
4316 UINT32 PcieSlotCap;\r
4317\r
4318 PcieSlotCap = PciExpressCap->SlotCap;\r
4319\r
4320 ShellPrintEx (-1, -1,\r
4321 L" Attention Button Present(0): %E%d%N\r\n",\r
4322 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
4323 );\r
4324 ShellPrintEx (-1, -1,\r
4325 L" Power Controller Present(1): %E%d%N\r\n",\r
4326 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
4327 );\r
4328 ShellPrintEx (-1, -1,\r
4329 L" MRL Sensor Present(2): %E%d%N\r\n",\r
4330 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
4331 );\r
4332 ShellPrintEx (-1, -1,\r
4333 L" Attention Indicator Present(3): %E%d%N\r\n",\r
4334 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
4335 );\r
4336 ShellPrintEx (-1, -1,\r
4337 L" Power Indicator Present(4): %E%d%N\r\n",\r
4338 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
4339 );\r
4340 ShellPrintEx (-1, -1,\r
4341 L" Hot-Plug Surprise(5): %E%d%N\r\n",\r
4342 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
4343 );\r
4344 ShellPrintEx (-1, -1,\r
4345 L" Hot-Plug Capable(6): %E%d%N\r\n",\r
4346 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
4347 );\r
4348 ShellPrintEx (-1, -1,\r
4349 L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r
4350 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
4351 );\r
4352 ShellPrintEx (-1, -1,\r
4353 L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r
4354 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
4355 );\r
4356 ShellPrintEx (-1, -1,\r
4357 L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r
4358 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
4359 );\r
4360 ShellPrintEx (-1, -1,\r
4361 L" No Command Completed Support(18): %E%d%N\r\n",\r
4362 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
4363 );\r
4364 ShellPrintEx (-1, -1,\r
4365 L" Physical Slot Number(31:19): %E%d%N\r\n",\r
4366 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
4367 );\r
4368\r
4369 return EFI_SUCCESS;\r
4370}\r
4371\r
4372/**\r
4373 Print out information of the device slot control information.\r
4374\r
4375 @param[in] PciExpressCap The pointer to the structure about the device.\r
4376\r
4377 @retval EFI_SUCCESS The operation was successful.\r
4378**/\r
4379EFI_STATUS\r
4380ExplainPcieSlotControl (\r
4381 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4382 )\r
4383{\r
4384 UINT16 PcieSlotControl;\r
4385\r
4386 PcieSlotControl = PciExpressCap->SlotControl;\r
4387 ShellPrintEx (-1, -1,\r
4388 L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r
4389 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
4390 );\r
4391 ShellPrintEx (-1, -1,\r
4392 L" Power Fault Detected Enable(1): %E%d%N\r\n",\r
4393 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
4394 );\r
4395 ShellPrintEx (-1, -1,\r
4396 L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r
4397 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
4398 );\r
4399 ShellPrintEx (-1, -1,\r
4400 L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r
4401 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
4402 );\r
4403 ShellPrintEx (-1, -1,\r
4404 L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r
4405 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
4406 );\r
4407 ShellPrintEx (-1, -1,\r
4408 L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r
4409 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
4410 );\r
4411 ShellPrintEx (-1, -1,\r
4412 L" Attention Indicator Control(7:6): %E%s%N\r\n",\r
4413 IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
4414 );\r
4415 ShellPrintEx (-1, -1,\r
4416 L" Power Indicator Control(9:8): %E%s%N\r\n",\r
4417 IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
4418 );\r
4419 ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r
4420 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
4421 ShellPrintEx (-1, -1, L"Off%N\r\n");\r
4422 } else {\r
4423 ShellPrintEx (-1, -1, L"On%N\r\n");\r
4424 }\r
4425 ShellPrintEx (-1, -1,\r
4426 L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r
4427 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
4428 );\r
4429 ShellPrintEx (-1, -1,\r
4430 L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r
4431 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
4432 );\r
4433 return EFI_SUCCESS;\r
4434}\r
4435\r
4436/**\r
4437 Print out information of the device slot status information.\r
4438\r
4439 @param[in] PciExpressCap The pointer to the structure about the device.\r
4440\r
4441 @retval EFI_SUCCESS The operation was successful.\r
4442**/\r
4443EFI_STATUS\r
4444ExplainPcieSlotStatus (\r
4445 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4446 )\r
4447{\r
4448 UINT16 PcieSlotStatus;\r
4449\r
4450 PcieSlotStatus = PciExpressCap->SlotStatus;\r
4451\r
4452 ShellPrintEx (-1, -1,\r
4453 L" Attention Button Pressed(0): %E%d%N\r\n",\r
4454 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
4455 );\r
4456 ShellPrintEx (-1, -1,\r
4457 L" Power Fault Detected(1): %E%d%N\r\n",\r
4458 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
4459 );\r
4460 ShellPrintEx (-1, -1,\r
4461 L" MRL Sensor Changed(2): %E%d%N\r\n",\r
4462 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
4463 );\r
4464 ShellPrintEx (-1, -1,\r
4465 L" Presence Detect Changed(3): %E%d%N\r\n",\r
4466 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
4467 );\r
4468 ShellPrintEx (-1, -1,\r
4469 L" Command Completed(4): %E%d%N\r\n",\r
4470 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
4471 );\r
4472 ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r
4473 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
4474 ShellPrintEx (-1, -1, L" Opened%N\r\n");\r
4475 } else {\r
4476 ShellPrintEx (-1, -1, L" Closed%N\r\n");\r
4477 }\r
4478 ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r
4479 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
4480 ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r
4481 } else {\r
4482 ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r
4483 }\r
4484 ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
4485 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
4486 ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r
4487 } else {\r
4488 ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r
4489 }\r
4490 ShellPrintEx (-1, -1,\r
4491 L" Data Link Layer State Changed(8): %E%d%N\r\n",\r
4492 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
4493 );\r
4494 return EFI_SUCCESS;\r
4495}\r
4496\r
4497/**\r
4498 Print out information of the device root information.\r
4499\r
4500 @param[in] PciExpressCap The pointer to the structure about the device.\r
4501\r
4502 @retval EFI_SUCCESS The operation was successful.\r
4503**/\r
4504EFI_STATUS\r
4505ExplainPcieRootControl (\r
4506 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4507 )\r
4508{\r
4509 UINT16 PcieRootControl;\r
4510\r
4511 PcieRootControl = PciExpressCap->RootControl;\r
4512\r
4513 ShellPrintEx (-1, -1,\r
4514 L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r
4515 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
4516 );\r
4517 ShellPrintEx (-1, -1,\r
4518 L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r
4519 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
4520 );\r
4521 ShellPrintEx (-1, -1,\r
4522 L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r
4523 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
4524 );\r
4525 ShellPrintEx (-1, -1,\r
4526 L" PME Interrupt Enable(3): %E%d%N\r\n",\r
4527 PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
4528 );\r
4529 ShellPrintEx (-1, -1,\r
4530 L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r
4531 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
4532 );\r
4533\r
4534 return EFI_SUCCESS;\r
4535}\r
4536\r
4537/**\r
4538 Print out information of the device root capability information.\r
4539\r
4540 @param[in] PciExpressCap The pointer to the structure about the device.\r
4541\r
4542 @retval EFI_SUCCESS The operation was successful.\r
4543**/\r
4544EFI_STATUS\r
4545ExplainPcieRootCap (\r
4546 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4547 )\r
4548{\r
4549 UINT16 PcieRootCap;\r
4550\r
4551 PcieRootCap = PciExpressCap->RsvdP;\r
4552\r
4553 ShellPrintEx (-1, -1,\r
4554 L" CRS Software Visibility(0): %E%d%N\r\n",\r
4555 PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
4556 );\r
4557\r
4558 return EFI_SUCCESS;\r
4559}\r
4560\r
4561/**\r
4562 Print out information of the device root status information.\r
4563\r
4564 @param[in] PciExpressCap The pointer to the structure about the device.\r
4565\r
4566 @retval EFI_SUCCESS The operation was successful.\r
4567**/\r
4568EFI_STATUS\r
4569ExplainPcieRootStatus (\r
4570 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4571 )\r
4572{\r
4573 UINT32 PcieRootStatus;\r
4574\r
4575 PcieRootStatus = PciExpressCap->RootStatus;\r
4576\r
4577 ShellPrintEx (-1, -1,\r
4578 L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r
4579 PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
4580 );\r
4581 ShellPrintEx (-1, -1,\r
4582 L" PME Status(16): %E%d%N\r\n",\r
4583 PCIE_CAP_PME_STATUS (PcieRootStatus)\r
4584 );\r
4585 ShellPrintEx (-1, -1,\r
4586 L" PME Pending(17): %E%d%N\r\n",\r
4587 PCIE_CAP_PME_PENDING (PcieRootStatus)\r
4588 );\r
4589 return EFI_SUCCESS;\r
4590}\r
4591\r
4592/**\r
4593 Display Pcie device structure.\r
4594\r
4595 @param[in] IoDev The pointer to the root pci protocol.\r
4596 @param[in] Address The Address to start at.\r
4597 @param[in] CapabilityPtr The offset from the address to start.\r
4598**/\r
4599EFI_STATUS\r
4600PciExplainPciExpress (\r
4601 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
4602 IN UINT64 Address,\r
4603 IN UINT8 CapabilityPtr\r
4604 )\r
4605{\r
4606\r
4607 PCIE_CAP_STURCTURE PciExpressCap;\r
4608 EFI_STATUS Status;\r
4609 UINT64 CapRegAddress;\r
4610 UINT8 Bus;\r
4611 UINT8 Dev;\r
4612 UINT8 Func;\r
4613 UINT8 *ExRegBuffer;\r
4614 UINTN ExtendRegSize;\r
4615 UINT64 Pciex_Address;\r
4616 UINT8 DevicePortType;\r
4617 UINTN Index;\r
4618 UINT8 *RegAddr;\r
4619 UINTN RegValue;\r
4620\r
4621 CapRegAddress = Address + CapabilityPtr;\r
4622 IoDev->Pci.Read (\r
4623 IoDev,\r
4624 EfiPciWidthUint32,\r
4625 CapRegAddress,\r
4626 sizeof (PciExpressCap) / sizeof (UINT32),\r
4627 &PciExpressCap\r
4628 );\r
4629\r
4630 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
4631\r
4632 ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
4633\r
4634 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
4635 if (ShellGetExecutionBreakFlag()) {\r
4636 goto Done;\r
4637 }\r
4638 RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
4639 switch (PcieExplainList[Index].Width) {\r
4640 case FieldWidthUINT8:\r
4641 RegValue = *(UINT8 *) RegAddr;\r
4642 break;\r
4643 case FieldWidthUINT16:\r
4644 RegValue = *(UINT16 *) RegAddr;\r
4645 break;\r
4646 case FieldWidthUINT32:\r
4647 RegValue = *(UINT32 *) RegAddr;\r
4648 break;\r
4649 default:\r
4650 RegValue = 0;\r
4651 break;\r
4652 }\r
4653 ShellPrintHiiEx(-1, -1, NULL,\r
4654 PcieExplainList[Index].Token,\r
4655 gShellDebug1HiiHandle,\r
4656 PcieExplainList[Index].Offset,\r
4657 RegValue\r
4658 );\r
4659 if (PcieExplainList[Index].Func == NULL) {\r
4660 continue;\r
4661 }\r
4662 switch (PcieExplainList[Index].Type) {\r
4663 case PcieExplainTypeLink:\r
4664 //\r
4665 // Link registers should not be used by\r
4666 // a) Root Complex Integrated Endpoint\r
4667 // b) Root Complex Event Collector\r
4668 //\r
4669 if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
4670 DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
4671 continue;\r
4672 }\r
4673 break;\r
4674 case PcieExplainTypeSlot:\r
4675 //\r
4676 // Slot registers are only valid for\r
4677 // a) Root Port of PCI Express Root Complex\r
4678 // b) Downstream Port of PCI Express Switch\r
4679 // and when SlotImplemented bit is set in PCIE cap register.\r
4680 //\r
4681 if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
4682 DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
4683 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
4684 continue;\r
4685 }\r
4686 break;\r
4687 case PcieExplainTypeRoot:\r
4688 //\r
4689 // Root registers are only valid for\r
4690 // Root Port of PCI Express Root Complex\r
4691 //\r
4692 if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
4693 continue;\r
4694 }\r
4695 break;\r
4696 default:\r
4697 break;\r
4698 }\r
4699 PcieExplainList[Index].Func (&PciExpressCap);\r
4700 }\r
4701\r
4702 Bus = (UINT8) (RShiftU64 (Address, 24));\r
4703 Dev = (UINT8) (RShiftU64 (Address, 16));\r
4704 Func = (UINT8) (RShiftU64 (Address, 8));\r
4705\r
4706 Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);\r
4707\r
4708 ExtendRegSize = 0x1000 - 0x100;\r
4709\r
4710 ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
4711\r
4712 //\r
4713 // PciRootBridgeIo protocol should support pci express extend space IO\r
4714 // (Begins at offset 0x100)\r
4715 //\r
4716 Status = IoDev->Pci.Read (\r
4717 IoDev,\r
4718 EfiPciWidthUint32,\r
4719 Pciex_Address,\r
4720 (ExtendRegSize) / sizeof (UINT32),\r
4721 (VOID *) (ExRegBuffer)\r
4722 );\r
4723 if (EFI_ERROR (Status)) {\r
4724 FreePool ((VOID *) ExRegBuffer);\r
4725 return EFI_UNSUPPORTED;\r
4726 }\r
4727 //\r
4728 // Start outputing PciEx extend space( 0xFF-0xFFF)\r
4729 //\r
4730 ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
4731\r
4732 if (ExRegBuffer != NULL) {\r
4733 DumpHex (\r
4734 2,\r
4735 0x100,\r
4736 ExtendRegSize,\r
4737 (VOID *) (ExRegBuffer)\r
4738 );\r
4739\r
4740 FreePool ((VOID *) ExRegBuffer);\r
4741 }\r
4742\r
4743Done:\r
4744 return EFI_SUCCESS;\r
4745}\r
EFI Development Kit II mirror for PVE