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1/** @file\r
2 Local APIC Library.\r
3\r
4 This local APIC library instance supports x2APIC capable processors\r
5 which have xAPIC and x2APIC modes.\r
6\r
7 Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r
8 Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>\r
9\r
10 SPDX-License-Identifier: BSD-2-Clause-Patent\r
11\r
12**/\r
13\r
14#include <Register/Intel/Cpuid.h>\r
15#include <Register/Amd/Cpuid.h>\r
16#include <Register/Intel/Msr.h>\r
17#include <Register/Intel/LocalApic.h>\r
18\r
19#include <Library/BaseLib.h>\r
20#include <Library/DebugLib.h>\r
21#include <Library/LocalApicLib.h>\r
22#include <Library/IoLib.h>\r
23#include <Library/TimerLib.h>\r
24#include <Library/PcdLib.h>\r
25#include <Library/UefiCpuLib.h>\r
26\r
27//\r
28// Library internal functions\r
29//\r
30\r
31/**\r
32 Determine if the CPU supports the Local APIC Base Address MSR.\r
33\r
34 @retval TRUE The CPU supports the Local APIC Base Address MSR.\r
35 @retval FALSE The CPU does not support the Local APIC Base Address MSR.\r
36\r
37**/\r
38BOOLEAN\r
39LocalApicBaseAddressMsrSupported (\r
40 VOID\r
41 )\r
42{\r
43 UINT32 RegEax;\r
44 UINTN FamilyId;\r
45\r
46 AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
47 FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
48 if (FamilyId == 0x04 || FamilyId == 0x05) {\r
49 //\r
50 // CPUs with a FamilyId of 0x04 or 0x05 do not support the\r
51 // Local APIC Base Address MSR\r
52 //\r
53 return FALSE;\r
54 }\r
55 return TRUE;\r
56}\r
57\r
58/**\r
59 Retrieve the base address of local APIC.\r
60\r
61 @return The base address of local APIC.\r
62\r
63**/\r
64UINTN\r
65EFIAPI\r
66GetLocalApicBaseAddress (\r
67 VOID\r
68 )\r
69{\r
70 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
71\r
72 if (!LocalApicBaseAddressMsrSupported ()) {\r
73 //\r
74 // If CPU does not support Local APIC Base Address MSR, then retrieve\r
75 // Local APIC Base Address from PCD\r
76 //\r
77 return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
78 }\r
79\r
80 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
81\r
82 return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
83 (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
84}\r
85\r
86/**\r
87 Set the base address of local APIC.\r
88\r
89 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
90\r
91 @param[in] BaseAddress Local APIC base address to be set.\r
92\r
93**/\r
94VOID\r
95EFIAPI\r
96SetLocalApicBaseAddress (\r
97 IN UINTN BaseAddress\r
98 )\r
99{\r
100 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
101\r
102 ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
103\r
104 if (!LocalApicBaseAddressMsrSupported ()) {\r
105 //\r
106 // Ignore set request of the CPU does not support APIC Base Address MSR\r
107 //\r
108 return;\r
109 }\r
110\r
111 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
112\r
113 ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);\r
114 ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
115\r
116 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
117}\r
118\r
119/**\r
120 Read from a local APIC register.\r
121\r
122 This function reads from a local APIC register either in xAPIC or x2APIC mode.\r
123 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r
124 accessed using multiple 32-bit loads or stores, so this function only performs\r
125 32-bit read.\r
126\r
127 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r
128 It must be 16-byte aligned.\r
129\r
130 @return 32-bit Value read from the register.\r
131**/\r
132UINT32\r
133EFIAPI\r
134ReadLocalApicReg (\r
135 IN UINTN MmioOffset\r
136 )\r
137{\r
138 UINT32 MsrIndex;\r
139\r
140 ASSERT ((MmioOffset & 0xf) == 0);\r
141\r
142 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
143 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r
144 } else {\r
145 //\r
146 // DFR is not supported in x2APIC mode.\r
147 //\r
148 ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);\r
149 //\r
150 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It\r
151 // is not supported in this function for simplicity.\r
152 //\r
153 ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);\r
154\r
155 MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;\r
156 return AsmReadMsr32 (MsrIndex);\r
157 }\r
158}\r
159\r
160/**\r
161 Write to a local APIC register.\r
162\r
163 This function writes to a local APIC register either in xAPIC or x2APIC mode.\r
164 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r
165 accessed using multiple 32-bit loads or stores, so this function only performs\r
166 32-bit write.\r
167\r
168 if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r
169\r
170 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r
171 It must be 16-byte aligned.\r
172 @param Value Value to be written to the register.\r
173**/\r
174VOID\r
175EFIAPI\r
176WriteLocalApicReg (\r
177 IN UINTN MmioOffset,\r
178 IN UINT32 Value\r
179 )\r
180{\r
181 UINT32 MsrIndex;\r
182\r
183 ASSERT ((MmioOffset & 0xf) == 0);\r
184\r
185 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
186 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r
187 } else {\r
188 //\r
189 // DFR is not supported in x2APIC mode.\r
190 //\r
191 ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);\r
192 //\r
193 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It\r
194 // is not supported in this function for simplicity.\r
195 //\r
196 ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);\r
197 ASSERT (MmioOffset != XAPIC_ICR_LOW_OFFSET);\r
198\r
199 MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;\r
200 //\r
201 // The serializing semantics of WRMSR are relaxed when writing to the APIC registers.\r
202 // Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.\r
203 //\r
204 MemoryFence ();\r
205 AsmWriteMsr32 (MsrIndex, Value);\r
206 }\r
207}\r
208\r
209/**\r
210 Send an IPI by writing to ICR.\r
211\r
212 This function returns after the IPI has been accepted by the target processor.\r
213\r
214 @param IcrLow 32-bit value to be written to the low half of ICR.\r
215 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r
216**/\r
217VOID\r
218SendIpi (\r
219 IN UINT32 IcrLow,\r
220 IN UINT32 ApicId\r
221 )\r
222{\r
223 UINT64 MsrValue;\r
224 LOCAL_APIC_ICR_LOW IcrLowReg;\r
225 UINTN LocalApciBaseAddress;\r
226 UINT32 IcrHigh;\r
227 BOOLEAN InterruptState;\r
228\r
229 //\r
230 // Legacy APIC or X2APIC?\r
231 //\r
232 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
233 ASSERT (ApicId <= 0xff);\r
234\r
235 InterruptState = SaveAndDisableInterrupts ();\r
236\r
237 //\r
238 // Get base address of this LAPIC\r
239 //\r
240 LocalApciBaseAddress = GetLocalApicBaseAddress();\r
241\r
242 //\r
243 // Save existing contents of ICR high 32 bits\r
244 //\r
245 IcrHigh = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET);\r
246\r
247 //\r
248 // Wait for DeliveryStatus clear in case a previous IPI\r
249 // is still being sent\r
250 //\r
251 do {\r
252 IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r
253 } while (IcrLowReg.Bits.DeliveryStatus != 0);\r
254\r
255 //\r
256 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r
257 //\r
258 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
259 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);\r
260\r
261 //\r
262 // Wait for DeliveryStatus clear again\r
263 //\r
264 do {\r
265 IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r
266 } while (IcrLowReg.Bits.DeliveryStatus != 0);\r
267\r
268 //\r
269 // And restore old contents of ICR high\r
270 //\r
271 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r
272\r
273 SetInterruptState (InterruptState);\r
274\r
275 } else {\r
276 //\r
277 // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an\r
278 // interrupt in x2APIC mode.\r
279 //\r
280 MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;\r
281 AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);\r
282 }\r
283}\r
284\r
285//\r
286// Library API implementation functions\r
287//\r
288\r
289/**\r
290 Get the current local APIC mode.\r
291\r
292 If local APIC is disabled, then ASSERT.\r
293\r
294 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r
295 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
296**/\r
297UINTN\r
298EFIAPI\r
299GetApicMode (\r
300 VOID\r
301 )\r
302{\r
303 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
304\r
305 if (!LocalApicBaseAddressMsrSupported ()) {\r
306 //\r
307 // If CPU does not support APIC Base Address MSR, then return XAPIC mode\r
308 //\r
309 return LOCAL_APIC_MODE_XAPIC;\r
310 }\r
311\r
312 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
313 //\r
314 // Local APIC should have been enabled\r
315 //\r
316 ASSERT (ApicBaseMsr.Bits.EN != 0);\r
317 if (ApicBaseMsr.Bits.EXTD != 0) {\r
318 return LOCAL_APIC_MODE_X2APIC;\r
319 } else {\r
320 return LOCAL_APIC_MODE_XAPIC;\r
321 }\r
322}\r
323\r
324/**\r
325 Set the current local APIC mode.\r
326\r
327 If the specified local APIC mode is not valid, then ASSERT.\r
328 If the specified local APIC mode can't be set as current, then ASSERT.\r
329\r
330 @param ApicMode APIC mode to be set.\r
331\r
332 @note This API must not be called from an interrupt handler or SMI handler.\r
333 It may result in unpredictable behavior.\r
334**/\r
335VOID\r
336EFIAPI\r
337SetApicMode (\r
338 IN UINTN ApicMode\r
339 )\r
340{\r
341 UINTN CurrentMode;\r
342 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
343\r
344 if (!LocalApicBaseAddressMsrSupported ()) {\r
345 //\r
346 // Ignore set request if the CPU does not support APIC Base Address MSR\r
347 //\r
348 return;\r
349 }\r
350\r
351 CurrentMode = GetApicMode ();\r
352 if (CurrentMode == LOCAL_APIC_MODE_XAPIC) {\r
353 switch (ApicMode) {\r
354 case LOCAL_APIC_MODE_XAPIC:\r
355 break;\r
356 case LOCAL_APIC_MODE_X2APIC:\r
357 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
358 ApicBaseMsr.Bits.EXTD = 1;\r
359 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
360 break;\r
361 default:\r
362 ASSERT (FALSE);\r
363 }\r
364 } else {\r
365 switch (ApicMode) {\r
366 case LOCAL_APIC_MODE_XAPIC:\r
367 //\r
368 // Transition from x2APIC mode to xAPIC mode is a two-step process:\r
369 // x2APIC -> Local APIC disabled -> xAPIC\r
370 //\r
371 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
372 ApicBaseMsr.Bits.EXTD = 0;\r
373 ApicBaseMsr.Bits.EN = 0;\r
374 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
375 ApicBaseMsr.Bits.EN = 1;\r
376 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
377 break;\r
378 case LOCAL_APIC_MODE_X2APIC:\r
379 break;\r
380 default:\r
381 ASSERT (FALSE);\r
382 }\r
383 }\r
384}\r
385\r
386/**\r
387 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
388\r
389 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
390 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r
391 the 32-bit local APIC ID is returned as initial APIC ID.\r
392\r
393 @return 32-bit initial local APIC ID of the executing processor.\r
394**/\r
395UINT32\r
396EFIAPI\r
397GetInitialApicId (\r
398 VOID\r
399 )\r
400{\r
401 UINT32 ApicId;\r
402 UINT32 MaxCpuIdIndex;\r
403 UINT32 RegEbx;\r
404\r
405 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
406 //\r
407 // Get the max index of basic CPUID\r
408 //\r
409 AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
410 //\r
411 // If CPUID Leaf B is supported,\r
412 // And CPUID.0BH:EBX[15:0] reports a non-zero value,\r
413 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r
414 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r
415 //\r
416 if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
417 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &RegEbx, NULL, &ApicId);\r
418 if ((RegEbx & (BIT16 - 1)) != 0) {\r
419 return ApicId;\r
420 }\r
421 }\r
422 AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
423 return RegEbx >> 24;\r
424 } else {\r
425 return GetApicId ();\r
426 }\r
427}\r
428\r
429/**\r
430 Get the local APIC ID of the executing processor.\r
431\r
432 @return 32-bit local APIC ID of the executing processor.\r
433**/\r
434UINT32\r
435EFIAPI\r
436GetApicId (\r
437 VOID\r
438 )\r
439{\r
440 UINT32 ApicId;\r
441 UINT32 InitApicId;\r
442\r
443 ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r
444 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
445 ApicId = ((InitApicId = GetInitialApicId ()) < 0x100) ? (ApicId >> 24) : InitApicId;\r
446 }\r
447\r
448 return ApicId;\r
449}\r
450\r
451/**\r
452 Get the value of the local APIC version register.\r
453\r
454 @return the value of the local APIC version register.\r
455**/\r
456UINT32\r
457EFIAPI\r
458GetApicVersion (\r
459 VOID\r
460 )\r
461{\r
462 return ReadLocalApicReg (XAPIC_VERSION_OFFSET);\r
463}\r
464\r
465/**\r
466 Send a Fixed IPI to a specified target processor.\r
467\r
468 This function returns after the IPI has been accepted by the target processor.\r
469\r
470 @param ApicId The local APIC ID of the target processor.\r
471 @param Vector The vector number of the interrupt being sent.\r
472**/\r
473VOID\r
474EFIAPI\r
475SendFixedIpi (\r
476 IN UINT32 ApicId,\r
477 IN UINT8 Vector\r
478 )\r
479{\r
480 LOCAL_APIC_ICR_LOW IcrLow;\r
481\r
482 IcrLow.Uint32 = 0;\r
483 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
484 IcrLow.Bits.Level = 1;\r
485 IcrLow.Bits.Vector = Vector;\r
486 SendIpi (IcrLow.Uint32, ApicId);\r
487}\r
488\r
489/**\r
490 Send a Fixed IPI to all processors excluding self.\r
491\r
492 This function returns after the IPI has been accepted by the target processors.\r
493\r
494 @param Vector The vector number of the interrupt being sent.\r
495**/\r
496VOID\r
497EFIAPI\r
498SendFixedIpiAllExcludingSelf (\r
499 IN UINT8 Vector\r
500 )\r
501{\r
502 LOCAL_APIC_ICR_LOW IcrLow;\r
503\r
504 IcrLow.Uint32 = 0;\r
505 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
506 IcrLow.Bits.Level = 1;\r
507 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
508 IcrLow.Bits.Vector = Vector;\r
509 SendIpi (IcrLow.Uint32, 0);\r
510}\r
511\r
512/**\r
513 Send a SMI IPI to a specified target processor.\r
514\r
515 This function returns after the IPI has been accepted by the target processor.\r
516\r
517 @param ApicId Specify the local APIC ID of the target processor.\r
518**/\r
519VOID\r
520EFIAPI\r
521SendSmiIpi (\r
522 IN UINT32 ApicId\r
523 )\r
524{\r
525 LOCAL_APIC_ICR_LOW IcrLow;\r
526\r
527 IcrLow.Uint32 = 0;\r
528 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
529 IcrLow.Bits.Level = 1;\r
530 SendIpi (IcrLow.Uint32, ApicId);\r
531}\r
532\r
533/**\r
534 Send a SMI IPI to all processors excluding self.\r
535\r
536 This function returns after the IPI has been accepted by the target processors.\r
537**/\r
538VOID\r
539EFIAPI\r
540SendSmiIpiAllExcludingSelf (\r
541 VOID\r
542 )\r
543{\r
544 LOCAL_APIC_ICR_LOW IcrLow;\r
545\r
546 IcrLow.Uint32 = 0;\r
547 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
548 IcrLow.Bits.Level = 1;\r
549 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
550 SendIpi (IcrLow.Uint32, 0);\r
551}\r
552\r
553/**\r
554 Send an INIT IPI to a specified target processor.\r
555\r
556 This function returns after the IPI has been accepted by the target processor.\r
557\r
558 @param ApicId Specify the local APIC ID of the target processor.\r
559**/\r
560VOID\r
561EFIAPI\r
562SendInitIpi (\r
563 IN UINT32 ApicId\r
564 )\r
565{\r
566 LOCAL_APIC_ICR_LOW IcrLow;\r
567\r
568 IcrLow.Uint32 = 0;\r
569 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
570 IcrLow.Bits.Level = 1;\r
571 SendIpi (IcrLow.Uint32, ApicId);\r
572}\r
573\r
574/**\r
575 Send an INIT IPI to all processors excluding self.\r
576\r
577 This function returns after the IPI has been accepted by the target processors.\r
578**/\r
579VOID\r
580EFIAPI\r
581SendInitIpiAllExcludingSelf (\r
582 VOID\r
583 )\r
584{\r
585 LOCAL_APIC_ICR_LOW IcrLow;\r
586\r
587 IcrLow.Uint32 = 0;\r
588 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
589 IcrLow.Bits.Level = 1;\r
590 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
591 SendIpi (IcrLow.Uint32, 0);\r
592}\r
593\r
594/**\r
595 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
596\r
597 This function returns after the IPI has been accepted by the target processor.\r
598\r
599 if StartupRoutine >= 1M, then ASSERT.\r
600 if StartupRoutine is not multiple of 4K, then ASSERT.\r
601\r
602 @param ApicId Specify the local APIC ID of the target processor.\r
603 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
604 address and 4K aligned.\r
605**/\r
606VOID\r
607EFIAPI\r
608SendInitSipiSipi (\r
609 IN UINT32 ApicId,\r
610 IN UINT32 StartupRoutine\r
611 )\r
612{\r
613 LOCAL_APIC_ICR_LOW IcrLow;\r
614\r
615 ASSERT (StartupRoutine < 0x100000);\r
616 ASSERT ((StartupRoutine & 0xfff) == 0);\r
617\r
618 SendInitIpi (ApicId);\r
619 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
620 IcrLow.Uint32 = 0;\r
621 IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
622 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
623 IcrLow.Bits.Level = 1;\r
624 SendIpi (IcrLow.Uint32, ApicId);\r
625 if (!StandardSignatureIsAuthenticAMD ()) {\r
626 MicroSecondDelay (200);\r
627 SendIpi (IcrLow.Uint32, ApicId);\r
628 }\r
629}\r
630\r
631/**\r
632 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
633\r
634 This function returns after the IPI has been accepted by the target processors.\r
635\r
636 if StartupRoutine >= 1M, then ASSERT.\r
637 if StartupRoutine is not multiple of 4K, then ASSERT.\r
638\r
639 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
640 address and 4K aligned.\r
641**/\r
642VOID\r
643EFIAPI\r
644SendInitSipiSipiAllExcludingSelf (\r
645 IN UINT32 StartupRoutine\r
646 )\r
647{\r
648 LOCAL_APIC_ICR_LOW IcrLow;\r
649\r
650 ASSERT (StartupRoutine < 0x100000);\r
651 ASSERT ((StartupRoutine & 0xfff) == 0);\r
652\r
653 SendInitIpiAllExcludingSelf ();\r
654 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
655 IcrLow.Uint32 = 0;\r
656 IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
657 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
658 IcrLow.Bits.Level = 1;\r
659 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
660 SendIpi (IcrLow.Uint32, 0);\r
661 if (!StandardSignatureIsAuthenticAMD ()) {\r
662 MicroSecondDelay (200);\r
663 SendIpi (IcrLow.Uint32, 0);\r
664 }\r
665}\r
666\r
667/**\r
668 Initialize the state of the SoftwareEnable bit in the Local APIC\r
669 Spurious Interrupt Vector register.\r
670\r
671 @param Enable If TRUE, then set SoftwareEnable to 1\r
672 If FALSE, then set SoftwareEnable to 0.\r
673\r
674**/\r
675VOID\r
676EFIAPI\r
677InitializeLocalApicSoftwareEnable (\r
678 IN BOOLEAN Enable\r
679 )\r
680{\r
681 LOCAL_APIC_SVR Svr;\r
682\r
683 //\r
684 // Set local APIC software-enabled bit.\r
685 //\r
686 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
687 if (Enable) {\r
688 if (Svr.Bits.SoftwareEnable == 0) {\r
689 Svr.Bits.SoftwareEnable = 1;\r
690 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
691 }\r
692 } else {\r
693 if (Svr.Bits.SoftwareEnable == 1) {\r
694 Svr.Bits.SoftwareEnable = 0;\r
695 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
696 }\r
697 }\r
698}\r
699\r
700/**\r
701 Programming Virtual Wire Mode.\r
702\r
703 This function programs the local APIC for virtual wire mode following\r
704 the example described in chapter A.3 of the MP 1.4 spec.\r
705\r
706 IOxAPIC is not involved in this type of virtual wire mode.\r
707**/\r
708VOID\r
709EFIAPI\r
710ProgramVirtualWireMode (\r
711 VOID\r
712 )\r
713{\r
714 LOCAL_APIC_SVR Svr;\r
715 LOCAL_APIC_LVT_LINT Lint;\r
716\r
717 //\r
718 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r
719 //\r
720 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
721 Svr.Bits.SpuriousVector = 0xf;\r
722 Svr.Bits.SoftwareEnable = 1;\r
723 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
724\r
725 //\r
726 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r
727 //\r
728 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
729 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r
730 Lint.Bits.InputPinPolarity = 0;\r
731 Lint.Bits.TriggerMode = 0;\r
732 Lint.Bits.Mask = 0;\r
733 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r
734\r
735 //\r
736 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r
737 //\r
738 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
739 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r
740 Lint.Bits.InputPinPolarity = 0;\r
741 Lint.Bits.TriggerMode = 0;\r
742 Lint.Bits.Mask = 0;\r
743 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r
744}\r
745\r
746/**\r
747 Disable LINT0 & LINT1 interrupts.\r
748\r
749 This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
750**/\r
751VOID\r
752EFIAPI\r
753DisableLvtInterrupts (\r
754 VOID\r
755 )\r
756{\r
757 LOCAL_APIC_LVT_LINT LvtLint;\r
758\r
759 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
760 LvtLint.Bits.Mask = 1;\r
761 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r
762\r
763 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
764 LvtLint.Bits.Mask = 1;\r
765 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r
766}\r
767\r
768/**\r
769 Read the initial count value from the init-count register.\r
770\r
771 @return The initial count value read from the init-count register.\r
772**/\r
773UINT32\r
774EFIAPI\r
775GetApicTimerInitCount (\r
776 VOID\r
777 )\r
778{\r
779 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r
780}\r
781\r
782/**\r
783 Read the current count value from the current-count register.\r
784\r
785 @return The current count value read from the current-count register.\r
786**/\r
787UINT32\r
788EFIAPI\r
789GetApicTimerCurrentCount (\r
790 VOID\r
791 )\r
792{\r
793 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r
794}\r
795\r
796/**\r
797 Initialize the local APIC timer.\r
798\r
799 The local APIC timer is initialized and enabled.\r
800\r
801 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
802 If it is 0, then use the current divide value in the DCR.\r
803 @param InitCount The initial count value.\r
804 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
805 @param Vector The timer interrupt vector number.\r
806**/\r
807VOID\r
808EFIAPI\r
809InitializeApicTimer (\r
810 IN UINTN DivideValue,\r
811 IN UINT32 InitCount,\r
812 IN BOOLEAN PeriodicMode,\r
813 IN UINT8 Vector\r
814 )\r
815{\r
816 LOCAL_APIC_DCR Dcr;\r
817 LOCAL_APIC_LVT_TIMER LvtTimer;\r
818 UINT32 Divisor;\r
819\r
820 //\r
821 // Ensure local APIC is in software-enabled state.\r
822 //\r
823 InitializeLocalApicSoftwareEnable (TRUE);\r
824\r
825 //\r
826 // Program init-count register.\r
827 //\r
828 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r
829\r
830 if (DivideValue != 0) {\r
831 ASSERT (DivideValue <= 128);\r
832 ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r
833 Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r
834\r
835 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
836 Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
837 Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
838 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);\r
839 }\r
840\r
841 //\r
842 // Enable APIC timer interrupt with specified timer mode.\r
843 //\r
844 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
845 if (PeriodicMode) {\r
846 LvtTimer.Bits.TimerMode = 1;\r
847 } else {\r
848 LvtTimer.Bits.TimerMode = 0;\r
849 }\r
850 LvtTimer.Bits.Mask = 0;\r
851 LvtTimer.Bits.Vector = Vector;\r
852 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
853}\r
854\r
855/**\r
856 Get the state of the local APIC timer.\r
857\r
858 This function will ASSERT if the local APIC is not software enabled.\r
859\r
860 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
861 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
862 @param Vector Return the timer interrupt vector number.\r
863**/\r
864VOID\r
865EFIAPI\r
866GetApicTimerState (\r
867 OUT UINTN *DivideValue OPTIONAL,\r
868 OUT BOOLEAN *PeriodicMode OPTIONAL,\r
869 OUT UINT8 *Vector OPTIONAL\r
870 )\r
871{\r
872 UINT32 Divisor;\r
873 LOCAL_APIC_DCR Dcr;\r
874 LOCAL_APIC_LVT_TIMER LvtTimer;\r
875\r
876 //\r
877 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r
878 // Vector Register.\r
879 // This bit will be 1, if local APIC is software enabled.\r
880 //\r
881 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r
882\r
883 if (DivideValue != NULL) {\r
884 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
885 Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
886 Divisor = (Divisor + 1) & 0x7;\r
887 *DivideValue = ((UINTN)1) << Divisor;\r
888 }\r
889\r
890 if (PeriodicMode != NULL || Vector != NULL) {\r
891 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
892 if (PeriodicMode != NULL) {\r
893 if (LvtTimer.Bits.TimerMode == 1) {\r
894 *PeriodicMode = TRUE;\r
895 } else {\r
896 *PeriodicMode = FALSE;\r
897 }\r
898 }\r
899 if (Vector != NULL) {\r
900 *Vector = (UINT8) LvtTimer.Bits.Vector;\r
901 }\r
902 }\r
903}\r
904\r
905/**\r
906 Enable the local APIC timer interrupt.\r
907**/\r
908VOID\r
909EFIAPI\r
910EnableApicTimerInterrupt (\r
911 VOID\r
912 )\r
913{\r
914 LOCAL_APIC_LVT_TIMER LvtTimer;\r
915\r
916 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
917 LvtTimer.Bits.Mask = 0;\r
918 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
919}\r
920\r
921/**\r
922 Disable the local APIC timer interrupt.\r
923**/\r
924VOID\r
925EFIAPI\r
926DisableApicTimerInterrupt (\r
927 VOID\r
928 )\r
929{\r
930 LOCAL_APIC_LVT_TIMER LvtTimer;\r
931\r
932 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
933 LvtTimer.Bits.Mask = 1;\r
934 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
935}\r
936\r
937/**\r
938 Get the local APIC timer interrupt state.\r
939\r
940 @retval TRUE The local APIC timer interrupt is enabled.\r
941 @retval FALSE The local APIC timer interrupt is disabled.\r
942**/\r
943BOOLEAN\r
944EFIAPI\r
945GetApicTimerInterruptState (\r
946 VOID\r
947 )\r
948{\r
949 LOCAL_APIC_LVT_TIMER LvtTimer;\r
950\r
951 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
952 return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r
953}\r
954\r
955/**\r
956 Send EOI to the local APIC.\r
957**/\r
958VOID\r
959EFIAPI\r
960SendApicEoi (\r
961 VOID\r
962 )\r
963{\r
964 WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r
965}\r
966\r
967/**\r
968 Get the 32-bit address that a device should use to send a Message Signaled\r
969 Interrupt (MSI) to the Local APIC of the currently executing processor.\r
970\r
971 @return 32-bit address used to send an MSI to the Local APIC.\r
972**/\r
973UINT32\r
974EFIAPI\r
975GetApicMsiAddress (\r
976 VOID\r
977 )\r
978{\r
979 LOCAL_APIC_MSI_ADDRESS MsiAddress;\r
980\r
981 //\r
982 // Return address for an MSI interrupt to be delivered only to the APIC ID\r
983 // of the currently executing processor.\r
984 //\r
985 MsiAddress.Uint32 = 0;\r
986 MsiAddress.Bits.BaseAddress = 0xFEE;\r
987 MsiAddress.Bits.DestinationId = GetApicId ();\r
988 return MsiAddress.Uint32;\r
989}\r
990\r
991/**\r
992 Get the 64-bit data value that a device should use to send a Message Signaled\r
993 Interrupt (MSI) to the Local APIC of the currently executing processor.\r
994\r
995 If Vector is not in range 0x10..0xFE, then ASSERT().\r
996 If DeliveryMode is not supported, then ASSERT().\r
997\r
998 @param Vector The 8-bit interrupt vector associated with the MSI.\r
999 Must be in the range 0x10..0xFE\r
1000 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI\r
1001 is handled. The only supported values are:\r
1002 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
1003 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
1004 2: LOCAL_APIC_DELIVERY_MODE_SMI\r
1005 4: LOCAL_APIC_DELIVERY_MODE_NMI\r
1006 5: LOCAL_APIC_DELIVERY_MODE_INIT\r
1007 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
1008\r
1009 @param LevelTriggered TRUE specifies a level triggered interrupt.\r
1010 FALSE specifies an edge triggered interrupt.\r
1011 @param AssertionLevel Ignored if LevelTriggered is FALSE.\r
1012 TRUE specifies a level triggered interrupt that active\r
1013 when the interrupt line is asserted.\r
1014 FALSE specifies a level triggered interrupt that active\r
1015 when the interrupt line is deasserted.\r
1016\r
1017 @return 64-bit data value used to send an MSI to the Local APIC.\r
1018**/\r
1019UINT64\r
1020EFIAPI\r
1021GetApicMsiValue (\r
1022 IN UINT8 Vector,\r
1023 IN UINTN DeliveryMode,\r
1024 IN BOOLEAN LevelTriggered,\r
1025 IN BOOLEAN AssertionLevel\r
1026 )\r
1027{\r
1028 LOCAL_APIC_MSI_DATA MsiData;\r
1029\r
1030 ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
1031 ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
1032\r
1033 MsiData.Uint64 = 0;\r
1034 MsiData.Bits.Vector = Vector;\r
1035 MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r
1036 if (LevelTriggered) {\r
1037 MsiData.Bits.TriggerMode = 1;\r
1038 if (AssertionLevel) {\r
1039 MsiData.Bits.Level = 1;\r
1040 }\r
1041 }\r
1042 return MsiData.Uint64;\r
1043}\r
1044\r
1045/**\r
1046 Get Package ID/Core ID/Thread ID of a processor.\r
1047\r
1048 The algorithm assumes the target system has symmetry across physical\r
1049 package boundaries with respect to the number of logical processors\r
1050 per package, number of cores per package.\r
1051\r
1052 @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
1053 @param[out] Package Returns the processor package ID.\r
1054 @param[out] Core Returns the processor core ID.\r
1055 @param[out] Thread Returns the processor thread ID.\r
1056**/\r
1057VOID\r
1058EFIAPI\r
1059GetProcessorLocationByApicId (\r
1060 IN UINT32 InitialApicId,\r
1061 OUT UINT32 *Package OPTIONAL,\r
1062 OUT UINT32 *Core OPTIONAL,\r
1063 OUT UINT32 *Thread OPTIONAL\r
1064 )\r
1065{\r
1066 BOOLEAN TopologyLeafSupported;\r
1067 CPUID_VERSION_INFO_EBX VersionInfoEbx;\r
1068 CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
1069 CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r
1070 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
1071 CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r
1072 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
1073 CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;\r
1074 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;\r
1075 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;\r
1076 UINT32 MaxStandardCpuIdIndex;\r
1077 UINT32 MaxExtendedCpuIdIndex;\r
1078 UINT32 SubIndex;\r
1079 UINTN LevelType;\r
1080 UINT32 MaxLogicProcessorsPerPackage;\r
1081 UINT32 MaxCoresPerPackage;\r
1082 UINTN ThreadBits;\r
1083 UINTN CoreBits;\r
1084\r
1085 //\r
1086 // Check if the processor is capable of supporting more than one logical processor.\r
1087 //\r
1088 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
1089 if (VersionInfoEdx.Bits.HTT == 0) {\r
1090 if (Thread != NULL) {\r
1091 *Thread = 0;\r
1092 }\r
1093 if (Core != NULL) {\r
1094 *Core = 0;\r
1095 }\r
1096 if (Package != NULL) {\r
1097 *Package = 0;\r
1098 }\r
1099 return;\r
1100 }\r
1101\r
1102 //\r
1103 // Assume three-level mapping of APIC ID: Package|Core|Thread.\r
1104 //\r
1105 ThreadBits = 0;\r
1106 CoreBits = 0;\r
1107\r
1108 //\r
1109 // Get max index of CPUID\r
1110 //\r
1111 AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
1112 AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r
1113\r
1114 //\r
1115 // If the extended topology enumeration leaf is available, it\r
1116 // is the preferred mechanism for enumerating topology.\r
1117 //\r
1118 TopologyLeafSupported = FALSE;\r
1119 if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
1120 AsmCpuidEx(\r
1121 CPUID_EXTENDED_TOPOLOGY,\r
1122 0,\r
1123 &ExtendedTopologyEax.Uint32,\r
1124 &ExtendedTopologyEbx.Uint32,\r
1125 &ExtendedTopologyEcx.Uint32,\r
1126 NULL\r
1127 );\r
1128 //\r
1129 // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
1130 // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
1131 // supported on that processor.\r
1132 //\r
1133 if (ExtendedTopologyEbx.Uint32 != 0) {\r
1134 TopologyLeafSupported = TRUE;\r
1135\r
1136 //\r
1137 // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
1138 // the SMT sub-field of x2APIC ID.\r
1139 //\r
1140 LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
1141 ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
1142 ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
1143\r
1144 //\r
1145 // Software must not assume any "level type" encoding\r
1146 // value to be related to any sub-leaf index, except sub-leaf 0.\r
1147 //\r
1148 SubIndex = 1;\r
1149 do {\r
1150 AsmCpuidEx (\r
1151 CPUID_EXTENDED_TOPOLOGY,\r
1152 SubIndex,\r
1153 &ExtendedTopologyEax.Uint32,\r
1154 NULL,\r
1155 &ExtendedTopologyEcx.Uint32,\r
1156 NULL\r
1157 );\r
1158 LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
1159 if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
1160 CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
1161 break;\r
1162 }\r
1163 SubIndex++;\r
1164 } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
1165 }\r
1166 }\r
1167\r
1168 if (!TopologyLeafSupported) {\r
1169 //\r
1170 // Get logical processor count\r
1171 //\r
1172 AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
1173 MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
1174\r
1175 //\r
1176 // Assume single-core processor\r
1177 //\r
1178 MaxCoresPerPackage = 1;\r
1179\r
1180 //\r
1181 // Check for topology extensions on AMD processor\r
1182 //\r
1183 if (StandardSignatureIsAuthenticAMD()) {\r
1184 if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r
1185 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
1186 if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r
1187 //\r
1188 // Account for max possible thread count to decode ApicId\r
1189 //\r
1190 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r
1191 MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r
1192\r
1193 //\r
1194 // Get cores per processor package\r
1195 //\r
1196 AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);\r
1197 MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
1198 }\r
1199 }\r
1200 }\r
1201 else {\r
1202 //\r
1203 // Extract core count based on CACHE information\r
1204 //\r
1205 if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
1206 AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
1207 if (CacheParamsEax.Uint32 != 0) {\r
1208 MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
1209 }\r
1210 }\r
1211 }\r
1212\r
1213 ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
1214 CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);\r
1215 }\r
1216\r
1217 if (Thread != NULL) {\r
1218 *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
1219 }\r
1220 if (Core != NULL) {\r
1221 *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
1222 }\r
1223 if (Package != NULL) {\r
1224 *Package = (InitialApicId >> (ThreadBits + CoreBits));\r
1225 }\r
1226}\r
1227\r
1228/**\r
1229 Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.\r
1230\r
1231 The algorithm assumes the target system has symmetry across physical\r
1232 package boundaries with respect to the number of threads per core, number of\r
1233 cores per module, number of modules per tile, number of tiles per die, number\r
1234 of dies per package.\r
1235\r
1236 @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
1237 @param[out] Package Returns the processor package ID.\r
1238 @param[out] Die Returns the processor die ID.\r
1239 @param[out] Tile Returns the processor tile ID.\r
1240 @param[out] Module Returns the processor module ID.\r
1241 @param[out] Core Returns the processor core ID.\r
1242 @param[out] Thread Returns the processor thread ID.\r
1243**/\r
1244VOID\r
1245EFIAPI\r
1246GetProcessorLocation2ByApicId (\r
1247 IN UINT32 InitialApicId,\r
1248 OUT UINT32 *Package OPTIONAL,\r
1249 OUT UINT32 *Die OPTIONAL,\r
1250 OUT UINT32 *Tile OPTIONAL,\r
1251 OUT UINT32 *Module OPTIONAL,\r
1252 OUT UINT32 *Core OPTIONAL,\r
1253 OUT UINT32 *Thread OPTIONAL\r
1254 )\r
1255{\r
1256 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
1257 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
1258 UINT32 MaxStandardCpuIdIndex;\r
1259 UINT32 Index;\r
1260 UINTN LevelType;\r
1261 UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
1262 UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
1263\r
1264 for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r
1265 Bits[LevelType] = 0;\r
1266 }\r
1267\r
1268 //\r
1269 // Get max index of CPUID\r
1270 //\r
1271 AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
1272 if (MaxStandardCpuIdIndex < CPUID_V2_EXTENDED_TOPOLOGY) {\r
1273 if (Die != NULL) {\r
1274 *Die = 0;\r
1275 }\r
1276 if (Tile != NULL) {\r
1277 *Tile = 0;\r
1278 }\r
1279 if (Module != NULL) {\r
1280 *Module = 0;\r
1281 }\r
1282 GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);\r
1283 return;\r
1284 }\r
1285\r
1286 //\r
1287 // If the V2 extended topology enumeration leaf is available, it\r
1288 // is the preferred mechanism for enumerating topology.\r
1289 //\r
1290 for (Index = 0; ; Index++) {\r
1291 AsmCpuidEx(\r
1292 CPUID_V2_EXTENDED_TOPOLOGY,\r
1293 Index,\r
1294 &ExtendedTopologyEax.Uint32,\r
1295 NULL,\r
1296 &ExtendedTopologyEcx.Uint32,\r
1297 NULL\r
1298 );\r
1299\r
1300 LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
1301\r
1302 //\r
1303 // first level reported should be SMT.\r
1304 //\r
1305 ASSERT ((Index != 0) || (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT));\r
1306 if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r
1307 break;\r
1308 }\r
1309 ASSERT (LevelType < ARRAY_SIZE (Bits));\r
1310 Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;\r
1311 }\r
1312\r
1313 for (LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r
1314 //\r
1315 // If there are more levels between level-1 (low-level) and level-2 (high-level), the unknown levels will be ignored\r
1316 // and treated as an extension of the last known level (i.e., level-1 in this case).\r
1317 //\r
1318 if (Bits[LevelType] == 0) {\r
1319 Bits[LevelType] = Bits[LevelType - 1];\r
1320 }\r
1321 }\r
1322\r
1323 Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;\r
1324 Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die;\r
1325 Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile;\r
1326 Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module;\r
1327 Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core;\r
1328 Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread;\r
1329\r
1330 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;\r
1331\r
1332 for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT\r
1333 ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1\r
1334 ; LevelType ++\r
1335 ) {\r
1336 if (Location[LevelType] != NULL) {\r
1337 //\r
1338 // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique\r
1339 // topology ID of the next level type.\r
1340 //\r
1341 *Location[LevelType] = InitialApicId >> Bits[LevelType - 1];\r
1342\r
1343 //\r
1344 // Bits[i] - Bits[i-1] holds the number of bits for the next ONE level type.\r
1345 //\r
1346 *Location[LevelType] &= (1 << (Bits[LevelType] - Bits[LevelType - 1])) - 1;\r
1347 }\r
1348 }\r
1349}\r