[mirror_edk2.git] / UefiCpuPkg / Library / MpInitLib / X64 / MpFuncs.nasm

;------------------------------------------------------------------------------ ;\r
; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;\r
;   MpFuncs.nasm\r
;\r
; Abstract:\r
;\r
;   This is the assembly code for MP support\r
;\r
;-------------------------------------------------------------------------------\r
\r
%include "MpEqu.inc"\r
extern ASM_PFX(InitializeFloatingPointUnits)\r
\r
DEFAULT REL\r
\r
SECTION .text\r
\r
;-------------------------------------------------------------------------------------\r
;RendezvousFunnelProc  procedure follows. All APs execute their procedure. This\r
;procedure serializes all the AP processors through an Init sequence. It must be\r
;noted that APs arrive here very raw...ie: real mode, no stack.\r
;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
;IS IN MACHINE CODE.\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(RendezvousFunnelProc)\r
ASM_PFX(RendezvousFunnelProc):\r
RendezvousFunnelProcStart:\r
; At this point CS = 0x(vv00) and ip= 0x0.\r
; Save BIST information to ebp firstly\r
\r
BITS 16\r
    mov        ebp, eax                        ; Save BIST information\r
\r
    mov        ax, cs\r
    mov        ds, ax\r
    mov        es, ax\r
    mov        ss, ax\r
    xor        ax, ax\r
    mov        fs, ax\r
    mov        gs, ax\r
\r
    mov        si,  BufferStartLocation\r
    mov        ebx, [si]\r
\r
    mov        si,  DataSegmentLocation\r
    mov        edx, [si]\r
\r
    ;\r
    ; Get start address of 32-bit code in low memory (<1MB)\r
    ;\r
    mov        edi, ModeTransitionMemoryLocation\r
\r
    mov        si, GdtrLocation\r
o32 lgdt       [cs:si]\r
\r
    mov        si, IdtrLocation\r
o32 lidt       [cs:si]\r
\r
    ;\r
    ; Switch to protected mode\r
    ;\r
    mov        eax, cr0                    ; Get control register 0\r
    or         eax, 000000003h             ; Set PE bit (bit #0) & MP\r
    mov        cr0, eax\r
\r
    ; Switch to 32-bit code (>1MB)\r
o32 jmp far    [cs:di]\r
\r
;\r
; Following code must be copied to memory with type of EfiBootServicesCode.\r
; This is required if NX is enabled for EfiBootServicesCode of memory.\r
;\r
BITS 32\r
Flat32Start:                                   ; protected mode entry point\r
    mov        ds, dx\r
    mov        es, dx\r
    mov        fs, dx\r
    mov        gs, dx\r
    mov        ss, dx\r
\r
    ;\r
    ; Enable execute disable bit\r
    ;\r
    mov        esi, EnableExecuteDisableLocation\r
    cmp        byte [ebx + esi], 0\r
    jz         SkipEnableExecuteDisableBit\r
\r
    mov        ecx, 0c0000080h             ; EFER MSR number\r
    rdmsr                                  ; Read EFER\r
    bts        eax, 11                     ; Enable Execute Disable Bit\r
    wrmsr                                  ; Write EFER\r
\r
SkipEnableExecuteDisableBit:\r
    ;\r
    ; Enable PAE\r
    ;\r
    mov        eax, cr4\r
    bts        eax, 5\r
    mov        cr4, eax\r
\r
    ;\r
    ; Load page table\r
    ;\r
    mov        esi, Cr3Location             ; Save CR3 in ecx\r
    mov        ecx, [ebx + esi]\r
    mov        cr3, ecx                    ; Load CR3\r
\r
    ;\r
    ; Enable long mode\r
    ;\r
    mov        ecx, 0c0000080h             ; EFER MSR number\r
    rdmsr                                  ; Read EFER\r
    bts        eax, 8                      ; Set LME=1\r
    wrmsr                                  ; Write EFER\r
\r
    ;\r
    ; Enable paging\r
    ;\r
    mov        eax, cr0                    ; Read CR0\r
    bts        eax, 31                     ; Set PG=1\r
    mov        cr0, eax                    ; Write CR0\r
\r
    ;\r
    ; Far jump to 64-bit code\r
    ;\r
    mov        edi, ModeHighMemoryLocation\r
    add        edi, ebx\r
    jmp far    [edi]\r
\r
BITS 64\r
LongModeStart:\r
    mov        esi, ebx\r
    lea        edi, [esi + InitFlagLocation]\r
    cmp        qword [edi], 1       ; ApInitConfig\r
    jnz        GetApicId\r
\r
    ; Increment the number of APs executing here as early as possible\r
    ; This is decremented in C code when AP is finished executing\r
    mov        edi, esi\r
    add        edi, NumApsExecutingLocation\r
    lock inc   dword [edi]\r
\r
    ; AP init\r
    mov        edi, esi\r
    add        edi, LockLocation\r
    mov        rax, NotVacantFlag\r
\r
TestLock:\r
    xchg       qword [edi], rax\r
    cmp        rax, NotVacantFlag\r
    jz         TestLock\r
\r
    lea        ecx, [esi + ApIndexLocation]\r
    inc        dword [ecx]\r
    mov        ebx, [ecx]\r
\r
Releaselock:\r
    mov        rax, VacantFlag\r
    xchg       qword [edi], rax\r
    ; program stack\r
    mov        edi, esi\r
    add        edi, StackSizeLocation\r
    mov        eax, dword [edi]\r
    mov        ecx, ebx\r
    inc        ecx\r
    mul        ecx                               ; EAX = StackSize * (CpuNumber + 1)\r
    mov        edi, esi\r
    add        edi, StackStartAddressLocation\r
    add        rax, qword [edi]\r
    mov        rsp, rax\r
    jmp        CProcedureInvoke\r
\r
GetApicId:\r
    mov        eax, 0\r
    cpuid\r
    cmp        eax, 0bh\r
    jb         NoX2Apic             ; CPUID level below CPUID_EXTENDED_TOPOLOGY\r
\r
    mov        eax, 0bh\r
    xor        ecx, ecx\r
    cpuid\r
    test       ebx, 0ffffh\r
    jz         NoX2Apic             ; CPUID.0BH:EBX[15:0] is zero\r
\r
    ; Processor is x2APIC capable; 32-bit x2APIC ID is already in EDX\r
    jmp        GetProcessorNumber\r
\r
NoX2Apic:\r
    ; Processor is not x2APIC capable, so get 8-bit APIC ID\r
    mov        eax, 1\r
    cpuid\r
    shr        ebx, 24\r
    mov        edx, ebx\r
\r
GetProcessorNumber:\r
    ;\r
    ; Get processor number for this AP\r
    ; Note that BSP may become an AP due to SwitchBsp()\r
    ;\r
    xor         ebx, ebx\r
    lea         eax, [esi + CpuInfoLocation]\r
    mov         edi, [eax]\r
\r
GetNextProcNumber:\r
    cmp         dword [edi], edx                      ; APIC ID match?\r
    jz          ProgramStack\r
    add         edi, 20\r
    inc         ebx\r
    jmp         GetNextProcNumber\r
\r
ProgramStack:\r
    mov         rsp, qword [edi + 12]\r
\r
CProcedureInvoke:\r
    push       rbp               ; Push BIST data at top of AP stack\r
    xor        rbp, rbp          ; Clear ebp for call stack trace\r
    push       rbp\r
    mov        rbp, rsp\r
\r
    mov        rax, qword [esi + InitializeFloatingPointUnitsAddress]\r
    sub        rsp, 20h\r
    call       rax               ; Call assembly function to initialize FPU per UEFI spec\r
    add        rsp, 20h\r
\r
    mov        edx, ebx          ; edx is ApIndex\r
    mov        ecx, esi\r
    add        ecx, LockLocation ; rcx is address of exchange info data buffer\r
\r
    mov        edi, esi\r
    add        edi, ApProcedureLocation\r
    mov        rax, qword [edi]\r
\r
    sub        rsp, 20h\r
    call       rax               ; Invoke C function\r
    add        rsp, 20h\r
    jmp        $                 ; Should never reach here\r
\r
RendezvousFunnelProcEnd:\r
\r
;-------------------------------------------------------------------------------------\r
;  AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish);\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(AsmRelocateApLoop)\r
ASM_PFX(AsmRelocateApLoop):\r
AsmRelocateApLoopStart:\r
    cli                          ; Disable interrupt before switching to 32-bit mode\r
    mov        rax, [rsp + 40]   ; CountTofinish\r
    lock dec   dword [rax]       ; (*CountTofinish)--\r
    mov        rsp, r9\r
    push       rcx\r
    push       rdx\r
\r
    lea        rsi, [PmEntry]    ; rsi <- The start address of transition code\r
\r
    push       r8\r
    push       rsi\r
    DB         0x48\r
    retf\r
BITS 32\r
PmEntry:\r
    mov        eax, cr0\r
    btr        eax, 31           ; Clear CR0.PG\r
    mov        cr0, eax          ; Disable paging and caches\r
\r
    mov        ebx, edx          ; Save EntryPoint to rbx, for rdmsr will overwrite rdx\r
    mov        ecx, 0xc0000080\r
    rdmsr\r
    and        ah, ~ 1           ; Clear LME\r
    wrmsr\r
    mov        eax, cr4\r
    and        al, ~ (1 << 5)    ; Clear PAE\r
    mov        cr4, eax\r
\r
    pop        edx\r
    add        esp, 4\r
    pop        ecx,\r
    add        esp, 4\r
    cmp        cl, 1              ; Check mwait-monitor support\r
    jnz        HltLoop\r
    mov        ebx, edx           ; Save C-State to ebx\r
MwaitLoop:\r
    cli\r
    mov        eax, esp           ; Set Monitor Address\r
    xor        ecx, ecx           ; ecx = 0\r
    xor        edx, edx           ; edx = 0\r
    monitor\r
    mov        eax, ebx           ; Mwait Cx, Target C-State per eax[7:4]\r
    shl        eax, 4\r
    mwait\r
    jmp        MwaitLoop\r
HltLoop:\r
    cli\r
    hlt\r
    jmp        HltLoop\r
BITS 64\r
AsmRelocateApLoopEnd:\r
\r
;-------------------------------------------------------------------------------------\r
;  AsmGetAddressMap (&AddressMap);\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(AsmGetAddressMap)\r
ASM_PFX(AsmGetAddressMap):\r
    lea        rax, [ASM_PFX(RendezvousFunnelProc)]\r
    mov        qword [rcx], rax\r
    mov        qword [rcx +  8h], LongModeStart - RendezvousFunnelProcStart\r
    mov        qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
    lea        rax, [ASM_PFX(AsmRelocateApLoop)]\r
    mov        qword [rcx + 18h], rax\r
    mov        qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart\r
    mov        qword [rcx + 28h], Flat32Start - RendezvousFunnelProcStart\r
    ret\r
\r
;-------------------------------------------------------------------------------------\r
;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
;about to become an AP. It switches its stack with the current AP.\r
;AsmExchangeRole (IN   CPU_EXCHANGE_INFO    *MyInfo, IN   CPU_EXCHANGE_INFO    *OthersInfo);\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(AsmExchangeRole)\r
ASM_PFX(AsmExchangeRole):\r
    ; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
    ; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
\r
    push       rax\r
    push       rbx\r
    push       rcx\r
    push       rdx\r
    push       rsi\r
    push       rdi\r
    push       rbp\r
    push       r8\r
    push       r9\r
    push       r10\r
    push       r11\r
    push       r12\r
    push       r13\r
    push       r14\r
    push       r15\r
\r
    mov        rax, cr0\r
    push       rax\r
\r
    mov        rax, cr4\r
    push       rax\r
\r
    ; rsi contains MyInfo pointer\r
    mov        rsi, rcx\r
\r
    ; rdi contains OthersInfo pointer\r
    mov        rdi, rdx\r
\r
    ;Store EFLAGS, GDTR and IDTR regiter to stack\r
    pushfq\r
    sgdt       [rsi + 16]\r
    sidt       [rsi + 26]\r
\r
    ; Store the its StackPointer\r
    mov        [rsi + 8], rsp\r
\r
    ; update its switch state to STORED\r
    mov        byte [rsi], CPU_SWITCH_STATE_STORED\r
\r
WaitForOtherStored:\r
    ; wait until the other CPU finish storing its state\r
    cmp        byte [rdi], CPU_SWITCH_STATE_STORED\r
    jz         OtherStored\r
    pause\r
    jmp        WaitForOtherStored\r
\r
OtherStored:\r
    ; Since another CPU already stored its state, load them\r
    ; load GDTR value\r
    lgdt       [rdi + 16]\r
\r
    ; load IDTR value\r
    lidt       [rdi + 26]\r
\r
    ; load its future StackPointer\r
    mov        rsp, [rdi + 8]\r
\r
    ; update the other CPU's switch state to LOADED\r
    mov        byte [rdi], CPU_SWITCH_STATE_LOADED\r
\r
WaitForOtherLoaded:\r
    ; wait until the other CPU finish loading new state,\r
    ; otherwise the data in stack may corrupt\r
    cmp        byte [rsi], CPU_SWITCH_STATE_LOADED\r
    jz         OtherLoaded\r
    pause\r
    jmp        WaitForOtherLoaded\r
\r
OtherLoaded:\r
    ; since the other CPU already get the data it want, leave this procedure\r
    popfq\r
\r
    pop        rax\r
    mov        cr4, rax\r
\r
    pop        rax\r
    mov        cr0, rax\r
\r
    pop        r15\r
    pop        r14\r
    pop        r13\r
    pop        r12\r
    pop        r11\r
    pop        r10\r
    pop        r9\r
    pop        r8\r
    pop        rbp\r
    pop        rdi\r
    pop        rsi\r
    pop        rdx\r
    pop        rcx\r
    pop        rbx\r
    pop        rax\r
\r
    ret\r
Commit	Line	Data
	1	;------------------------------------------------------------------------------ ;\r
	2	; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
	3	; SPDX-License-Identifier: BSD-2-Clause-Patent\r
	4	;\r
	5	; Module Name:\r
	6	;\r
	7	; MpFuncs.nasm\r
	8	;\r
	9	; Abstract:\r
	10	;\r
	11	; This is the assembly code for MP support\r
	12	;\r
	13	;-------------------------------------------------------------------------------\r
	14	\r
	15	%include "MpEqu.inc"\r
	16	extern ASM_PFX(InitializeFloatingPointUnits)\r
	17	\r
	18	DEFAULT REL\r
	19	\r
	20	SECTION .text\r
	21	\r
	22	;-------------------------------------------------------------------------------------\r
	23	;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
	24	;procedure serializes all the AP processors through an Init sequence. It must be\r
	25	;noted that APs arrive here very raw...ie: real mode, no stack.\r
	26	;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
	27	;IS IN MACHINE CODE.\r
	28	;-------------------------------------------------------------------------------------\r
	29	global ASM_PFX(RendezvousFunnelProc)\r
	30	ASM_PFX(RendezvousFunnelProc):\r
	31	RendezvousFunnelProcStart:\r
	32	; At this point CS = 0x(vv00) and ip= 0x0.\r
	33	; Save BIST information to ebp firstly\r
	34	\r
	35	BITS 16\r
	36	mov ebp, eax ; Save BIST information\r
	37	\r
	38	mov ax, cs\r
	39	mov ds, ax\r
	40	mov es, ax\r
	41	mov ss, ax\r
	42	xor ax, ax\r
	43	mov fs, ax\r
	44	mov gs, ax\r
	45	\r
	46	mov si, BufferStartLocation\r
	47	mov ebx, [si]\r
	48	\r
	49	mov si, DataSegmentLocation\r
	50	mov edx, [si]\r
	51	\r
	52	;\r
	53	; Get start address of 32-bit code in low memory (<1MB)\r
	54	;\r
	55	mov edi, ModeTransitionMemoryLocation\r
	56	\r
	57	mov si, GdtrLocation\r
	58	o32 lgdt [cs:si]\r
	59	\r
	60	mov si, IdtrLocation\r
	61	o32 lidt [cs:si]\r
	62	\r
	63	;\r
	64	; Switch to protected mode\r
	65	;\r
	66	mov eax, cr0 ; Get control register 0\r
	67	or eax, 000000003h ; Set PE bit (bit #0) & MP\r
	68	mov cr0, eax\r
	69	\r
	70	; Switch to 32-bit code (>1MB)\r
	71	o32 jmp far [cs:di]\r
	72	\r
	73	;\r
	74	; Following code must be copied to memory with type of EfiBootServicesCode.\r
	75	; This is required if NX is enabled for EfiBootServicesCode of memory.\r
	76	;\r
	77	BITS 32\r
	78	Flat32Start: ; protected mode entry point\r
	79	mov ds, dx\r
	80	mov es, dx\r
	81	mov fs, dx\r
	82	mov gs, dx\r
	83	mov ss, dx\r
	84	\r
	85	;\r
	86	; Enable execute disable bit\r
	87	;\r
	88	mov esi, EnableExecuteDisableLocation\r
	89	cmp byte [ebx + esi], 0\r
	90	jz SkipEnableExecuteDisableBit\r
	91	\r
	92	mov ecx, 0c0000080h ; EFER MSR number\r
	93	rdmsr ; Read EFER\r
	94	bts eax, 11 ; Enable Execute Disable Bit\r
	95	wrmsr ; Write EFER\r
	96	\r
	97	SkipEnableExecuteDisableBit:\r
	98	;\r
	99	; Enable PAE\r
	100	;\r
	101	mov eax, cr4\r
	102	bts eax, 5\r
	103	mov cr4, eax\r
	104	\r
	105	;\r
	106	; Load page table\r
	107	;\r
	108	mov esi, Cr3Location ; Save CR3 in ecx\r
	109	mov ecx, [ebx + esi]\r
	110	mov cr3, ecx ; Load CR3\r
	111	\r
	112	;\r
	113	; Enable long mode\r
	114	;\r
	115	mov ecx, 0c0000080h ; EFER MSR number\r
	116	rdmsr ; Read EFER\r
	117	bts eax, 8 ; Set LME=1\r
	118	wrmsr ; Write EFER\r
	119	\r
	120	;\r
	121	; Enable paging\r
	122	;\r
	123	mov eax, cr0 ; Read CR0\r
	124	bts eax, 31 ; Set PG=1\r
	125	mov cr0, eax ; Write CR0\r
	126	\r
	127	;\r
	128	; Far jump to 64-bit code\r
	129	;\r
	130	mov edi, ModeHighMemoryLocation\r
	131	add edi, ebx\r
	132	jmp far [edi]\r
	133	\r
	134	BITS 64\r
	135	LongModeStart:\r
	136	mov esi, ebx\r
	137	lea edi, [esi + InitFlagLocation]\r
	138	cmp qword [edi], 1 ; ApInitConfig\r
	139	jnz GetApicId\r
	140	\r
	141	; Increment the number of APs executing here as early as possible\r
	142	; This is decremented in C code when AP is finished executing\r
	143	mov edi, esi\r
	144	add edi, NumApsExecutingLocation\r
	145	lock inc dword [edi]\r
	146	\r
	147	; AP init\r
	148	mov edi, esi\r
	149	add edi, LockLocation\r
	150	mov rax, NotVacantFlag\r
	151	\r
	152	TestLock:\r
	153	xchg qword [edi], rax\r
	154	cmp rax, NotVacantFlag\r
	155	jz TestLock\r
	156	\r
	157	lea ecx, [esi + ApIndexLocation]\r
	158	inc dword [ecx]\r
	159	mov ebx, [ecx]\r
	160	\r
	161	Releaselock:\r
	162	mov rax, VacantFlag\r
	163	xchg qword [edi], rax\r
	164	; program stack\r
	165	mov edi, esi\r
	166	add edi, StackSizeLocation\r
	167	mov eax, dword [edi]\r
	168	mov ecx, ebx\r
	169	inc ecx\r
	170	mul ecx ; EAX = StackSize * (CpuNumber + 1)\r
	171	mov edi, esi\r
	172	add edi, StackStartAddressLocation\r
	173	add rax, qword [edi]\r
	174	mov rsp, rax\r
	175	jmp CProcedureInvoke\r
	176	\r
	177	GetApicId:\r
	178	mov eax, 0\r
	179	cpuid\r
	180	cmp eax, 0bh\r
	181	jb NoX2Apic ; CPUID level below CPUID_EXTENDED_TOPOLOGY\r
	182	\r
	183	mov eax, 0bh\r
	184	xor ecx, ecx\r
	185	cpuid\r
	186	test ebx, 0ffffh\r
	187	jz NoX2Apic ; CPUID.0BH:EBX[15:0] is zero\r
	188	\r
	189	; Processor is x2APIC capable; 32-bit x2APIC ID is already in EDX\r
	190	jmp GetProcessorNumber\r
	191	\r
	192	NoX2Apic:\r
	193	; Processor is not x2APIC capable, so get 8-bit APIC ID\r
	194	mov eax, 1\r
	195	cpuid\r
	196	shr ebx, 24\r
	197	mov edx, ebx\r
	198	\r
	199	GetProcessorNumber:\r
	200	;\r
	201	; Get processor number for this AP\r
	202	; Note that BSP may become an AP due to SwitchBsp()\r
	203	;\r
	204	xor ebx, ebx\r
	205	lea eax, [esi + CpuInfoLocation]\r
	206	mov edi, [eax]\r
	207	\r
	208	GetNextProcNumber:\r
	209	cmp dword [edi], edx ; APIC ID match?\r
	210	jz ProgramStack\r
	211	add edi, 20\r
	212	inc ebx\r
	213	jmp GetNextProcNumber\r
	214	\r
	215	ProgramStack:\r
	216	mov rsp, qword [edi + 12]\r
	217	\r
	218	CProcedureInvoke:\r
	219	push rbp ; Push BIST data at top of AP stack\r
	220	xor rbp, rbp ; Clear ebp for call stack trace\r
	221	push rbp\r
	222	mov rbp, rsp\r
	223	\r
	224	mov rax, qword [esi + InitializeFloatingPointUnitsAddress]\r
	225	sub rsp, 20h\r
	226	call rax ; Call assembly function to initialize FPU per UEFI spec\r
	227	add rsp, 20h\r
	228	\r
	229	mov edx, ebx ; edx is ApIndex\r
	230	mov ecx, esi\r
	231	add ecx, LockLocation ; rcx is address of exchange info data buffer\r
	232	\r
	233	mov edi, esi\r
	234	add edi, ApProcedureLocation\r
	235	mov rax, qword [edi]\r
	236	\r
	237	sub rsp, 20h\r
	238	call rax ; Invoke C function\r
	239	add rsp, 20h\r
	240	jmp $ ; Should never reach here\r
	241	\r
	242	RendezvousFunnelProcEnd:\r
	243	\r
	244	;-------------------------------------------------------------------------------------\r
	245	; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish);\r
	246	;-------------------------------------------------------------------------------------\r
	247	global ASM_PFX(AsmRelocateApLoop)\r
	248	ASM_PFX(AsmRelocateApLoop):\r
	249	AsmRelocateApLoopStart:\r
	250	cli ; Disable interrupt before switching to 32-bit mode\r
	251	mov rax, [rsp + 40] ; CountTofinish\r
	252	lock dec dword [rax] ; (*CountTofinish)--\r
	253	mov rsp, r9\r
	254	push rcx\r
	255	push rdx\r
	256	\r
	257	lea rsi, [PmEntry] ; rsi <- The start address of transition code\r
	258	\r
	259	push r8\r
	260	push rsi\r
	261	DB 0x48\r
	262	retf\r
	263	BITS 32\r
	264	PmEntry:\r
	265	mov eax, cr0\r
	266	btr eax, 31 ; Clear CR0.PG\r
	267	mov cr0, eax ; Disable paging and caches\r
	268	\r
	269	mov ebx, edx ; Save EntryPoint to rbx, for rdmsr will overwrite rdx\r
	270	mov ecx, 0xc0000080\r
	271	rdmsr\r
	272	and ah, ~ 1 ; Clear LME\r
	273	wrmsr\r
	274	mov eax, cr4\r
	275	and al, ~ (1 << 5) ; Clear PAE\r
	276	mov cr4, eax\r
	277	\r
	278	pop edx\r
	279	add esp, 4\r
	280	pop ecx,\r
	281	add esp, 4\r
	282	cmp cl, 1 ; Check mwait-monitor support\r
	283	jnz HltLoop\r
	284	mov ebx, edx ; Save C-State to ebx\r
	285	MwaitLoop:\r
	286	cli\r
	287	mov eax, esp ; Set Monitor Address\r
	288	xor ecx, ecx ; ecx = 0\r
	289	xor edx, edx ; edx = 0\r
	290	monitor\r
	291	mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4]\r
	292	shl eax, 4\r
	293	mwait\r
	294	jmp MwaitLoop\r
	295	HltLoop:\r
	296	cli\r
	297	hlt\r
	298	jmp HltLoop\r
	299	BITS 64\r
	300	AsmRelocateApLoopEnd:\r
	301	\r
	302	;-------------------------------------------------------------------------------------\r
	303	; AsmGetAddressMap (&AddressMap);\r
	304	;-------------------------------------------------------------------------------------\r
	305	global ASM_PFX(AsmGetAddressMap)\r
	306	ASM_PFX(AsmGetAddressMap):\r
	307	lea rax, [ASM_PFX(RendezvousFunnelProc)]\r
	308	mov qword [rcx], rax\r
	309	mov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcStart\r
	310	mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
	311	lea rax, [ASM_PFX(AsmRelocateApLoop)]\r
	312	mov qword [rcx + 18h], rax\r
	313	mov qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart\r
	314	mov qword [rcx + 28h], Flat32Start - RendezvousFunnelProcStart\r
	315	ret\r
	316	\r
	317	;-------------------------------------------------------------------------------------\r
	318	;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
	319	;about to become an AP. It switches its stack with the current AP.\r
	320	;AsmExchangeRole (IN CPU_EXCHANGE_INFO MyInfo, IN CPU_EXCHANGE_INFO OthersInfo);\r
	321	;-------------------------------------------------------------------------------------\r
	322	global ASM_PFX(AsmExchangeRole)\r
	323	ASM_PFX(AsmExchangeRole):\r
	324	; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
	325	; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
	326	\r
	327	push rax\r
	328	push rbx\r
	329	push rcx\r
	330	push rdx\r
	331	push rsi\r
	332	push rdi\r
	333	push rbp\r
	334	push r8\r
	335	push r9\r
	336	push r10\r
	337	push r11\r
	338	push r12\r
	339	push r13\r
	340	push r14\r
	341	push r15\r
	342	\r
	343	mov rax, cr0\r
	344	push rax\r
	345	\r
	346	mov rax, cr4\r
	347	push rax\r
	348	\r
	349	; rsi contains MyInfo pointer\r
	350	mov rsi, rcx\r
	351	\r
	352	; rdi contains OthersInfo pointer\r
	353	mov rdi, rdx\r
	354	\r
	355	;Store EFLAGS, GDTR and IDTR regiter to stack\r
	356	pushfq\r
	357	sgdt [rsi + 16]\r
	358	sidt [rsi + 26]\r
	359	\r
	360	; Store the its StackPointer\r
	361	mov [rsi + 8], rsp\r
	362	\r
	363	; update its switch state to STORED\r
	364	mov byte [rsi], CPU_SWITCH_STATE_STORED\r
	365	\r
	366	WaitForOtherStored:\r
	367	; wait until the other CPU finish storing its state\r
	368	cmp byte [rdi], CPU_SWITCH_STATE_STORED\r
	369	jz OtherStored\r
	370	pause\r
	371	jmp WaitForOtherStored\r
	372	\r
	373	OtherStored:\r
	374	; Since another CPU already stored its state, load them\r
	375	; load GDTR value\r
	376	lgdt [rdi + 16]\r
	377	\r
	378	; load IDTR value\r
	379	lidt [rdi + 26]\r
	380	\r
	381	; load its future StackPointer\r
	382	mov rsp, [rdi + 8]\r
	383	\r
	384	; update the other CPU's switch state to LOADED\r
	385	mov byte [rdi], CPU_SWITCH_STATE_LOADED\r
	386	\r
	387	WaitForOtherLoaded:\r
	388	; wait until the other CPU finish loading new state,\r
	389	; otherwise the data in stack may corrupt\r
	390	cmp byte [rsi], CPU_SWITCH_STATE_LOADED\r
	391	jz OtherLoaded\r
	392	pause\r
	393	jmp WaitForOtherLoaded\r
	394	\r
	395	OtherLoaded:\r
	396	; since the other CPU already get the data it want, leave this procedure\r
	397	popfq\r
	398	\r
	399	pop rax\r
	400	mov cr4, rax\r
	401	\r
	402	pop rax\r
	403	mov cr0, rax\r
	404	\r
	405	pop r15\r
	406	pop r14\r
	407	pop r13\r
	408	pop r12\r
	409	pop r11\r
	410	pop r10\r
	411	pop r9\r
	412	pop r8\r
	413	pop rbp\r
	414	pop rdi\r
	415	pop rsi\r
	416	pop rdx\r
	417	pop rcx\r
	418	pop rbx\r
	419	pop rax\r
	420	\r
	421	ret\r