[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.h

/** @file\r
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
\r
Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _CPU_PISMMCPUDXESMM_H_\r
#define _CPU_PISMMCPUDXESMM_H_\r
\r
#include <PiSmm.h>\r
\r
#include <Protocol/MpService.h>\r
#include <Protocol/SmmConfiguration.h>\r
#include <Protocol/SmmCpu.h>\r
#include <Protocol/SmmAccess2.h>\r
#include <Protocol/SmmReadyToLock.h>\r
#include <Protocol/SmmCpuService.h>\r
\r
#include <Guid/AcpiS3Context.h>\r
#include <Guid/PiSmmMemoryAttributesTable.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/SynchronizationLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/CacheMaintenanceLib.h>\r
#include <Library/MtrrLib.h>\r
#include <Library/SmmCpuPlatformHookLib.h>\r
#include <Library/SmmServicesTableLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/UefiRuntimeServicesTableLib.h>\r
#include <Library/DebugAgentLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/LocalApicLib.h>\r
#include <Library/UefiCpuLib.h>\r
#include <Library/CpuExceptionHandlerLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/SmmCpuFeaturesLib.h>\r
#include <Library/PeCoffGetEntryPointLib.h>\r
\r
#include <AcpiCpuData.h>\r
#include <CpuHotPlugData.h>\r
\r
#include <Register/Cpuid.h>\r
#include <Register/Msr.h>\r
\r
#include "CpuService.h"\r
#include "SmmProfile.h"\r
\r
//\r
// MSRs required for configuration of SMM Code Access Check\r
//\r
#define EFI_MSR_SMM_MCA_CAP                    0x17D\r
#define  SMM_CODE_ACCESS_CHK_BIT               BIT58\r
\r
#define  SMM_FEATURE_CONTROL_LOCK_BIT          BIT0\r
#define  SMM_CODE_CHK_EN_BIT                   BIT2\r
\r
///\r
/// Page Table Entry\r
///\r
#define IA32_PG_P                   BIT0\r
#define IA32_PG_RW                  BIT1\r
#define IA32_PG_U                   BIT2\r
#define IA32_PG_WT                  BIT3\r
#define IA32_PG_CD                  BIT4\r
#define IA32_PG_A                   BIT5\r
#define IA32_PG_D                   BIT6\r
#define IA32_PG_PS                  BIT7\r
#define IA32_PG_PAT_2M              BIT12\r
#define IA32_PG_PAT_4K              IA32_PG_PS\r
#define IA32_PG_PMNT                BIT62\r
#define IA32_PG_NX                  BIT63\r
\r
#define PAGE_ATTRIBUTE_BITS         (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r
//\r
// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
// X64 PAE PDPTE does not have such restriction\r
//\r
#define IA32_PAE_PDPTE_ATTRIBUTE_BITS    (IA32_PG_P)\r
\r
#define PAGE_PROGATE_BITS           (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r
\r
#define PAGING_4K_MASK  0xFFF\r
#define PAGING_2M_MASK  0x1FFFFF\r
#define PAGING_1G_MASK  0x3FFFFFFF\r
\r
#define PAGING_PAE_INDEX_MASK  0x1FF\r
\r
#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
\r
#define SMRR_MAX_ADDRESS       BASE_4GB\r
\r
typedef enum {\r
  PageNone,\r
  Page4K,\r
  Page2M,\r
  Page1G,\r
} PAGE_ATTRIBUTE;\r
\r
typedef struct {\r
  PAGE_ATTRIBUTE   Attribute;\r
  UINT64           Length;\r
  UINT64           AddressMask;\r
} PAGE_ATTRIBUTE_TABLE;\r
\r
//\r
// Size of Task-State Segment defined in IA32 Manual\r
//\r
#define TSS_SIZE              104\r
#define TSS_X64_IST1_OFFSET   36\r
#define TSS_IA32_CR3_OFFSET   28\r
#define TSS_IA32_ESP_OFFSET   56\r
\r
#define CR0_WP                BIT16\r
\r
//\r
// Code select value\r
//\r
#define PROTECT_MODE_CODE_SEGMENT          0x08\r
#define LONG_MODE_CODE_SEGMENT             0x38\r
\r
//\r
// The size 0x20 must be bigger than\r
// the size of template code of SmmInit. Currently,\r
// the size of SmmInit requires the 0x16 Bytes buffer\r
// at least.\r
//\r
#define BACK_BUF_SIZE  0x20\r
\r
#define EXCEPTION_VECTOR_NUMBER     0x20\r
\r
#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r
\r
typedef UINT32                              SMM_CPU_ARRIVAL_EXCEPTIONS;\r
#define ARRIVAL_EXCEPTION_BLOCKED           0x1\r
#define ARRIVAL_EXCEPTION_DELAYED           0x2\r
#define ARRIVAL_EXCEPTION_SMI_DISABLED      0x4\r
\r
//\r
// Private structure for the SMM CPU module that is stored in DXE Runtime memory\r
// Contains the SMM Configuration Protocols that is produced.\r
// Contains a mix of DXE and SMM contents.  All the fields must be used properly.\r
//\r
#define SMM_CPU_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('s', 'c', 'p', 'u')\r
\r
typedef struct {\r
  UINTN                           Signature;\r
\r
  EFI_HANDLE                      SmmCpuHandle;\r
\r
  EFI_PROCESSOR_INFORMATION       *ProcessorInfo;\r
  SMM_CPU_OPERATION               *Operation;\r
  UINTN                           *CpuSaveStateSize;\r
  VOID                            **CpuSaveState;\r
\r
  EFI_SMM_RESERVED_SMRAM_REGION   SmmReservedSmramRegion[1];\r
  EFI_SMM_ENTRY_CONTEXT           SmmCoreEntryContext;\r
  EFI_SMM_ENTRY_POINT             SmmCoreEntry;\r
\r
  EFI_SMM_CONFIGURATION_PROTOCOL  SmmConfiguration;\r
} SMM_CPU_PRIVATE_DATA;\r
\r
extern SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate;\r
extern CPU_HOT_PLUG_DATA      mCpuHotPlugData;\r
extern UINTN                  mMaxNumberOfCpus;\r
extern UINTN                  mNumberOfCpus;\r
extern EFI_SMM_CPU_PROTOCOL   mSmmCpu;\r
\r
///\r
/// The mode of the CPU at the time an SMI occurs\r
///\r
extern UINT8  mSmmSaveStateRegisterLma;\r
\r
//\r
// SMM CPU Protocol function prototypes.\r
//\r
\r
/**\r
  Read information from the CPU save state.\r
\r
  @param  This      EFI_SMM_CPU_PROTOCOL instance\r
  @param  Width     The number of bytes to read from the CPU save state.\r
  @param  Register  Specifies the CPU register to read form the save state.\r
  @param  CpuIndex  Specifies the zero-based index of the CPU save state\r
  @param  Buffer    Upon return, this holds the CPU register value read from the save state.\r
\r
  @retval EFI_SUCCESS   The register was read from Save State\r
  @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
  @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmReadSaveState (\r
  IN CONST EFI_SMM_CPU_PROTOCOL         *This,\r
  IN UINTN                              Width,\r
  IN EFI_SMM_SAVE_STATE_REGISTER        Register,\r
  IN UINTN                              CpuIndex,\r
  OUT VOID                              *Buffer\r
  );\r
\r
/**\r
  Write data to the CPU save state.\r
\r
  @param  This      EFI_SMM_CPU_PROTOCOL instance\r
  @param  Width     The number of bytes to read from the CPU save state.\r
  @param  Register  Specifies the CPU register to write to the save state.\r
  @param  CpuIndex  Specifies the zero-based index of the CPU save state\r
  @param  Buffer    Upon entry, this holds the new CPU register value.\r
\r
  @retval EFI_SUCCESS   The register was written from Save State\r
  @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
  @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmWriteSaveState (\r
  IN CONST EFI_SMM_CPU_PROTOCOL         *This,\r
  IN UINTN                              Width,\r
  IN EFI_SMM_SAVE_STATE_REGISTER        Register,\r
  IN UINTN                              CpuIndex,\r
  IN CONST VOID                         *Buffer\r
  );\r
\r
/**\r
Read a CPU Save State register on the target processor.\r
\r
This function abstracts the differences that whether the CPU Save State register is in the\r
IA32 CPU Save State Map or X64 CPU Save State Map.\r
\r
This function supports reading a CPU Save State register in SMBase relocation handler.\r
\r
@param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.\r
@param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.\r
@param[in]  Width          The number of bytes to read from the CPU save state.\r
@param[out] Buffer         Upon return, this holds the CPU register value read from the save state.\r
\r
@retval EFI_SUCCESS           The register was read from Save State.\r
@retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.\r
@retval EFI_INVALID_PARAMTER  This or Buffer is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
ReadSaveStateRegister (\r
  IN UINTN                        CpuIndex,\r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN UINTN                        Width,\r
  OUT VOID                        *Buffer\r
  );\r
\r
/**\r
Write value to a CPU Save State register on the target processor.\r
\r
This function abstracts the differences that whether the CPU Save State register is in the\r
IA32 CPU Save State Map or X64 CPU Save State Map.\r
\r
This function supports writing a CPU Save State register in SMBase relocation handler.\r
\r
@param[in] CpuIndex       Specifies the zero-based index of the CPU save state.\r
@param[in] RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.\r
@param[in] Width          The number of bytes to read from the CPU save state.\r
@param[in] Buffer         Upon entry, this holds the new CPU register value.\r
\r
@retval EFI_SUCCESS           The register was written to Save State.\r
@retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.\r
@retval EFI_INVALID_PARAMTER  ProcessorIndex or Width is not correct.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
WriteSaveStateRegister (\r
  IN UINTN                        CpuIndex,\r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN UINTN                        Width,\r
  IN CONST VOID                   *Buffer\r
  );\r
\r
//\r
//\r
//\r
typedef struct {\r
  UINT32                            Offset;\r
  UINT16                            Segment;\r
  UINT16                            Reserved;\r
} IA32_FAR_ADDRESS;\r
\r
extern IA32_FAR_ADDRESS             gSmmJmpAddr;\r
\r
extern CONST UINT8                  gcSmmInitTemplate[];\r
extern CONST UINT16                 gcSmmInitSize;\r
extern UINT32                       gSmmCr0;\r
extern UINT32                       gSmmCr3;\r
extern UINT32                       gSmmCr4;\r
extern UINTN                        gSmmInitStack;\r
\r
/**\r
  Semaphore operation for all processor relocate SMMBase.\r
**/\r
VOID\r
EFIAPI\r
SmmRelocationSemaphoreComplete (\r
  VOID\r
  );\r
\r
///\r
/// The type of SMM CPU Information\r
///\r
typedef struct {\r
  SPIN_LOCK                         *Busy;\r
  volatile EFI_AP_PROCEDURE         Procedure;\r
  volatile VOID                     *Parameter;\r
  volatile UINT32                   *Run;\r
  volatile BOOLEAN                  *Present;\r
} SMM_CPU_DATA_BLOCK;\r
\r
typedef enum {\r
  SmmCpuSyncModeTradition,\r
  SmmCpuSyncModeRelaxedAp,\r
  SmmCpuSyncModeMax\r
} SMM_CPU_SYNC_MODE;\r
\r
typedef struct {\r
  //\r
  // Pointer to an array. The array should be located immediately after this structure\r
  // so that UC cache-ability can be set together.\r
  //\r
  SMM_CPU_DATA_BLOCK            *CpuData;\r
  volatile UINT32               *Counter;\r
  volatile UINT32               BspIndex;\r
  volatile BOOLEAN              *InsideSmm;\r
  volatile BOOLEAN              *AllCpusInSync;\r
  volatile SMM_CPU_SYNC_MODE    EffectiveSyncMode;\r
  volatile BOOLEAN              SwitchBsp;\r
  volatile BOOLEAN              *CandidateBsp;\r
} SMM_DISPATCHER_MP_SYNC_DATA;\r
\r
#define MSR_SPIN_LOCK_INIT_NUM 15\r
\r
typedef struct {\r
  SPIN_LOCK    *SpinLock;\r
  UINT32       MsrIndex;\r
} MP_MSR_LOCK;\r
\r
#define SMM_PSD_OFFSET              0xfb00\r
\r
///\r
/// All global semaphores' pointer\r
///\r
typedef struct {\r
  volatile UINT32      *Counter;\r
  volatile BOOLEAN     *InsideSmm;\r
  volatile BOOLEAN     *AllCpusInSync;\r
  SPIN_LOCK            *PFLock;\r
  SPIN_LOCK            *CodeAccessCheckLock;\r
  SPIN_LOCK            *MemoryMappedLock;\r
} SMM_CPU_SEMAPHORE_GLOBAL;\r
\r
///\r
/// All semaphores for each processor\r
///\r
typedef struct {\r
  SPIN_LOCK                         *Busy;\r
  volatile UINT32                   *Run;\r
  volatile BOOLEAN                  *Present;\r
} SMM_CPU_SEMAPHORE_CPU;\r
\r
///\r
/// All MSRs semaphores' pointer and counter\r
///\r
typedef struct {\r
  SPIN_LOCK            *Msr;\r
  UINTN                AvailableCounter;\r
} SMM_CPU_SEMAPHORE_MSR;\r
\r
///\r
/// All semaphores' information\r
///\r
typedef struct {\r
  SMM_CPU_SEMAPHORE_GLOBAL          SemaphoreGlobal;\r
  SMM_CPU_SEMAPHORE_CPU             SemaphoreCpu;\r
  SMM_CPU_SEMAPHORE_MSR             SemaphoreMsr;\r
} SMM_CPU_SEMAPHORES;\r
\r
extern IA32_DESCRIPTOR                     gcSmiGdtr;\r
extern EFI_PHYSICAL_ADDRESS                mGdtBuffer;\r
extern UINTN                               mGdtBufferSize;\r
extern IA32_DESCRIPTOR                     gcSmiIdtr;\r
extern VOID                                *gcSmiIdtrPtr;\r
extern UINT64                              gPhyMask;\r
extern SMM_DISPATCHER_MP_SYNC_DATA         *mSmmMpSyncData;\r
extern UINTN                               mSmmStackArrayBase;\r
extern UINTN                               mSmmStackArrayEnd;\r
extern UINTN                               mSmmStackSize;\r
extern EFI_SMM_CPU_SERVICE_PROTOCOL        mSmmCpuService;\r
extern IA32_DESCRIPTOR                     gcSmiInitGdtr;\r
extern SMM_CPU_SEMAPHORES                  mSmmCpuSemaphores;\r
extern UINTN                               mSemaphoreSize;\r
extern SPIN_LOCK                           *mPFLock;\r
extern SPIN_LOCK                           *mConfigSmmCodeAccessCheckLock;\r
extern SPIN_LOCK                           *mMemoryMappedLock;\r
extern EFI_SMRAM_DESCRIPTOR                *mSmmCpuSmramRanges;\r
extern UINTN                               mSmmCpuSmramRangeCount;\r
\r
//\r
// Copy of the PcdPteMemoryEncryptionAddressOrMask\r
//\r
extern UINT64  mAddressEncMask;\r
\r
/**\r
  Create 4G PageTable in SMRAM.\r
\r
  @param[in]      Is32BitPageTable Whether the page table is 32-bit PAE\r
  @return         PageTable Address\r
\r
**/\r
UINT32\r
Gen4GPageTable (\r
  IN      BOOLEAN                   Is32BitPageTable\r
  );\r
\r
\r
/**\r
  Initialize global data for MP synchronization.\r
\r
  @param Stacks       Base address of SMI stack buffer for all processors.\r
  @param StackSize    Stack size for each processor in SMM.\r
\r
**/\r
UINT32\r
InitializeMpServiceData (\r
  IN VOID        *Stacks,\r
  IN UINTN       StackSize\r
  );\r
\r
/**\r
  Initialize Timer for SMM AP Sync.\r
\r
**/\r
VOID\r
InitializeSmmTimer (\r
  VOID\r
  );\r
\r
/**\r
  Start Timer for SMM AP Sync.\r
\r
**/\r
UINT64\r
EFIAPI\r
StartSyncTimer (\r
  VOID\r
  );\r
\r
/**\r
  Check if the SMM AP Sync timer is timeout.\r
\r
  @param Timer  The start timer from the begin.\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
IsSyncTimerTimeout (\r
  IN      UINT64                    Timer\r
  );\r
\r
/**\r
  Initialize IDT for SMM Stack Guard.\r
\r
**/\r
VOID\r
EFIAPI\r
InitializeIDTSmmStackGuard (\r
  VOID\r
  );\r
\r
/**\r
  Initialize Gdt for all processors.\r
\r
  @param[in]   Cr3          CR3 value.\r
  @param[out]  GdtStepSize  The step size for GDT table.\r
\r
  @return GdtBase for processor 0.\r
          GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r
**/\r
VOID *\r
InitGdt (\r
  IN  UINTN  Cr3,\r
  OUT UINTN  *GdtStepSize\r
  );\r
\r
/**\r
  This function sets GDT/IDT buffer to be RO and XP.\r
**/\r
VOID\r
PatchGdtIdtMap (\r
  VOID\r
  );\r
\r
/**\r
\r
  Register the SMM Foundation entry point.\r
\r
  @param          This              Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r
  @param          SmmEntryPoint     SMM Foundation EntryPoint\r
\r
  @retval         EFI_SUCCESS       Successfully to register SMM foundation entry point\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RegisterSmmEntry (\r
  IN CONST EFI_SMM_CONFIGURATION_PROTOCOL  *This,\r
  IN EFI_SMM_ENTRY_POINT                   SmmEntryPoint\r
  );\r
\r
/**\r
  Create PageTable for SMM use.\r
\r
  @return     PageTable Address\r
\r
**/\r
UINT32\r
SmmInitPageTable (\r
  VOID\r
  );\r
\r
/**\r
  Schedule a procedure to run on the specified CPU.\r
\r
  @param   Procedure        The address of the procedure to run\r
  @param   CpuIndex         Target CPU number\r
  @param   ProcArguments    The parameter to pass to the procedure\r
\r
  @retval   EFI_INVALID_PARAMETER    CpuNumber not valid\r
  @retval   EFI_INVALID_PARAMETER    CpuNumber specifying BSP\r
  @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM\r
  @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy\r
  @retval   EFI_SUCCESS - The procedure has been successfully scheduled\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmStartupThisAp (\r
  IN      EFI_AP_PROCEDURE          Procedure,\r
  IN      UINTN                     CpuIndex,\r
  IN OUT  VOID                      *ProcArguments OPTIONAL\r
  );\r
\r
/**\r
  Schedule a procedure to run on the specified CPU in a blocking fashion.\r
\r
  @param  Procedure                The address of the procedure to run\r
  @param  CpuIndex                 Target CPU Index\r
  @param  ProcArguments            The parameter to pass to the procedure\r
\r
  @retval EFI_INVALID_PARAMETER    CpuNumber not valid\r
  @retval EFI_INVALID_PARAMETER    CpuNumber specifying BSP\r
  @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM\r
  @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy\r
  @retval EFI_SUCCESS              The procedure has been successfully scheduled\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmBlockingStartupThisAp (\r
  IN      EFI_AP_PROCEDURE          Procedure,\r
  IN      UINTN                     CpuIndex,\r
  IN OUT  VOID                      *ProcArguments OPTIONAL\r
  );\r
\r
/**\r
  This function sets the attributes for the memory region specified by BaseAddress and\r
  Length from their current attributes to the attributes specified by Attributes.\r
\r
  @param[in]  BaseAddress      The physical address that is the start address of a memory region.\r
  @param[in]  Length           The size in bytes of the memory region.\r
  @param[in]  Attributes       The bit mask of attributes to set for the memory region.\r
\r
  @retval EFI_SUCCESS           The attributes were set for the memory region.\r
  @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by\r
                                BaseAddress and Length cannot be modified.\r
  @retval EFI_INVALID_PARAMETER Length is zero.\r
                                Attributes specified an illegal combination of attributes that\r
                                cannot be set together.\r
  @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of\r
                                the memory resource range.\r
  @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory\r
                                resource range specified by BaseAddress and Length.\r
                                The bit mask of attributes is not support for the memory resource\r
                                range specified by BaseAddress and Length.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmSetMemoryAttributes (\r
  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
  IN  UINT64                                     Length,\r
  IN  UINT64                                     Attributes\r
  );\r
\r
/**\r
  This function clears the attributes for the memory region specified by BaseAddress and\r
  Length from their current attributes to the attributes specified by Attributes.\r
\r
  @param[in]  BaseAddress      The physical address that is the start address of a memory region.\r
  @param[in]  Length           The size in bytes of the memory region.\r
  @param[in]  Attributes       The bit mask of attributes to clear for the memory region.\r
\r
  @retval EFI_SUCCESS           The attributes were cleared for the memory region.\r
  @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by\r
                                BaseAddress and Length cannot be modified.\r
  @retval EFI_INVALID_PARAMETER Length is zero.\r
                                Attributes specified an illegal combination of attributes that\r
                                cannot be set together.\r
  @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of\r
                                the memory resource range.\r
  @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory\r
                                resource range specified by BaseAddress and Length.\r
                                The bit mask of attributes is not support for the memory resource\r
                                range specified by BaseAddress and Length.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmClearMemoryAttributes (\r
  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
  IN  UINT64                                     Length,\r
  IN  UINT64                                     Attributes\r
  );\r
\r
/**\r
  Initialize MP synchronization data.\r
\r
**/\r
VOID\r
EFIAPI\r
InitializeMpSyncData (\r
  VOID\r
  );\r
\r
/**\r
\r
  Find out SMRAM information including SMRR base and SMRR size.\r
\r
  @param          SmrrBase          SMRR base\r
  @param          SmrrSize          SMRR size\r
\r
**/\r
VOID\r
FindSmramInfo (\r
  OUT UINT32   *SmrrBase,\r
  OUT UINT32   *SmrrSize\r
  );\r
\r
/**\r
  Relocate SmmBases for each processor.\r
\r
  Execute on first boot and all S3 resumes\r
\r
**/\r
VOID\r
EFIAPI\r
SmmRelocateBases (\r
  VOID\r
  );\r
\r
/**\r
  Page Fault handler for SMM use.\r
\r
  @param  InterruptType    Defines the type of interrupt or exception that\r
                           occurred on the processor.This parameter is processor architecture specific.\r
  @param  SystemContext    A pointer to the processor context when\r
                           the interrupt occurred on the processor.\r
**/\r
VOID\r
EFIAPI\r
SmiPFHandler (\r
  IN EFI_EXCEPTION_TYPE   InterruptType,\r
  IN EFI_SYSTEM_CONTEXT   SystemContext\r
  );\r
\r
/**\r
  Perform the remaining tasks.\r
\r
**/\r
VOID\r
PerformRemainingTasks (\r
  VOID\r
  );\r
\r
/**\r
  Perform the pre tasks.\r
\r
**/\r
VOID\r
PerformPreTasks (\r
  VOID\r
  );\r
\r
/**\r
  Initialize MSR spin lock by MSR index.\r
\r
  @param  MsrIndex       MSR index value.\r
\r
**/\r
VOID\r
InitMsrSpinLockByIndex (\r
  IN UINT32      MsrIndex\r
  );\r
\r
/**\r
  Hook return address of SMM Save State so that semaphore code\r
  can be executed immediately after AP exits SMM to indicate to\r
  the BSP that an AP has exited SMM after SMBASE relocation.\r
\r
  @param[in] CpuIndex     The processor index.\r
  @param[in] RebasedFlag  A pointer to a flag that is set to TRUE\r
                          immediately after AP exits SMM.\r
\r
**/\r
VOID\r
SemaphoreHook (\r
  IN UINTN             CpuIndex,\r
  IN volatile BOOLEAN  *RebasedFlag\r
  );\r
\r
/**\r
Configure SMM Code Access Check feature for all processors.\r
SMM Feature Control MSR will be locked after configuration.\r
**/\r
VOID\r
ConfigSmmCodeAccessCheck (\r
  VOID\r
  );\r
\r
/**\r
  Hook the code executed immediately after an RSM instruction on the currently\r
  executing CPU.  The mode of code executed immediately after RSM must be\r
  detected, and the appropriate hook must be selected.  Always clear the auto\r
  HALT restart flag if it is set.\r
\r
  @param[in] CpuIndex                 The processor index for the currently\r
                                      executing CPU.\r
  @param[in] CpuState                 Pointer to SMRAM Save State Map for the\r
                                      currently executing CPU.\r
  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to\r
                                      32-bit mode from 64-bit SMM.\r
  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to\r
                                      same mode as SMM.\r
\r
  @retval The value of the original instruction pointer before it was hooked.\r
\r
**/\r
UINT64\r
EFIAPI\r
HookReturnFromSmm (\r
  IN UINTN              CpuIndex,\r
  SMRAM_SAVE_STATE_MAP  *CpuState,\r
  UINT64                NewInstructionPointer32,\r
  UINT64                NewInstructionPointer\r
  );\r
\r
/**\r
  Get the size of the SMI Handler in bytes.\r
\r
  @retval The size, in bytes, of the SMI Handler.\r
\r
**/\r
UINTN\r
EFIAPI\r
GetSmiHandlerSize (\r
  VOID\r
  );\r
\r
/**\r
  Install the SMI handler for the CPU specified by CpuIndex.  This function\r
  is called by the CPU that was elected as monarch during System Management\r
  Mode initialization.\r
\r
  @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.\r
                        The value must be between 0 and the NumberOfCpus field\r
                        in the System Management System Table (SMST).\r
  @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.\r
  @param[in] SmiStack   The stack to use when an SMI is processed by the\r
                        the CPU specified by CpuIndex.\r
  @param[in] StackSize  The size, in bytes, if the stack used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] GdtBase    The base address of the GDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtBase    The base address of the IDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] Cr3        The base address of the page tables to use when an SMI\r
                        is processed by the CPU specified by CpuIndex.\r
**/\r
VOID\r
EFIAPI\r
InstallSmiHandler (\r
  IN UINTN   CpuIndex,\r
  IN UINT32  SmBase,\r
  IN VOID    *SmiStack,\r
  IN UINTN   StackSize,\r
  IN UINTN   GdtBase,\r
  IN UINTN   GdtSize,\r
  IN UINTN   IdtBase,\r
  IN UINTN   IdtSize,\r
  IN UINT32  Cr3\r
  );\r
\r
/**\r
  Search module name by input IP address and output it.\r
\r
  @param CallerIpAddress   Caller instruction pointer.\r
\r
**/\r
VOID\r
DumpModuleInfoByIp (\r
  IN  UINTN              CallerIpAddress\r
  );\r
\r
/**\r
  This function sets memory attribute according to MemoryAttributesTable.\r
**/\r
VOID\r
SetMemMapAttributes (\r
  VOID\r
  );\r
\r
/**\r
  This function sets UEFI memory attribute according to UEFI memory map.\r
**/\r
VOID\r
SetUefiMemMapAttributes (\r
  VOID\r
  );\r
\r
/**\r
  Return if the Address is forbidden as SMM communication buffer.\r
\r
  @param[in] Address the address to be checked\r
\r
  @return TRUE  The address is forbidden as SMM communication buffer.\r
  @return FALSE The address is allowed as SMM communication buffer.\r
**/\r
BOOLEAN\r
IsSmmCommBufferForbiddenAddress (\r
  IN UINT64  Address\r
  );\r
\r
/**\r
  This function caches the UEFI memory map information.\r
**/\r
VOID\r
GetUefiMemoryMap (\r
  VOID\r
  );\r
\r
/**\r
  This function sets memory attribute for page table.\r
**/\r
VOID\r
SetPageTableAttributes (\r
  VOID\r
  );\r
\r
/**\r
  Return page table base.\r
\r
  @return page table base.\r
**/\r
UINTN\r
GetPageTableBase (\r
  VOID\r
  );\r
\r
/**\r
  This function sets the attributes for the memory region specified by BaseAddress and\r
  Length from their current attributes to the attributes specified by Attributes.\r
\r
  @param[in]   BaseAddress      The physical address that is the start address of a memory region.\r
  @param[in]   Length           The size in bytes of the memory region.\r
  @param[in]   Attributes       The bit mask of attributes to set for the memory region.\r
  @param[out]  IsSplitted       TRUE means page table splitted. FALSE means page table not splitted.\r
\r
  @retval EFI_SUCCESS           The attributes were set for the memory region.\r
  @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by\r
                                BaseAddress and Length cannot be modified.\r
  @retval EFI_INVALID_PARAMETER Length is zero.\r
                                Attributes specified an illegal combination of attributes that\r
                                cannot be set together.\r
  @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of\r
                                the memory resource range.\r
  @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory\r
                                resource range specified by BaseAddress and Length.\r
                                The bit mask of attributes is not support for the memory resource\r
                                range specified by BaseAddress and Length.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmSetMemoryAttributesEx (\r
  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
  IN  UINT64                                     Length,\r
  IN  UINT64                                     Attributes,\r
  OUT BOOLEAN                                    *IsSplitted  OPTIONAL\r
  );\r
\r
/**\r
  This function clears the attributes for the memory region specified by BaseAddress and\r
  Length from their current attributes to the attributes specified by Attributes.\r
\r
  @param[in]   BaseAddress      The physical address that is the start address of a memory region.\r
  @param[in]   Length           The size in bytes of the memory region.\r
  @param[in]   Attributes       The bit mask of attributes to clear for the memory region.\r
  @param[out]  IsSplitted       TRUE means page table splitted. FALSE means page table not splitted.\r
\r
  @retval EFI_SUCCESS           The attributes were cleared for the memory region.\r
  @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by\r
                                BaseAddress and Length cannot be modified.\r
  @retval EFI_INVALID_PARAMETER Length is zero.\r
                                Attributes specified an illegal combination of attributes that\r
                                cannot be set together.\r
  @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of\r
                                the memory resource range.\r
  @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory\r
                                resource range specified by BaseAddress and Length.\r
                                The bit mask of attributes is not support for the memory resource\r
                                range specified by BaseAddress and Length.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmClearMemoryAttributesEx (\r
  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
  IN  UINT64                                     Length,\r
  IN  UINT64                                     Attributes,\r
  OUT BOOLEAN                                    *IsSplitted  OPTIONAL\r
  );\r
\r
/**\r
  This API provides a way to allocate memory for page table.\r
\r
  This API can be called more once to allocate memory for page tables.\r
\r
  Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL\r
  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is\r
  returned.\r
\r
  @param  Pages                 The number of 4 KB pages to allocate.\r
\r
  @return A pointer to the allocated buffer or NULL if allocation fails.\r
\r
**/\r
VOID *\r
AllocatePageTableMemory (\r
  IN UINTN           Pages\r
  );\r
\r
/**\r
  Allocate pages for code.\r
\r
  @param[in]  Pages Number of pages to be allocated.\r
\r
  @return Allocated memory.\r
**/\r
VOID *\r
AllocateCodePages (\r
  IN UINTN           Pages\r
  );\r
\r
/**\r
  Allocate aligned pages for code.\r
\r
  @param[in]  Pages                 Number of pages to be allocated.\r
  @param[in]  Alignment             The requested alignment of the allocation.\r
                                    Must be a power of two.\r
                                    If Alignment is zero, then byte alignment is used.\r
\r
  @return Allocated memory.\r
**/\r
VOID *\r
AllocateAlignedCodePages (\r
  IN UINTN            Pages,\r
  IN UINTN            Alignment\r
  );\r
\r
\r
//\r
// S3 related global variable and function prototype.\r
//\r
\r
extern BOOLEAN                mSmmS3Flag;\r
\r
/**\r
  Initialize SMM S3 resume state structure used during S3 Resume.\r
\r
  @param[in] Cr3    The base address of the page tables to use in SMM.\r
\r
**/\r
VOID\r
InitSmmS3ResumeState (\r
  IN UINT32  Cr3\r
  );\r
\r
/**\r
  Get ACPI CPU data.\r
\r
**/\r
VOID\r
GetAcpiCpuData (\r
  VOID\r
  );\r
\r
/**\r
  Restore SMM Configuration in S3 boot path.\r
\r
**/\r
VOID\r
RestoreSmmConfigurationInS3 (\r
  VOID\r
  );\r
\r
/**\r
  Get ACPI S3 enable flag.\r
\r
**/\r
VOID\r
GetAcpiS3EnableFlag (\r
  VOID\r
  );\r
\r
/**\r
  Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r
\r
  @param[in] ApHltLoopCode          The address of the safe hlt-loop function.\r
  @param[in] TopOfStack             A pointer to the new stack to use for the ApHltLoopCode.\r
  @param[in] NumberToFinishAddress  Address of Semaphore of APs finish count.\r
\r
**/\r
VOID\r
TransferApToSafeState (\r
  IN UINTN  ApHltLoopCode,\r
  IN UINTN  TopOfStack,\r
  IN UINTN  NumberToFinishAddress\r
  );\r
\r
#endif\r