Waiting for redeye so I added some memory map comments to ArmEb.h. Also fixed assembl...

[mirror_edk2.git] / ArmEbPkg / Include / ArmEb / ArmEb.h

diff --git a/ArmEbPkg/Include/ArmEb/ArmEb.h b/ArmEbPkg/Include/ArmEb/ArmEb.h
index f855e6379d2f1a3f8e23458a32af34c032f93f8d..4eb0dec342a7249ffc9b8a4513fe7b31837044a4 100755 (executable)
--- a/ArmEbPkg/Include/ArmEb/ArmEb.h
+++ b/ArmEbPkg/Include/ArmEb/ArmEb.h
@@ -17,4 +17,86 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <ArmEb/ArmEbUart.h>\r
 #include <ArmEb/ArmEbTimer.h>\r
 \r
+///\r
+/// ARM EB Memory Map\r
+///\r
+// 0x00000000 - 0x0FFFFFFF SDRAM 256MB\r
+// 0x10000000 - 0x100FFFFF System FPGA (config registers) 1MB\r
+//   0x10000000\960x10000FFF  4KB    System registers \r
+//   0x10001000\960x10001FFF  4KB    System controller \r
+//   0x10002000\960x10002FFF  4KB    Two-Wire Serial Bus Interface \r
+//   0x10003000\960x10003FFF  4KB    Reserved \r
+//   0x10004000\960x10004FFF  4KB    Advanced Audio CODEC Interface \r
+//   0x10005000\960x10005FFF  4KB    MultiMedia Card Interface (MCI) \r
+//   0x10006000\960x10006FFF  4KB    Keyboard/Mouse Interface 0 \r
+//   0x10007000\960x10007FFF  4KB    Keyboard/Mouse Interface 1 \r
+//   0x10008000\960x10008FFF  4KB    Character LCD Interface \r
+//   0x10009000\960x10009FFF  4KB    UART 0 Interface \r
+//   0x1000A000\960x1000AFFF  4KB    UART 1 Interface \r
+//   0x1000B000\960x1000BFFF  4KB    UART 2 Interface \r
+//   0x1000C000\960x1000CFFF  4KB    UART 3 Interface \r
+//   0x1000D000\960x1000DFFF  4KB    Synchronous Serial Port Interface \r
+//   0x1000E000\960x1000EFFF  4KB    Smart Card Interface \r
+//   0x1000F000\960x1000FFFF  4KB    Reserved \r
+//   0x10010000\960x10010FFF  4KB    Watchdog Interface \r
+//   0x10011000\960x10011FFF  4KB    Timer modules 0 and 1 interface (Timer 1 starts at 0x10011020)\r
+//   0x10012000\960x10012FFF  4KB    Timer modules 2 and 3 interface (Timer 3 starts at 0x10012020)\r
+//   0x10013000\960x10013FFF  4KB    GPIO Interface 0 \r
+//   0x10014000\960x10014FFF  4KB    GPIO Interface 1 \r
+//   0x10015000\960x10015FFF  4KB    GPIO Interface 2 (miscellaneous onboard I/O) \r
+//   0x10016000\960x10016FFF  4KB    Reserved \r
+//   0x10017000\960x10017FFF  4KB    Real Time Clock Interface \r
+//   0x10018000\960x10018FFF  4KB    Dynamic Memory Controller configuration \r
+//   0x10019000\960x10019FFF  4KB    PCI controller configuration registers \r
+//   0x1001A000\960x1001FFFF  24KB   Reserved \r
+//   0x10020000\960x1002FFFF  64KB   Color LCD Controller \r
+//   0x10030000\960x1003FFFF  64KB   DMA Controller configuration registers \r
+//   0x10040000\960x1004FFFF  64KB   Generic Interrupt Controller 1 (nIRQ for tile 1) \r
+//   0x10050000\960x1005FFFF  64KB   Generic Interrupt Controller 2 (nFIQ for tile 1) \r
+//   0x10060000\960x1006FFFF  64KB   Generic Interrupt Controller 3 (nIRQ for tile 2) \r
+//   0x10070000\960x1007FFFF  64KB   Generic Interrupt Controller 4 (nFIQ for tile 2) \r
+//   0x10080000\960x1008FFFF  64KB   Static Memory Controller configuration registers \r
+//   0x100A0000\960x100EFFFF  448MB  Reserved \r
+//   0x10090000\960x100FFFFF  64KB   Debug Access Port (DAP) \r
+// 0x10100000 - 0x100FFFFF Reserved 3MB\r
+// 0x10400000 - 0x17FFFFFF System FPGA 124MB\r
+// 0x18000000 - 0x1FFFFFFF Logic Tile 1 128MB\r
+// 0x20000000 - 0x3FFFFFFF Reserved 512MB\r
+// 0x40000000 - 0x7FFFFFFF System FPGA 1GB\r
+//   0x40000000\960x43FFFFFF   CS0 NOR flash (nNOR_CS1) \r
+//   0x44000000\960x47FFFFFF   CS1 NOR flash (nNOR_CS2) \r
+//   0x48000000\960x4BFFFFFF   CS2 SRAM (nSRAMCS) \r
+//   0x4C000000\960x4DFFFFFF   CS3 Config flash \r
+//   0x4E000000\960x4EFFFFFF   Ethernet \r
+//   0x4F000000\960x4FFFFFFF   USB \r
+//   0x50000000\960x53FFFFFF   CS4 (nEXPCS) PISMO (nCS0) \r
+//   0x54000000\960x57FFFFFF   CS5 (nSTATICCS4) PISMO (nCS1) \r
+//   0x58000000\960x5BFFFFFF   CS6 (nSTATICCS5) PISMO (nCS2) \r
+//   0x5C000000\960x5FFFFFFF   CS7 (nSTATICCS6) PISMO (nCS3) \r
+//   0x61000000\960x61FFFFFF   PCI SelfCfg window \r
+//   0x62000000\960x62FFFFFF   PCI Cfg window \r
+//   0x63000000\960x63FFFFFF   PCI I/O window\r
+//   0x64000000\960x67FFFFFF   PCI memory window 0 \r
+//   0x68000000\960x6BFFFFFF   PCI memory window 1 \r
+//   0x6C000000\960x6FFFFFFF   PCI memory window 2 \r
+//   0x70000000 - 0x7FFFFFFF   DRAM Mirror\r
+// 0x80000000 - 0xFFFFFFFF Logic Tile site 2 2GB\r
+\r
+//\r
+// At reset EB_DRAM_BASE is alaised to EB_CS0_NOR_BASE\r
+//\r
+#define EB_DRAM_BASE          0x00000000   // 256 MB DRAM\r
+#define EB_CONFIG_BASE        0x10000000\r
+\r
+#define EB_CSO_NOR_BASE       0x40000000   // 64 MB NOR FLASH\r
+#define EB_CS1_NOR_BASE       0x44000000   // 64 MB NOR FLASH\r
+#define EB_CS2_SRAM           0x48000000   //  2 MB of SRAM\r
+#define EB_CS3_CONFIG_FLASH   0x4c000000   //  8 MB Config FLASH for FPGA. Not to be used by application code\r
+#define EB_CS3_ETHERNET       0x4e000000   // 16 MB Ethernet controller\r
+#define EB_CS4_PISMO_CS0      0x50000000   // Expansion  CS0\r
+#define EB_CS5_PISMO_CS0      0x54000000   // Expansion  CS0\r
+#define EB_CS6_PISMO_CS0      0x58000000   // Expansion  CS0\r
+\r
+#define EB_DRAM_REMAP_BASE    0x70000000   // if REMAPSTAT is HIGH alais of EB_DRAM_BASE\r
+\r
 #endif \r