ArmPkg/ArmV7Mmu.h: Added masks to extract attributes from Section and Page entries

[mirror_edk2.git] / ArmPkg / ArmPkg.dec

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index e664f8626a4ca96461b6801f15176821cefe5204..39f264251bb13038a09705cd498ecaab1b7d680e 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -128,15 +128,7 @@
   # - BIT9 : SIF - Secure Instruction Fetch\r
   # 0x31 = NS | EA | FW\r
   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
-  \r
-  # Non Secure Access Control Register\r
-  # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
-  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 \r
-  # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
-  # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
-  # 0xC00 = cp10 | cp11\r
-  gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
-  \r
+\r
   # System Memory (DRAM): These PCDs define the region of in-built system memory\r
   # Some platforms can get DRAM extensions, these additional regions will be declared\r
   # to UEFI by ArmPLatformPlib   \r
@@ -147,10 +139,6 @@
   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
   # The Primary Core is ClusterId[0] & CoreId[0] \r
   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
-  # Number of the CPU Interface for the Primary Core (eg: The number for the CPU0 of\r
-  # Cluster1 might be 4 if the implementer had followed the convention: Cpu Interface\r
-  # = 4 * Cluster)\r
-  gArmTokenSpaceGuid.PcdGicPrimaryCoreId|0|UINT32|0x00000043\r
 \r
   #\r
   # ARM L2x0 PCDs\r
@@ -185,3 +173,26 @@
   gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023\r
   # The FDT blob must be loaded at a 64bit aligned address.\r
   gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026\r
+\r
+  # Non Secure Access Control Register\r
+  # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
+  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
+  # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
+  # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
+  # 0xC00 = cp10 | cp11\r
+  gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
+\r
+[PcdsFixedAtBuild.AARCH64]\r
+  # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
+  #        Mode Description              Bits\r
+  # NS EL2 SP2 all interupts disabled =  0x3c9\r
+  # NS EL1 SP1 all interupts disabled =  0x3c5\r
+  # Other modes include using SP0 or switching to Aarch32, but these are\r
+  # not currently supported.\r
+  gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
+  # If the fixed FDT address is not available, then it should be loaded above the kernel.\r
+  # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.\r
+  # (see the kernel doc: Documentation/arm64/booting.txt)\r
+  gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023\r
+  # The FDT blob must be loaded at a 2MB aligned address.\r
+  gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r