ArmPkg/PL390Gic: Introduced PcdGicSgiIntId to define which SGI is used for core synch...

[mirror_edk2.git] / ArmPkg / ArmPkg.dec

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index d28d78316040700511764bb00247aa32d9ebd39e..65d42748773ac182ff2c208c120cbe64d3cf3e53 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -65,9 +65,9 @@
   # it has been configured by the CPU DXE\r
   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
   \r
-  gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered|FALSE|BOOLEAN|0x00000025\r
-\r
 [PcdsFixedAtBuild.common]\r
+  gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
+\r
   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r
   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r
@@ -83,6 +83,7 @@
   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
   gArmTokenSpaceGuid.PcdGicNumInterrupts|96|UINT32|0x00000023\r
+  gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
 \r
   #\r
   # ARM Secure Firmware PCDs\r
@@ -99,6 +100,34 @@
   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D\r
   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
+  \r
+  #\r
+  # ARM Security Extension\r
+  #\r
+  \r
+  # Secure Configuration Register\r
+  # - BIT0 : NS - Non Secure bit \r
+  # - BIT1 : IRQ Handler\r
+  # - BIT2 : FIQ Handler\r
+  # - BIT3 : EA - External Abort\r
+  # - BIT4 : FW - F bit writable\r
+  # - BIT5 : AW - A bit writable\r
+  # - BIT6 : nET - Not Early Termination\r
+  # - BIT7 : SCD - Secure Monitor Call Disable\r
+  # - BIT8 : HCE - Hyp Call enable\r
+  # - BIT9 : SIF - Secure Instruction Fetch\r
+  # 0x31 = NS | EA | FW\r
+  gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
+  \r
+  # Non Secure Access Control Register\r
+  # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
+  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 \r
+  # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
+  # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
+  # 0xC00 = cp10 | cp11\r
+  gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
+  \r
+  gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
 \r
   # System Memory (DRAM): These PCDs define the region of in-built system memory\r
   # Some platforms can get DRAM extensions, these additional regions will be declared\r
@@ -111,16 +140,6 @@
   # The Primary Core is ClusterId[0] & CoreId[0] \r
   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
 \r
-  #\r
-  # ARM MPCore MailBox PCDs\r
-  #\r
-  # Address to Set/Get to Mailbox in Multicore system\r
-  gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress|0|UINT32|0x00000017\r
-  gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress|0|UINT32|0x00000018\r
-  # Address/Value to clear Mailbox in Multicore system\r
-  gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress|0|UINT32|0x00000019\r
-  gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue|0|UINT32|0x0000001A\r
-\r
   #\r
   # ARM L2x0 PCDs\r
   #\r
@@ -141,3 +160,10 @@
   # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
   gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r
 \r
+  #\r
+  # ARM Architectural Timer\r
+  #\r
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
+  # ARM Architectural Timer Interrupt(GIC PPI) number\r
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035  \r
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r