+ \r
+ #\r
+ # ARM PL390 General Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
+ gArmTokenSpaceGuid.PcdGicNumInterrupts|96|UINT32|0x00000023\r
+\r
+ #\r
+ # ARM Secure Firmware PCDs\r
+ #\r
+ gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015\r
+ gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
+ gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F\r
+ gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
+\r
+ #\r
+ # ARM Normal (or Non Secure) Firmware PCDs\r
+ #\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B\r
+ gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D\r
+ gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
+ \r
+ #\r
+ # ARM Security Extension\r
+ #\r
+ \r
+ # Secure Configuration Register\r
+ # - BIT0 : NS - Non Secure bit \r
+ # - BIT1 : IRQ Handler\r
+ # - BIT2 : FIQ Handler\r
+ # - BIT3 : EA - External Abort\r
+ # - BIT4 : FW - F bit writable\r
+ # - BIT5 : AW - A bit writable\r
+ # - BIT6 : nET - Not Early Termination\r
+ # - BIT7 : SCD - Secure Monitor Call Disable\r
+ # - BIT8 : HCE - Hyp Call enable\r
+ # - BIT9 : SIF - Secure Instruction Fetch\r
+ # 0x31 = NS | EA | FW\r
+ gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
+ \r
+ # Non Secure Access Control Register\r
+ # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
+ # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 \r
+ # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
+ # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
+ # 0xC00 = cp10 | cp11\r
+ gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
+ \r
+ gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
+\r
+ # System Memory (DRAM): These PCDs define the region of in-built system memory\r
+ # Some platforms can get DRAM extensions, these additional regions will be declared\r
+ # to UEFI by ArmPLatformPlib \r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A\r
+\r
+ # Use ClusterId + CoreId to identify the PrimaryCore\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
+ # The Primary Core is ClusterId[0] & CoreId[0] \r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
+\r
+ #\r
+ # ARM L2x0 PCDs\r
+ #\r
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r
+ \r
+ #\r
+ # ARM PL390 General Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000001C\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000001D\r
+ \r
+ # \r
+ # BdsLib\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E\r
+ # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory\r
+ gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F\r
+ # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
+ gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r
+\r
+ #\r
+ # ARM Architectural Timer\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
+ # ARM Architectural Timer Interrupt(GIC PPI) number\r
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035 \r
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r