# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h\r
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
- \r
+ ArmGicArchLib|Include/Library/ArmGicArchLib.h\r
+\r
[Guids.common]\r
gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
\r
# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
# it has been configured by the CPU DXE\r
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
- \r
- # Define if the Power State Coordination Interface (PSCI) is supported by the Platform Trusted Firmware\r
- gArmTokenSpaceGuid.PcdArmPsciSupport|FALSE|BOOLEAN|0x00000033\r
- \r
+\r
+ # Define if the spin-table mechanism is used by the secondary cores when booting\r
+ # Linux (instead of PSCI)\r
+ gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033\r
+\r
+ # Define if the GICv3 controller should use the GICv2 legacy\r
+ gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
+\r
+[PcdsFeatureFlag.ARM]\r
+ # Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r
+ # TRUE may be appropriate to fix performance problems if you don't care about\r
+ # hardware coherency (i.e., no virtualization or cache coherent DMA)\r
+ gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r
+\r
[PcdsFixedAtBuild.common]\r
gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
\r
gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r
\r
gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002\r
- gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003\r
+ # This PCD will free the unallocated buffers if their size reach this threshold.\r
+ # We set the default value to 512MB.\r
+ gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003\r
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004\r
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
- \r
- #\r
- # ARM General Interrupt Controller\r
- #\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
- gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
\r
#\r
# ARM Secure Firmware PCDs\r
#\r
- gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015\r
+ gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015\r
gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
- gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F\r
+ gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r
gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
\r
- #\r
- # ARM Normal (or Non Secure) Firmware PCDs\r
- #\r
- gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B\r
- gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
- gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D\r
- gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
- \r
#\r
# ARM Hypervisor Firmware PCDs\r
- # \r
+ #\r
gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r
gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r
gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r
gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r
\r
- # System Memory (DRAM): These PCDs define the region of in-built system memory\r
- # Some platforms can get DRAM extensions, these additional regions will be declared\r
- # to UEFI by ArmPLatformPlib \r
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
- gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
-\r
# Use ClusterId + CoreId to identify the PrimaryCore\r
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
- # The Primary Core is ClusterId[0] & CoreId[0] \r
+ # The Primary Core is ClusterId[0] & CoreId[0]\r
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
\r
#\r
# ARM L2x0 PCDs\r
#\r
gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r
- \r
- # \r
+\r
+ #\r
# BdsLib\r
#\r
- gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E\r
# The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory\r
gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F\r
+ # Maximum file size for TFTP servers that do not support 'tsize' extension\r
+ gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000\r
\r
#\r
- # ARM Architectural Timer\r
+ # ARM Normal (or Non Secure) Firmware PCDs\r
#\r
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
- # ARM Architectural Timer Interrupt(GIC PPI) number\r
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035 \r
- gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
+ gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
+ gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
+\r
+[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r
\r
[PcdsFixedAtBuild.ARM]\r
#\r
\r
# By default we do transition to EL2 non-secure mode with Stack for EL2.\r
# Mode Description Bits\r
- # NS EL2 SP2 all interupts disabled = 0x3c9\r
- # NS EL1 SP1 all interupts disabled = 0x3c5\r
+ # NS EL2 SP2 all interrupts disabled = 0x3c9\r
+ # NS EL1 SP1 all interrupts disabled = 0x3c5\r
# Other modes include using SP0 or switching to Aarch32, but these are\r
# not currently supported.\r
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023\r
# The FDT blob must be loaded at a 2MB aligned address.\r
gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r
+\r
+\r
+#\r
+# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r
+# redefined when using UEFI in a context of virtual machine.\r
+#\r
+[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
+\r
+ # System Memory (DRAM): These PCDs define the region of in-built system memory\r
+ # Some platforms can get DRAM extensions, these additional regions will be declared\r
+ # to UEFI by ArmPlatformLib\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
+\r
+[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
+ #\r
+ # ARM Architectural Timer\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
+\r
+ # ARM Architectural Timer Interrupt(GIC PPI) numbers\r
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r
+\r
+ #\r
+ # ARM Generic Watchdog\r
+ #\r
+\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000007\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000008\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r
+\r
+ #\r
+ # ARM Generic Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
+ # Base address for the GIC Redistributor region that contains the boot CPU\r
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT32|0x0000000E\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
+ gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
projects / mirror_edk2.git / blobdiff