UefiCpuPkg/MpLib.c: Load microcode before mtrr sync per IA32 SDM

[mirror_edk2.git] / ArmPkg / Drivers / ArmCpuLib / ArmCortexA5xLib / ArmCortexA5xLib.c

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
index d13c7fd6fae210cb168167628f39566d24dc9227..3d39acd50c044e63f15220aaa69963cda940bd9c 100644 (file)
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
@@ -1,6 +1,6 @@
 /** @file\r
 \r
-  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
@@ -15,9 +15,8 @@
 #include <Base.h>\r
 #include <Library/ArmLib.h>\r
 #include <Library/ArmCpuLib.h>\r
-#include <Library/ArmArchTimerLib.h>\r
+#include <Library/ArmGenericTimerCounterLib.h>\r
 #include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
 #include <Library/PcdLib.h>\r
 \r
 #include <Chipset/ArmCortexA5x.h>\r
@@ -33,13 +32,24 @@ ArmCpuSetup (
 \r
   // Note: System Counter frequency can only be set in Secure privileged mode,\r
   // if security extensions are implemented.\r
-  ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));\r
+  ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));\r
 \r
   if (ArmIsMpCore ()) {\r
     // Turn on SMP coherency\r
-    ArmSetAuxCrBit (A5X_FEATURE_SMP);\r
+    ArmSetCpuExCrBit (A5X_FEATURE_SMP);\r
   }\r
 \r
+  //\r
+  // If CPU is CortexA57 r0p0 apply Errata workarounds\r
+  //\r
+  if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==\r
+                         ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {\r
+\r
+    // Errata 806969: DisableLoadStoreWB (1ULL << 49)\r
+    // Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate  (1ULL << 44)\r
+    // Errata 814670: disable DMB nullification (1ULL << 58)\r
+    ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );\r
+  }\r
 }\r
 \r
 VOID\r
@@ -48,3 +58,27 @@ ArmCpuSetupSmpNonSecure (
   )\r
 {\r
 }\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetCpuExCrBit (\r
+  IN  UINT64    Bits\r
+  )\r
+{\r
+  UINT64 Value;\r
+  Value =  ArmReadCpuExCr ();\r
+  Value |= Bits;\r
+  ArmWriteCpuExCr (Value);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmUnsetCpuExCrBit (\r
+  IN  UINT64    Bits\r
+  )\r
+{\r
+  UINT64 Value;\r
+  Value = ArmReadCpuExCr ();\r
+  Value &= ~Bits;\r
+  ArmWriteCpuExCr (Value);\r
+}\r