UefiCpuPkg/MpLib.c: Load microcode before mtrr sync per IA32 SDM

[mirror_edk2.git] / ArmPkg / Drivers / ArmCpuLib / ArmCortexA9Lib / ArmCortexA9Helper.S

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S
index 0d6a62b7400271f4fb6b8d24b318fdcf766b8894..365d57d7e8bd0f1f1497b8c26f7b7df6e63403ea 100644 (file)
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S
@@ -1,5 +1,5 @@
 //\r
-//  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
 //\r
 //  This program and the accompanying materials\r
 //  are licensed and made available under the terms and conditions of the BSD License\r
@@ -11,42 +11,13 @@
 //\r
 //\r
 \r
-#include <Library/ArmCpuLib.h>\r
-#include <Chipset/ArmCortexA9.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmCpuSynchronizeWait)\r
-GCC_ASM_EXPORT(ArmGetScuBaseAddress)\r
-GCC_ASM_IMPORT(CArmCpuSynchronizeWait)\r
-\r
-// VOID\r
-// ArmCpuSynchronizeWait (\r
-//   IN ARM_CPU_SYNCHRONIZE_EVENT   Event\r
-//   );\r
-ASM_PFX(ArmCpuSynchronizeWait):\r
-  cmp   r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
-  // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
-  beq   ArmWaitScuEnabled\r
-  b     CArmCpuSynchronizeWait\r
+#include <AsmMacroIoLib.h>\r
 \r
 // IN None\r
 // OUT r0 = SCU Base Address\r
-ASM_PFX(ArmGetScuBaseAddress):\r
+ASM_FUNC(ArmGetScuBaseAddress)\r
   // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
   // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
   // offset 0x0000 from the Private Memory Region.\r
   mrc   p15, 4, r0, c15, c0, 0\r
   bx  lr\r
-\r
-ASM_PFX(ArmWaitScuEnabled):\r
-  // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
-  // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
-  // offset 0x0000 from the Private Memory Region.\r
-  mrc   p15, 4, r0, c15, c0, 0\r
-  add   r0, r0, #A9_SCU_CONTROL_OFFSET\r
-  ldr   r0, [r0]\r
-  cmp   r0, #1\r
-  bne   ArmWaitScuEnabled\r
-  bx    lr\r