//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
//\r
//\r
\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/ArmCpuLib.h>\r
-#include <Chipset/ArmCortexA9.h>\r
-\r
+ INCLUDE AsmMacroExport.inc\r
INCLUDE AsmMacroIoLib.inc\r
\r
- EXPORT ArmCpuSynchronizeWait\r
- EXPORT ArmGetScuBaseAddress\r
- IMPORT CArmCpuSynchronizeWait\r
\r
PRESERVE8\r
- AREA ArmCortexA9Helper, CODE, READONLY\r
-\r
-// VOID\r
-// ArmCpuSynchronizeWait (\r
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
-// );\r
-ArmCpuSynchronizeWait\r
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
- beq ArmWaitScuEnabled\r
- // Case when the stack has been set up\r
- push {r1,lr}\r
- LoadConstantToReg (CArmCpuSynchronizeWait, r1)\r
- blx r1\r
- pop {r1,lr}\r
- bx lr\r
\r
// IN None\r
// OUT r0 = SCU Base Address\r
-ArmGetScuBaseAddress\r
+ RVCT_ASM_EXPORT ArmGetScuBaseAddress\r
// Read Configuration Base Address Register. ArmCBar cannot be called to get\r
// the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
// offset 0x0000 from the Private Memory Region.\r
mrc p15, 4, r0, c15, c0, 0\r
bx lr\r
\r
-ArmWaitScuEnabled\r
- // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- // offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- add r0, r0, #A9_SCU_CONTROL_OFFSET\r
- ldr r0, [r0]\r
- cmp r0, #1\r
- bne ArmWaitScuEnabled\r
- bx lr\r
-\r
END\r