ArmPlatformPkg/ArmPlatformLib: Added support for ArmPlatformIsPrimaryCore()

[mirror_edk2.git] / ArmPkg / Drivers / ArmCpuLib / ArmCortexA9Lib / ArmCortexA9Lib.c

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c
index 7c5c3ee6a99b9f254c2434583c216f84db7dd4db..4fc6a08b9a942e8fa33d7525fbcd56a04e4a11fa 100644 (file)
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c
@@ -1,6 +1,6 @@
 /** @file\r
 \r
-  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
@@ -15,39 +15,12 @@
 #include <Base.h>\r
 #include <Library/ArmLib.h>\r
 #include <Library/ArmCpuLib.h>\r
-#include <Library/ArmGicLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
 #include <Library/IoLib.h>\r
 #include <Library/PcdLib.h>\r
 \r
 #include <Chipset/ArmCortexA9.h>\r
 \r
-VOID\r
-ArmCpuSynchronizeSignal (\r
-  IN ARM_CPU_SYNCHRONIZE_EVENT   Event\r
-  )\r
-{\r
-  if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {\r
-    // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be\r
-    // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot\r
-    // Mem as been initialized\r
-  } else {\r
-    // Send SGI to all Secondary core to wake them up from WFI state.\r
-    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
-  }\r
-}\r
-\r
-VOID\r
-CArmCpuSynchronizeWait (\r
-  IN ARM_CPU_SYNCHRONIZE_EVENT   Event\r
-  )\r
-{\r
-  // Waiting for the SGI from the primary core\r
-  ArmCallWFI ();\r
-\r
-  // Acknowledge the interrupt and send End of Interrupt signal.\r
-  ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
-}\r
-\r
 VOID\r
 ArmEnableScu (\r
   VOID\r
@@ -76,6 +49,9 @@ ArmCpuSetup (
 \r
   // If MPCore then Enable the SCU\r
   if (ArmIsMpCore()) {\r
+    // Signals the Cortex-A9 processor is taking part in coherency\r
+    ArmSetAuxCrBit (A9_FEATURE_SMP);\r
+\r
     ArmEnableScu ();\r
   }\r
 }\r
@@ -88,10 +64,8 @@ ArmCpuSetupSmpNonSecure (
 {\r
   INTN          ScuBase;\r
 \r
-  ArmSetAuxCrBit (A9_FEATURE_SMP);\r
-\r
   // Make the SCU accessible in Non Secure world\r
-  if (IS_PRIMARY_CORE(MpId)) {\r
+  if (ArmPlatformIsPrimaryCore (MpId)) {\r
     ScuBase = ArmGetScuBaseAddress();\r
 \r
     // Allow NS access to SCU register\r