ArmPkg/ArmGicLib: select GICv2 mode if SRE is present but unavailable

[mirror_edk2.git] / ArmPkg / Drivers / ArmGic / AArch64 / ArmGicArchLib.c

diff --git a/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c b/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
index 5a7837f43d9412a46e0e8e446d38b2ecdf45f914..9da69b2131e38326d766fbe4e4f8119739c34e11 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
+++ b/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
@@ -15,6 +15,8 @@
 #include <Library/ArmLib.h>\r
 #include <Library/ArmGicLib.h>\r
 \r
+#include "GicV3/ArmGicV3Lib.h"\r
+\r
 ARM_GIC_ARCH_REVISION\r
 EFIAPI\r
 ArmGicGetSupportedArchRevision (\r
@@ -28,7 +30,17 @@ ArmGicGetSupportedArchRevision (
   // driver requires SRE. If only Memory mapped access is available we try to\r
   // drive the GIC as a v2.\r
   if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {\r
-    return ARM_GIC_ARCH_REVISION_3;\r
+    // Make sure System Register access is enabled (SRE). This depends on the\r
+    // higher privilege level giving us permission, otherwise we will either\r
+    // cause an exception here, or the write doesn't stick in which case we need\r
+    // to fall back to the GICv2 MMIO interface.\r
+    // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started\r
+    // at the same exception level.\r
+    // It is the OS responsibility to set this bit.\r
+    ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);\r
+    if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) {\r
+      return ARM_GIC_ARCH_REVISION_3;\r
+    }\r
   }\r
 \r
   return ARM_GIC_ARCH_REVISION_2;\r