/** @file\r
*\r
-* Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2018, ARM Limited. All rights reserved.\r
*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+* SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
\r
\r
// Route the SPIs to the primary CPU. SPIs start at the INTID 32\r
for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {\r
- MmioWrite32 (\r
+ MmioWrite64 (\r
mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),\r
CpuTarget\r
);\r