Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>\r
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
\r
--*/\r
\r
#define TT_ATTR_INDX_INVALID ((UINT32)~0)\r
\r
+#define MIN_T0SZ 16\r
+#define BITS_PER_LEVEL 9\r
+\r
+STATIC\r
+VOID\r
+GetRootTranslationTableInfo (\r
+ IN UINTN T0SZ,\r
+ OUT UINTN *RootTableLevel,\r
+ OUT UINTN *RootTableEntryCount\r
+ )\r
+{\r
+ *RootTableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;\r
+ *RootTableEntryCount = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;\r
+}\r
+\r
+STATIC\r
+UINT64\r
+PageAttributeToGcdAttribute (\r
+ IN UINT64 PageAttributes\r
+ )\r
+{\r
+ UINT64 GcdAttributes;\r
+\r
+ switch (PageAttributes & TT_ATTR_INDX_MASK) {\r
+ case TT_ATTR_INDX_DEVICE_MEMORY:\r
+ GcdAttributes = EFI_MEMORY_UC;\r
+ break;\r
+ case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:\r
+ GcdAttributes = EFI_MEMORY_WC;\r
+ break;\r
+ case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:\r
+ GcdAttributes = EFI_MEMORY_WT;\r
+ break;\r
+ case TT_ATTR_INDX_MEMORY_WRITE_BACK:\r
+ GcdAttributes = EFI_MEMORY_WB;\r
+ break;\r
+ default:\r
+ DEBUG ((DEBUG_ERROR,\r
+ "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n",\r
+ PageAttributes));\r
+ ASSERT (0);\r
+ // The Global Coherency Domain (GCD) value is defined as a bit set.\r
+ // Returning 0 means no attribute has been set.\r
+ GcdAttributes = 0;\r
+ }\r
+\r
+ // Determine protection attributes\r
+ if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) ||\r
+ ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {\r
+ // Read only cases map to write-protect\r
+ GcdAttributes |= EFI_MEMORY_RO;\r
+ }\r
+\r
+ // Process eXecute Never attribute\r
+ if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0) {\r
+ GcdAttributes |= EFI_MEMORY_XP;\r
+ }\r
+\r
+ return GcdAttributes;\r
+}\r
+\r
STATIC\r
UINT64\r
GetFirstPageAttribute (\r
// Get the first entry of the table\r
FirstEntry = *FirstLevelTableAddress;\r
\r
- if ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {\r
+ if ((TableLevel != 3) && (FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {\r
// Only valid for Levels 0, 1 and 2\r
- ASSERT (TableLevel < 3);\r
\r
// Get the attribute of the subsequent table\r
return GetFirstPageAttribute ((UINT64*)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1);\r
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,\r
*StartGcdRegion,\r
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion,\r
- PageAttributeToGcdAttribute (EntryAttribute));\r
+ PageAttributeToGcdAttribute (*PrevEntryAttribute));\r
}\r
\r
// Start of the new region\r
\r
switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) {\r
case EFI_MEMORY_UC:\r
- ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY;\r
+ if (ArmReadCurrentEL () == AARCH64_EL2) {\r
+ ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;\r
+ } else {\r
+ ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;\r
+ }\r
break;\r
case EFI_MEMORY_WC:\r
ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
break;\r
case EFI_MEMORY_WT:\r
- ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH;\r
+ ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r
break;\r
case EFI_MEMORY_WB:\r
- ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK;\r
+ ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r
break;\r
default:\r
- DEBUG ((EFI_D_ERROR, "EfiAttributeToArmAttribute: 0x%lX attributes is not supported.\n", EfiAttributes));\r
- ASSERT (0);\r
- ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY;\r
+ ArmAttributes = TT_ATTR_INDX_MASK;\r
}\r
\r
// Set the access flag to match the block attributes\r
ArmAttributes |= TT_AF;\r
\r
// Determine protection attributes\r
- if (EfiAttributes & EFI_MEMORY_WP) {\r
+ if (EfiAttributes & EFI_MEMORY_RO) {\r
ArmAttributes |= TT_AP_RO_RO;\r
}\r
\r
BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress);\r
EntryType = *BlockEntry & TT_TYPE_MASK;\r
\r
- if (EntryType == TT_TYPE_TABLE_ENTRY) {\r
+ if ((TableLevel < 3) && (EntryType == TT_TYPE_TABLE_ENTRY)) {\r
NextTranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);\r
\r
// The entry is a page table, so we go to the next level\r
if (!EFI_ERROR(Status)) {\r
return EFI_SUCCESS;\r
}\r
+\r
+ // Now we processed the table move to the next entry\r
+ BlockEntry++;\r
} else if (EntryType == BlockEntryType) {\r
// We have found the BlockEntry attached to the address. We save its start address (the start\r
- // address might be before the 'BaseAdress') and attributes\r
+ // address might be before the 'BaseAddress') and attributes\r
*BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL(TableLevel) - 1);\r
*RegionLength = 0;\r
*RegionAttributes = *BlockEntry & TT_ATTRIBUTES_MASK;\r
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