\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
Copyright (c) 2011, ARM Limited. All rights reserved.\r
- \r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include <Guid/IdleLoopEvent.h>\r
\r
-BOOLEAN mInterruptState = FALSE;\r
-\r
+BOOLEAN mIsFlushingGCD;\r
\r
/**\r
- This function flushes the range of addresses from Start to Start+Length \r
- from the processor's data cache. If Start is not aligned to a cache line \r
- boundary, then the bytes before Start to the preceding cache line boundary \r
- are also flushed. If Start+Length is not aligned to a cache line boundary, \r
- then the bytes past Start+Length to the end of the next cache line boundary \r
- are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r
- supported. If the data cache is fully coherent with all DMA operations, then \r
- this function can just return EFI_SUCCESS. If the processor does not support \r
+ This function flushes the range of addresses from Start to Start+Length\r
+ from the processor's data cache. If Start is not aligned to a cache line\r
+ boundary, then the bytes before Start to the preceding cache line boundary\r
+ are also flushed. If Start+Length is not aligned to a cache line boundary,\r
+ then the bytes past Start+Length to the end of the next cache line boundary\r
+ are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be\r
+ supported. If the data cache is fully coherent with all DMA operations, then\r
+ this function can just return EFI_SUCCESS. If the processor does not support\r
flushing a range of the data cache, then the entire data cache can be flushed.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
@retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r
the processor's data cache.\r
- @retval EFI_UNSUPPORTEDT The processor does not support the cache flush type specified\r
+ @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified\r
by FlushType.\r
@retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r
from the processor's data cache.\r
default:\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
- This function enables interrupt processing by the processor. \r
+ This function enables interrupt processing by the processor.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
{\r
ArmEnableInterrupts ();\r
\r
- mInterruptState = TRUE;\r
return EFI_SUCCESS;\r
}\r
\r
{\r
ArmDisableInterrupts ();\r
\r
- mInterruptState = FALSE;\r
return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
- This function retrieves the processor's current interrupt state a returns it in \r
- State. If interrupts are currently enabled, then TRUE is returned. If interrupts \r
+ This function retrieves the processor's current interrupt state a returns it in\r
+ State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r
are currently disabled, then FALSE is returned.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- *State = mInterruptState;\r
+ *State = ArmGetInterruptState();\r
return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
This function generates an INIT on the processor. If this function succeeds, then the\r
- processor will be reset, and control will not be returned to the caller. If InitType is \r
- not supported by this processor, or the processor cannot programmatically generate an \r
- INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error \r
+ processor will be reset, and control will not be returned to the caller. If InitType is\r
+ not supported by this processor, or the processor cannot programmatically generate an\r
+ INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error\r
occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
/**\r
Callback function for idle events.\r
- \r
+\r
@param Event Event whose notification function is being invoked.\r
@param Context The pointer to the notification function's context,\r
which is implementation-dependent.\r
CpuGetTimerValue,\r
CpuSetMemoryAttributes,\r
0, // NumberOfTimers\r
- 4, // DmaBufferAlignment\r
+ 2048, // DmaBufferAlignment\r
};\r
\r
+STATIC\r
+VOID\r
+InitializeDma (\r
+ IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol\r
+ )\r
+{\r
+ CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();\r
+}\r
+\r
EFI_STATUS\r
CpuDxeInitialize (\r
IN EFI_HANDLE ImageHandle,\r
EFI_STATUS Status;\r
EFI_EVENT IdleLoopEvent;\r
\r
- InitializeExceptions (&mCpu); \r
- \r
+ InitializeExceptions (&mCpu);\r
+\r
+ InitializeDma (&mCpu);\r
+\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
- &mCpuHandle, \r
- &gEfiCpuArchProtocolGuid, &mCpu, \r
- &gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages,\r
+ &mCpuHandle,\r
+ &gEfiCpuArchProtocolGuid, &mCpu,\r
NULL\r
);\r
- \r
+\r
//\r
// Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r
// and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r
// after the protocol is installed\r
//\r
+ mIsFlushingGCD = TRUE;\r
SyncCacheConfig (&mCpu);\r
- \r
+ mIsFlushingGCD = FALSE;\r
+\r
// If the platform is a MPCore system then install the Configuration Table describing the\r
// secondary core states\r
if (ArmIsMpCore()) {\r
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