Patch from open source community for CryptoPkg to allow it to build for ARM using...

[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / Mmu.c

diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c
index 89bf88ed3b139e6f8823c8aec60fdb82503c3894..681ffdeb1e54af8582dc18ee98696b641f275099 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Mmu.c
@@ -426,7 +426,7 @@ SyncCacheConfig (
     } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) {\r
       Status = SyncCacheConfigPage (\r
           i,FirstLevelTable[i],\r
-          &NumberOfDescriptors, &MemorySpaceMap,\r
+          NumberOfDescriptors, MemorySpaceMap,\r
           &NextRegionBase,&NextRegionLength,&NextSectionAttributes);\r
       ASSERT_EFI_ERROR (Status);\r
     } else {\r
@@ -547,7 +547,7 @@ UpdatePageEntries (
   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
 \r
   // calculate number of 4KB page table entries to change\r
-  NumPageEntries = Length/SIZE_4KB;\r
+  NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;\r
   \r
   // iterate for the number of 4KB pages to change\r
   Offset = 0;\r
@@ -598,7 +598,7 @@ UpdatePageEntries (
       if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {\r
         // The current section mapping is cacheable so Clean/Invalidate the MVA of the page\r
         // Note assumes switch(Attributes), not ARMv7 possibilities\r
-        WriteBackInvalidateDataCacheRange (Mva, SIZE_4KB);\r
+        WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);\r
       }\r
 \r
       // Only need to update if we are changing the entry  \r
@@ -607,7 +607,7 @@ UpdatePageEntries (
     }\r
 \r
     Status = EFI_SUCCESS;\r
-    Offset += SIZE_4KB;\r
+    Offset += TT_DESCRIPTOR_PAGE_SIZE;\r
     \r
   } // end first level translation table loop\r
 \r
@@ -791,7 +791,7 @@ ConvertSectionToPages (
   }\r
 \r
   // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
-  WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, SIZE_4KB);\r
+  WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, TT_DESCRIPTOR_PAGE_SIZE);\r
 \r
   // formulate page table entry, Domain=0, NS=0\r
   PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
@@ -868,7 +868,7 @@ CpuSetMemoryAttributes (
   )\r
 {\r
   DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r
-  if ( ((BaseAddress & (SIZE_4KB-1)) != 0) || ((Length & (SIZE_4KB-1)) != 0)){\r
+  if ( ((BaseAddress & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0) || ((Length & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0)){\r
     // minimum granularity is SIZE_4KB (4KB on ARM)\r
     DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));\r
     return EFI_UNSUPPORTED;\r