Arm Packages: Fixed coding style/Line endings to follow EDK2 coding convention

[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / Mmu.c

diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c
index 681ffdeb1e54af8582dc18ee98696b641f275099..74794eb9453ca50403a53d1fae1995c2d286c205 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Mmu.c
@@ -543,49 +543,49 @@ UpdatePageEntries (
       return EFI_UNSUPPORTED;\r
   }\r
 \r
-  // obtain page table base\r
+  // Obtain page table base\r
   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
 \r
-  // calculate number of 4KB page table entries to change\r
+  // Calculate number of 4KB page table entries to change\r
   NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;\r
   \r
-  // iterate for the number of 4KB pages to change\r
+  // Iterate for the number of 4KB pages to change\r
   Offset = 0;\r
-  for(p=0; p<NumPageEntries; p++) {\r
-    // calculate index into first level translation table for page table value\r
+  for(p = 0; p < NumPageEntries; p++) {\r
+    // Calculate index into first level translation table for page table value\r
     \r
     FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
     ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
 \r
-    // read the descriptor from the first level page table\r
+    // Read the descriptor from the first level page table\r
     Descriptor = FirstLevelTable[FirstLevelIdx];\r
 \r
-    // does this descriptor need to be converted from section entry to 4K pages?\r
+    // Does this descriptor need to be converted from section entry to 4K pages?\r
     if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {\r
       Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
       if (EFI_ERROR(Status)) {\r
-        // exit for loop\r
+        // Exit for loop\r
         break; \r
       } \r
       \r
-      // re-read descriptor\r
+      // Re-read descriptor\r
       Descriptor = FirstLevelTable[FirstLevelIdx];\r
     }\r
 \r
-    // obtain page table base address\r
+    // Obtain page table base address\r
     PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);\r
 \r
-    // calculate index into the page table\r
+    // Calculate index into the page table\r
     PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
     ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);\r
 \r
-    // get the entry\r
+    // Get the entry\r
     CurrentPageTableEntry = PageTable[PageTableIndex];\r
 \r
-    // mask off appropriate fields\r
+    // Mask off appropriate fields\r
     PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r
 \r
-    // mask in new attributes and/or permissions\r
+    // Mask in new attributes and/or permissions\r
     PageTableEntry |= EntryValue;\r
 \r
     if (VirtualMask != 0) {\r
@@ -609,7 +609,7 @@ UpdatePageEntries (
     Status = EFI_SUCCESS;\r
     Offset += TT_DESCRIPTOR_PAGE_SIZE;\r
     \r
-  } // end first level translation table loop\r
+  } // End first level translation table loop\r
 \r
   return Status;\r
 }\r
@@ -815,23 +815,24 @@ SetMemoryAttributes (
   EFI_STATUS    Status;\r
   \r
   if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r
-    // is the base and length a multiple of 1 MB?\r
+    // Is the base and length a multiple of 1 MB?\r
     DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
     Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r
   } else {\r
-    // base and/or length is not a multiple of 1 MB\r
+    // Base and/or length is not a multiple of 1 MB\r
     DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
     Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r
   }\r
 \r
-  // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
+  // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
   // flush and invalidate pages\r
+  //TODO: Do we really need to invalidate the caches everytime we change the memory attributes ?\r
   ArmCleanInvalidateDataCache ();\r
-  \r
+\r
   ArmInvalidateInstructionCache ();\r
 \r
-  // invalidate all TLB entries so changes are synced\r
-  ArmInvalidateTlb (); \r
+  // Invalidate all TLB entries so changes are synced\r
+  ArmInvalidateTlb ();\r
 \r
   return Status;\r
 }\r